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MCP3911 Datasheet

Download or read online Microchip Technology MCP3911 3.3V Two-Channel Analog Front End pdf datasheet.



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3.3V Two-Channel Analog Front End
Features
• Two Synchronous Sampling 16/24-bit Resolution
Delta-Sigma A/D Converters
• 94.5 dB SINAD, -106.5 dBc Total Harmonic
Distortion (THD) (up to 35th harmonic), 111 dB
SFDR for Each Channel
• 2.7V - 3.6V AV
, DV
DD
DD
• Programmable Data Rate up to 125 ksps
- 4 MHz Maximum Sampling Frequency
• Oversampling Ratio up to 4096
• Ultra Low Power Shutdown Mode with <2 µA
• -122 dB Crosstalk between the Two Channels
• Low Drift 1.2V Internal Voltage Reference: 7 ppm/° C
• Differential Voltage Reference Input Pins
• High Gain PGA on Each Channel (up to 32V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Modulator Output Pins for Each
Channel
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication
• Low Power Consumption (8.9 mW at 3.3V,
5.6 mW at 3.3V in low-power mode, typical)
• Available in Small 20-lead QFN and SSOP Pack-
ages, Pin-to-pin Compatible with MCP3901
• Extended Temperature Range: -40° C to +125° C
Applications
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring
• Audio/Voice Recognition
© 2012 Microchip Technology Inc.
MCP3911
Description
The MCP3911 is a 2.7V to 3.6V dual channel Analog
Front End (AFE) containing two synchronous sampling
Delta-Sigma Analog-to-Digital Converters (ADC), two
PGAs, phase delay compensation block, low-drift
internal voltage reference, modulator output block,
digital offset and gain errors calibration registers, and
high-speed 20 MHz SPI compatible serial interface.
The MCP3911 ADCs are fully configurable with fea-
tures such as: 16/24-bit resolution, OSR from 32 to
4096, gain from 1x to 32x, independent shutdown and
reset, dithering and auto-zeroing. The communication
is largely simplified with the one-byte-long commands
including various continuous read/write modes that can
be accessed by the Direct Memory Access (DMA) of an
MCU, and with a separate data ready pin that can be
directly connected to an Interrupt Request (IRQ) input
of an MCU.
The MCP3911 is capable of interfacing a large variety
of voltage and current sensors including shunts,
current transformers, Rogowski coils and Hall effect
sensors.
Package Type
20-Lead
RESET
1
20
SDI
DV
2
19
SDO
SSOP
DD
3
18
AV
SCK
DD
CH0+
4
17
CS
OSC2
CH0-
5
16
OSC1/CLKI
CH1-
6
15
CH1+
DR
7
14
AGND
MDAT0
8
13
MDAT1
REFIN+/OUT
9
12
REFIN-
10
11
DGND
20-Lead
QFN
20
19 18 17
16
CH0+
1
CH0-
2
EP
21
3
CH1-
CH1+
4
5
AGND
10
6
7
8
9
15
SCK
14
CS
13
OSC2
12
OSC1/CLKI
11
DR
DS22286A-page 1

Summary of Contents

Page 1

... Audio/Voice Recognition © 2012 Microchip Technology Inc. MCP3911 Description The MCP3911 is a 2.7V to 3.6V dual channel Analog Front End (AFE) containing two synchronous sampling Delta-Sigma Analog-to-Digital Converters (ADC), two PGAs, phase delay compensation block, low-drift internal voltage reference, modulator output block, digital offset and gain errors calibration registers, and high-speed 20 MHz SPI compatible serial interface ...

Page 2

... MCP3911 Functional block diagram AVDD REFIN/OUT Voltage VREFEXT Reference Vref - REFIN- Vref- Vref CH0 CH0- - PGA Modulator CH1 CH1- - PGA Modulator DUAL ADC POR AVDD Monitoring AGND DS22286A-page 2 DVDD AMCLK DMCLK/DRCLK ANALOG DIGITAL 3 SINC OFFCAL_CH0 GAINCAL_CH0 1 SINC <23:0> <23:0> DATA_CH0 MOD<3:0> <23:0> ...

Page 3

... MHz 4 125 ksps -1 1 /-1 -600/GAIN 600/ GAIN -1 0.2 1 0.5 µV/° MCP3911 DV 2.7V to 3.6V, MCLK DD Test Conditions bits OSR 256 or greater For maximum condi- tion, BOOST<1:0> For maximum condi- tion, BOOST<1:0> 11, OSR 32 V All analog input channels, measured to AGND nA RESET<1:0>11, MCLK ...

Page 4

... MCP3911 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply MHz; PRE<1:0> 00; OSR 256; GAIN 1; VREFEXT0, CLKEXT1, AZ_FREQ0, DITHER<1:0>11, BOOST<1:0> 10; V 0V -40° 125° Sym Characteristic Gain Error Drift INL Integral Non-Linearity ...

Page 5

... MCP3911 2.7V to 3.6V, MCLK DD Test Conditions VREFEXT 0 VREFEXT0, SHUT- DOWN<1:0>11 VREFEXT 1 VREFEXT 1 REFIN- should be con- nected to AGND when VREFEXT0 CLKEXT 1, (Note 6) CLKEXT 0, (Note 6) (Note 6) BOOST<1:0>00 BOOST<1:0>01 BOOST<1:0>10 BOOST<1:0> 11 MCLK 4 MHz, proportional to MCLK MCLK 16 MHz, pro- ...

Page 6

... MCP3911 1.2 SERIAL INTERFACE CHARACTERISTICS TABLE 1-2: SERIAL DC CHARACTERISTICS TABLE Electrical Specifications: Unless otherwise indicated, all parameters apply at DV 125° 30pF, applies to all digital I/O. LOAD Sym Characteristics V High-level Input voltage IH V Low-level Input voltage IL I Input leakage current LI I Output leakage current ...

Page 7

... C -65 150 ° C 89.3 ° C/W 43 ° C/W ) must not exceed the absolute maximum specification of 150C MCP3911 2.7 to 3.6V -40° Units Test Conditions ns µs 2.7 to 3.6V 2 Conditions (Note 1) t CSH Mode 1,1 Mode 0,0 t DIS ...

Page 8

... MCP3911 CS t CSS Mode 1,1 Mode 0,0 SCK SDI MSB in SDO FIGURE 1-2: Serial Input Timing Diagram DODR SCK SDO FIGURE 1-3: Data Ready Pulse / Sampling Timing Diagram. DS22286A-page 8 f SCK LSB in HI CSD t CLE t t CLD CSH t DRP ...

Page 9

... H Timing Waveform for t DO SCK t DO SDO Timing Waveform for MDAT0/1 Modulator Output Function OSC1/CLKI MDAT FIGURE 1-4: Timing Diagrams, continued. © 2012 Microchip Technology Inc. Waveform for SDO DIS t DOMDAT MCP3911 DIS 90% HI-Z 10% DS22286A-page 9 ...

Page 10

... MCP3911 NOTES: DS22286A-page 10 © 2012 Microchip Technology Inc. ...

Page 11

... Total Harmonic Distortion (-dBc) FIGURE 2-3: THD Histogram. © 2012 Microchip Technology Inc. 3.3V 3.3V 25° C, MCLK 4 MHz; PRESCALE -0.5 dBFS @ 60 Hz, VREFEXT 0; CLKEXT 1, IN FIGURE 2-4: FIGURE 2-5: 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 Signal-to-Noise and Distortion Ratio (dB) FIGURE 2-6: MCP3911 Spectral Response. Spectral Response. SINAD Histogram. DS22286A-page 11 ...

Page 12

... MCP3911 Note: Unless otherwise indicated, AV OSR 256; GAIN 1; Dithering Maximum; V AZ_FREQ 0; BOOST 1X. 104.5 106 107.5 109 110.5 112 113.5 Spurious Free Dynamic Range (dBFS) FIGURE 2-7: Spurious Free Dynamic Range Histogram. 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 95.6 95.8 95.9 Signal to Noise Ratio (dB) FIGURE 2-8: SNR Histogram. 5000 Channel 1 4500 4000 ...

Page 13

... Dithering Minimum Dithering None 128 256 512 1024 2048 4096 Oversampling Ratio (OSR) FIGURE 2-15: SFDR vs. OSR. © 2012 Microchip Technology Inc. MCP3911 0 -10 -20 Boost 0.5x -30 Boost 0.66x -40 -50 -60 -70 Boost 1x -80 -90 90 -100 -110 -120 ...

Page 14

... MCP3911 Note: Unless otherwise indicated, AV OSR 256; GAIN 1; Dithering Maximum; V AZ_FREQ 0; BOOST 1X. 120 110 100 90 80 Boost 0.66x Boost Boost 0. Frequency (MHz) FIGURE 2-19: SFDR vs. MCLK. FIGURE 2-20: SINAD vs. GAIN. 120 110 OSR 4096 OSR 2048 100 ...

Page 15

... G2 80 G1 70 G4 G16 60 G -50 -25 100 125 150 FIGURE 2-30: MCP3911 100 125 150 Temperature (°C) SINAD vs. Temperature 100 125 150 Temperature (°C) SNR vs. Temperature 100 125 150 Temperature (°C) SFDR vs. Temperature. ...

Page 16

... MCP3911 Note: Unless otherwise indicated, AV OSR 256; GAIN 1; Dithering Maximum; V AZ_FREQ 0; BOOST 1X. 400 350 300 G32 250 G16 200 G8 150 G4 100 G2 G1 -50 -100 -50 - Temperature (°C) FIGURE 2-31: Channel 0 Offset vs. Temperature. 400 350 300 G32 250 G16 200 G8 150 G4 100 G2 -50 G1 -100 ...

Page 17

... 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 FIGURE 2-40: MCLK 3.5 3 2 0.5 0.3 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 FIGURE 2-41: MCLK 0.3 0.6 MCP3911 AI , Boost Boost Boost 0. Boost 0. All Boost Settings DD MCLK Frequency (MHz) Operating Current vs. 3.3V Boost Boost Boost 0. Boost 0. ...

Page 18

... MCP3911 NOTES: DS22286A-page 18 © 2012 Microchip Technology Inc. ...

Page 19

... Table 3-1. Function 3.2 Digital the power supply pin for the digital circuitry DD within the MCP3911. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 3.6V for specified operation. 3.3 Analog the power supply pin for the analog circuitry DD within the MCP3911. This pin requires appropriate bypass capacitors and should be maintained to 2 ...

Page 20

... Digital Ground Connection (DGND) DGND is the ground connection to internal digital circuitry (See the MCP3911 Block diagram). To ensure optimal accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection digital ground plane is available recommended that this pin be tied to this plane of the Printed Circuit Board (PCB) ...

Page 21

... Data is clocked into the device on the RISING edge of SCK. Data is clocked out of the device on the FALLING edge of SCK. The MCP3911 interface is compatible with both SPI 0,0 and 1,1 modes. SPI modes can be changed during a CS high time. The maximum clock speed specified is 20 MHz. ...

Page 22

... MCP3911 NOTES: DS22286A-page 22 © 2012 Microchip Technology Inc. ...

Page 23

... Offset Error Gain Error Integral Non-Linearity Error Signal-To-Noise Ratio (SNR) Signal-To-Noise Ratio And Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3911 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hard Reset Mode (RESET 0) ...

Page 24

... MCP3911 Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR, AND PRESCALE, MCLK4MHZ PRE OSR <2:0> OSR < ...

Page 25

... This error varies with PGA and OSR settings. The gain error can be digitally compensated independently on each channel through the GAINCAL registers with a 24-bit calibration word. The gain error on the MCP3911 has a low temperature coefficient; for more information, see Figure © 2012 Microchip Technology Inc. ...

Page 26

... DAC is no more simple to realize and its linearity limits the THD of such ADCs. The MCP3911s 5-level quantizer is a flash ADC composed of four comparators arranged with equally spaced thresholds and a thermometer coding. The MCP3911 also includes proprietary 5-level DAC ⎞ ...

Page 27

... The dithering process scrambles the idle tones into baseband white noise and ensures that dynamic specs (SNR, SINAD, THD, SFDR) are less signal dependent. The MCP3911 incorporates a proprietary dithering algorithm on both ADCs in order to remove idle tones and improve THD, which is crucial for power metering applications ...

Page 28

... In this mode all internal registers are reset to their default state. The DC biases for the analog blocks are still active, i.e., the MCP3911 is ready to convert. However, this pin clears all conversion data in the ADCs. In this mode, the MDAT outputs are in high impedance. The comparator’ ...

Page 29

... The Configuration bits all reset to their default value, and the ADCs reset to their initial state, requiring 3 DRCLK periods for an initial data ready pulse. Exiting full Shutdown mode is effec- tively identical to an internal reset or returning from a POR condition. MCP3911 and and DV monitoring can ...

Page 30

... MCP3911 NOTES: DS22286A-page 30 © 2012 Microchip Technology Inc. ...

Page 31

... Delta-Sigma Modulator 5.3.1 ARCHITECTURE For best Both ADCs are identical in the MCP3911, and they include a proprietary second-order modulator with a multi-bit 5-level DAC architecture (see quantizer is a flash ADC composed of four compara- tors, with equally spaced thresholds, and a thermome- ter output coding. The proprietary 5-level architecture ...

Page 32

... MCP3911 modulator is still functional, however its stability is no longer guaranteed and therefore it is not recommended to exceed this limit (see FIGURE 2-24: SINAD vs. Input Signal Amplitude. for extended dynamic range performance limitations). The saturation point for the modulator is V /1.5 since the transfer function of the REF ADC includes a gain of 1 ...

Page 33

... AUTOZEROING FREQUENCY SETTING (AZ_FREQ) The MCP3911 modulators include an autozeroing algo- rithm to improve the offset error performance and greatly diminish 1/f noise in the ADC. This algorithm permits it to reach very high SNR and flattens the noise spectrum at the output of the ADC (see performance ...

Page 34

... The two MDAT output pins are in high impedance if the RESET pin is low. 5.5 SINC The decimation filter present in both channels of the MCP3911 is a cascade of two sinc filters (sinc a third order sinc filter with a decimation ratio of OSR followed by first order sinc filter with a decimation ratio of OSR (moving average of OSR 1 represents the decimation filter architecture ...

Page 35

... RESOLUTION IN BITS (NO MISSING CODES 128 23 256 24 512 24 1024 24 2048 24 4096 24 MCP3911 × ) 1 OSR 1 3 5-4). After the first data has been pro- SETTLING -3 dB BANDWIDTH TIME 96/DMCLK 0.26DRCLK 192/DMCLK 0.26DRCLK 384/DMCLK 0.26DRCLK 768/DMCLK 0.26DRCLK 1536/DMCLK ...

Page 36

... MCP3911 FIGURE 5-4: SINC Filter Frequency Response, OSR 256, MCLK 4 MHz, PRE<1:0> 00. FIGURE 5-5: SINC Filter Frequency Response, OSR 4096 (pink), OSR 512 (blue), MCLK 4 MHz, PRE<1:0> 00. DS22286A-page 36 © 2012 Microchip Technology Inc. ...

Page 37

... MCP3911 REF /1.5), the output code is locked to REF 3 1 SINC filter (see Equation 5-3). Decimal, 24-bit Hexadecimal Resolution ...

Page 38

... Voltage Reference 5.7.1 INTERNAL VOLTAGE REFERENCE The MCP3911 contains an internal voltage reference source specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the configuration register must be set to 0 (default mode). This internal V supplies reference voltage to both channels ...

Page 39

... Power-on Reset Operation. © 2012 Microchip Technology Inc. 5.8 Power-on Reset The MCP3911 contains an internal POR circuit that monitors both analog and digital supply voltages during operation. The typical threshold for a power-up event detection is 2.1 V ±5% and a typical start-up time ( µs. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µ ...

Page 40

... AGND. 5.10 Phase Delay Block The MCP3911 incorporates a phase delay generator, which ensures that the two ADCs are converting the inputs with a fixed delay between them. The two ADCs are synchronously sampling but the averaging of ...

Page 41

... Digital System Offset and Gain Errors The MCP3911 incorporates two sets of additional reg- isters per channel, to perform system digital offset and gain errors calibration. Each channel has its own set of registers associated that will modify the output result of the channel, if the calibration is enabled. The gain and ...

Page 42

... MCP3911 5.12.1 DIGITAL OFFSET ERROR CALIBRATION The OFFCAL_CHn registers are 23-bit plus sign twos complement register, which LSB value is the same as the Channel ADC Data. These two registers are then added bit-by-bit to the ADC output codes, if the EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL bit does not create any pipeline delay, the offset addi- tion is instantaneous ...

Page 43

... DESCRIPTION 6.1 Overview The MCP3911 device is compatible with SPI Modes 0,0 and 1,1. Data is clocked out of the MCP3911 on the falling edge of SCK and data is clocked into the MCP3911 on the rising edge of SCK. In these modes, SCK can Idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge ...

Page 44

... MCP3911 6.5 SPI MODE 1,1 Clock Idle High, Read/Write Examples In this SPI mode, SCK idles high. For the MCP3911, this means that there will be a falling edge on SCK before there is a rising edge. Note: Changing from an SPI Mode 1 SPI Mode 0,0 is possible and can be done while CS pin is logic high ...

Page 45

... SPI MODE 0,0 Clock Idle Low, Read/Write Examples In this SPI mode, SCK idles low. For the MCP3911, this means that there will be a rising edge on SCK before there is a falling edge. CS Data Transitions on the Falling Edge MCU and MCP3911 Latch Bits on the Rising Edge ...

Page 46

... Looping on Address Sets If the user wishes to read back either of the ADC channels continuously, or both channels continuously, the internal address counter of the MCP3911 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS pin returns logic high ...

Page 47

... CH1 ADC CH1 ADC CH0 ADC CH0 ADC CH1 ADC Lower byte Upper byte Middle byte Upper byte Middle byte MCP3911 CH0 ADC CH1 ADC CH1 ADC CH1 ADC CH0 ADC Upper byte Lower byte Upper byte Middle byte Lower byte ...

Page 48

... It is recommended to enter into ADC Reset mode for both ADCs, just after power-up, because the desired MCP3911 register configuration may not be the default one, and in this case, the ADC would output undesired data. Within the ADC Reset mode (RESET<1:0> 11), the user can configure the whole part with a single communication ...

Page 49

... ADC not in shutdown or Reset (i.e., only 1 ADC channel needs to be awake). Figure 6-9 represents the behavior of the data ready pin with the different DRMODE configurations, while shutdown or reset are applied. MCP3911 modes are set with the DS22286A-page 49 ...

Page 50

DRCLK Period RESET RESET<0> or SHUTDOWN<0> RESET<1> or SHUTDOWN<1> DRMODE00 DRMODE01 DRMODE10 DRMODE11 DRMODE00; DR ...

Page 51

... R/W Gain and Boost Configuration Register 16 R/W Status and Communication Register 16 R/W Configuration Register 24 R/W Offset Correction Register - Channel 0 24 R/W Gain Correction Register - Channel 0 24 R/W Offset Correction Register - Channel 1 24 R/W Gain Correction Register - Channel 1 8 R/W Internal Voltage reference Temperature Coefficient Adjustment Register MCP3911 Description DS22286A-page 51 ...

Page 52

... MCP3911 . TABLE 7-2: REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES Function Address 0x00 CHANNEL 0 0x01 0x02 0x03 CHANNEL 1 0x04 0x05 MOD 0x06 PHASE 0x07 0x08 GAIN 0x09 0x0A STATUSCOM 0x0B 0x0C CONFIG 0x0D 0x0E OFFCAL_CH0 0x0F 0x10 0x11 GAINCAL_CH0 0x12 0x13 ...

Page 53

... R-0 R-0 R-0 DATA_CHn DATA_CHn DATA_CHn <20> <19> <18> R-0 R-0 R-0 DATA_CHn DATA_CHn DATA_CHn <12> <11> <10> R-0 R-0 R-0 DATA_CHn DATA_CHn DATA_CHn <4> <3> <2> Unimplemented bit, read as 0 0 Bit is cleared MCP3911 R-0 R-0 DATA_CHn DATA_CHn <17> <16> bit 16 R-0 R-0 DATA_CHn DATA_CHn <9> <8> bit 8 R-0 R-0 DATA_CHn DATA_CHn <1> <0> bit Bit is unknown DS22286A-page 53 ...

Page 54

... MCP3911 7.2 MOD REGISTER - MODULATORS OUTPUT REGISTER Register REGISTER 7-2: MOD Name Bits Address MOD 8 0x06 The MOD register contains the most recent modulator data output. The default value corresponds to an equiv- alent input both ADCs. Each bit in this register corresponds to one comparator output on one of the channels ...

Page 55

... Delay PHASE Registers twos complement code/DMCLK (Default PHASE 0). © 2012 Microchip Technology Inc. Cof R/W U-0 R/W-0 R/W-0 PHASE<11> PHASE<10> bit 11 R/W-0 R/W-0 R/W-0 PHASE<3> PHASE<2> Unimplemented bit, read as 0 0 Bit is cleared MCP3911 R/W-0 R/W-0 PHASE<9> PHASE<8> bit 8 R/W-0 R/W-0 PHASE<1> PHASE<0> bit Bit is unknown DS22286A-page 55 ...

Page 56

... MCP3911 7.4 Gain - GAIN AND BOOST CONFIGURATION REGISTER Register REGISTER 7-4: GAIN Name Bits Address GAIN 8 0x09 R/W-1 R/W-0 R/W-0 BOOST<1> BOOST<0> PGA_CH1<2> bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7:6 BOOST<1:0> Bias Current Selection 11 Both channels have current Both channels have current x 1(DEFAULT Both channels have current x 0 ...

Page 57

... Address not incremented, continually write same single register © 2012 Microchip Technology Inc. Register Cof R/W R/W-0 R/W-0 R/W-0 DR_HIZ DRMODE<1> DRMODE<0> R/W-1 R/W-1 R/W-0 WIDTH<1> WIDTH<0> EN_OFFCAL U Unimplemented bit, read as 0 0 Bit is cleared MCP3911 R/W-1 R/W-1 DRSTATUS<1> DRSTATUS<0> bit 8 R/W-0 U-0 EN_GAINCAL bit Bit is unknown DS22286A-page 57 ...

Page 58

... MCP3911 bit 4:3 WIDTH<1:0> ADC Channel output data word width 11 Both channels are in 24-bit mode(DEFAULT Channel1 in 24-bit mode, Channel0 in 16-bit mode 01 Channel1 in 16-bit mode, Channel0 in 24-bit mode 00 Both channels are in 16-bit mode bit 2 EN_OFFCAL Enables or disables the 24-bit digital offset calibration on both channels 1 Enabled ...

Page 59

... VREFEXT DOWN<0> Unimplemented bit, read as 0 0 Bit is cleared AMCLK 1 MHz AMCLK 1 MHz AMCLK 1 MHz AMCLK 1 MHz AMCLK 1 MHz) (DEFAULT AMCLK 1 MHz AMCLK 1 MHz AMCLK 1 MHz) s MCP3911 R/W-1 R/W-0 DITHER<0> AZ_FREQ bit 8 R/W-1 U-0 CLKEXT bit Bit is unknown / DS22286A-page 59 ...

Page 60

... MCP3911 bit 2 VREFEXT Internal Voltage Reference Shutdown Control 1 Internal Voltage Reference Disabled 0 Internal Voltage Reference Enabled (Default) bit 1 CLKEXT Internal Clock selection bits 1 External clock drive by MCU on OSC1 pin (crystal oscillator disabled, no internal power consumption) (Default Crystal oscillator is enabled. A crystal must be placed between OSC1 and OSC2 pins. ...

Page 61

... CHn Output Code (GAINCAL_CHn1)ADC CHn Output Code. This register is a Don't Care if EN_GAINCAL0 (Offset calibration disabled) but its value is not cleared by the EN_GAINCAL bit. © 2012 Microchip Technology Inc. Cof R/W R/W ... R/W-0 R/W-0 ... GAINCAL_CHn GAINCAL_CHn <3> <2> Unimplemented bit, read as 0 0 Bit is cleared -23 increment in the multiplier. MCP3911 R/W-0 R/W-0 GAINCAL_CHn GAINCAL_CHn <1> <0> bit Bit is unknown DS22286A-page 61 ...

Page 62

... MCP3911 7.9 VREFCAL Register Internal Voltage Reference Temperature Coefficient Adjustment Register REGISTER 7-9: VREFCAL REGISTER Name Bits Address 0x1A VREFCAL 8 This register is only for advanced users. This register should not be written unless the user wants to calibrate the temperature coefficient of the whole system or application ...

Page 63

... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2012 Microchip Technology Inc. MCP3911 : Example 3911A0 PIN 1 E/ML ...

Page 64

... MCP3911 D TOP VIEW A3 DS22286A-page 64 EXPOSED PAD NOTE 1 BOTTOM VIEW © 2012 Microchip Technology Inc. ...

Page 65

... Microchip Technology Inc. MCP3911 DS22286A-page 65 ...

Page 66

... MCP3911 D N NOTE DS22286A-page © 2012 Microchip Technology Inc. φ L ...

Page 67

... APPENDIX A: REVISION HISTORY Revision A (March 2012) Original Release of this Document. © 2012 Microchip Technology Inc. MCP3911 DS22286A-page 67 ...

Page 68

... MCP3911 NOTES: DS22286A-page 68 © 2012 Microchip Technology Inc. ...

Page 69

... PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office PART NO Device Address Tape and Temperature Reel Options Device: MCP3911A0: Two Channel Analog Font End Converter Address Options A0 Default option. Contact Microchip factory for other ...

Page 70

... MCP3911 NOTES: DS22286A-page 70 © 2012 Microchip Technology Inc. ...

Page 71

... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2012, Microchip Technology Incorporated, Printed in the U ...

Page 72

... Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2012 Microchip Technology Inc. 11/29/11 ...

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