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PIC16(L)F1454 Datasheet

Download or read online Microchip Technology PIC16(L)F1454 14/20-Pin Flash, 8-Bit USB Microcontrollers With XLP Technology pdf datasheet.



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PIC16(L)F1454/5/9
Data Sheet
14/20-Pin Flash, 8-Bit USB Microcontrollers
with XLP Technology
Preliminary
 2012 Microchip Technology Inc.
DS41639A

Summary of Contents

Page 1

... Flash, 8-Bit USB Microcontrollers 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Data Sheet with XLP Technology Preliminary DS41639A ...

Page 2

... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2012, Microchip Technology Incorporated, Printed in the U ...

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... Software controllable hysteresis Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels • One Rail-to-Rail Resistive 5-Bit DAC with Positive Reference Selection Note 1: Analog features are not available on PIC16(L)F1454 devices. Preliminary (1) : DS41639A-page 3 ...

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... I - Debugging, Integrated on Chip Debugging, Available using Debug Header; Note Emulation, Available using Emulation Header. Three pins are input-only. 2: Data Sheet Index: 1: DS41639 PIC16(L)F1454/1455/1459 Data Sheet, 14/20-Pin Flash, 8-Bit USB For other small form-factor Note: www.microchip.com/packaging or contact your local sales office. DS41639A-page 4 ...

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... FIGURE 1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1454/1455 PDIP, SOIC, TSSOP MCLR/V Note 1: LVP support for PIC18(L)F1XK50 legacy designs. 2: See Table 1 and Table 2 FIGURE 2: 16-PIN QFN DIAGRAM FOR PIC16(L)F1454/1455 QFN (4x4) RA5 RA4 MCLR/V /RA3 PP RC5 Note 1: LVP support for PIC18(L)F1XK50 legacy designs. ...

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... RC2 RC3 14 7 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 /RA3 1 PP RA1/D-/ICSPCLK 15 RC5 USB RC4 3 PIC16(L)F1459 13 RC0/ICSPDAT RC3 4 12 RC1/ICSPCLK RC6 5 11 RC2 Preliminary (1) (1) (1) 2012 Microchip Technology Inc. ...

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... TABLE 1: 14-PIN ALLOCATION TABLE (PIC16(L)F1454) RA0 13 12 RA1 12 11 RA2 RA3 4 3 RA4 3 2 RA5 2 1 RC0 10 9 RC1 9 8 RC2 8 7 ...

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... INT ICSPCLK SDI (1) SDO (1) (1) (2) PWM2 SS CLKR TK PWM1 — — 2012 Microchip Technology Inc. ...

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... Default location for peripheral pin function. Alternate location can be selected using the APFCON register. Alternate location for peripheral pin function selected by the APFCON register. 2: LVP support for PIC18(L)F1XK50 legacy designs. 3: 2012 Microchip Technology Inc. D ...

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... Development Support... 385 32.0 Packaging Information... 389 Appendix A: Data Sheet Revision History... 407 Index ... 409 The Microchip Web Site ... 415 Customer Change Notification Service ... 415 Customer Support ... 415 Reader Response ... 416 Product Identification System... 417 DS41639A-page 10 Preliminary 2012 Microchip Technology Inc. ...

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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2012 Microchip Technology Inc. PIC16(L)F145X to receive the most current information on all of our products. Preliminary DS41639A-page 11 ...

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... PIC16(L)F145X NOTES: DS41639A-page 12 Preliminary 2012 Microchip Technology Inc. ...

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... DEVICE OVERVIEW The PIC16(L)F1454/5/9 are described within this data sheet. They are available in 14/20-pin packages. Figure 1-1 shows a block diagram PIC16(L)F1454/5/9 devices. Tables 1-2, show the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral Analog-to-Digital Converter (ADC) ...

Page 14

... PIC16(L)F1454/5/9 FIGURE 1-1: PIC16(L)F1454/5/9 BLOCK DIAGRAM Timing OSC2/CLKOUT Generation OSC1/CLKIN INTRC Oscillator MCLR USB CLKR Temp. EUSART (1) Indicator Note 1: PIC16(L)F1455/9 only. 2: PIC16(L)F1459 only. DS41639A-page 14 Program Flash Memory CPU (Figure 2-1) (1) (1) Timer0 Timer1 Timer2 C1 C2 ADC (1) FVR PWM1 PWM2 ...

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... TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION Name Function (3) RA0/D/ICSPDAT RA0 D ICSPDAT (3) RA1/D-/ICSPCLK RA1 D- ICSPCLK (2) (2) RA3/V /T1G /SS /MCLR RA3 T1G SS MCLR RA4/SOSCO/CLKOUT/ RA4 (1) (2) (1) T1G /SDO /CLKR /OSC2 SOSCO CLKOUT T1G SDO CLKR OSC2 RA5/CLKIN/SOSCI/T1CKI/ RA5 (2) PWM2 /OSC1 CLKIN ...

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... PIC16(L)F1454/5/9 TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION (CONTINUED) Name Function RC4/TX/CK RC4 TX CK RC5/T0CKI/RX/DT/PWM1 RC5 T0CKI RX DT PWM1 USB USB Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input ...

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... Default location for peripheral pin function. Alternate location can be selected using the APFCON register. Note 1: Alternate location for peripheral pin function selected by the APFCON register LVP support for PIC18(L)F1XK50 legacy designs. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Input Output Type Type TTL CMOS General purpose I/O. ...

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... PIC16(L)F1454/5/9 TABLE 1-3: PIC16(L)F1455 PINOUT DESCRIPTION (CONTINUED) Name Function RC1/AN5/C1IN1-/ RC1 C2IN1-/CWGFLT/SDA/ AN5 SDI/INT/ICSPCLK C1IN1- C2IN1- CWGFLT SDA SDI INT ICSPCLK RC2/AN6/DACOUT1/ RC2 (1) C1IN2-/C2IN2-/SDO AN6 DACOUT1 C1IN2- C2IN2- SDO RC3/AN7/DACOUT2/ RC3 (1) C1IN3-/C2IN3-/PWM2 / AN7 (1) (2) SS /CLKR ...

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... Default location for peripheral pin function. Alternate location can be selected using the APFCON register. Note 1: Alternate location for peripheral pin function selected by the APFCON register. 2: LVP support for PIC18(L)F1XK50 legacy designs. 3: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Input Output Type Type TTL CMOS General purpose I/O. ...

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... PIC16(L)F1454/5/9 TABLE 1-4: PIC16(L)F1459 PINOUT DESCRIPTION (CONTINUED) Name Function RC0/AN4/V /C1IN/C2IN/ RC0 REF ICSPDAT AN4 V REF C1IN C2IN ICSPDAT RC1/AN5/C1IN1-/C2IN1-/ RC1 CWGFLT/INT/ICSPCLK AN5 C1IN1- C2IN1- CWGFLT INT ICSPCLK RC2/AN6/DACOUT1/ RC2 C1IN2-/C2IN2- AN6 DACOUT1 C1IN2- C2IN2- RC3/AN7/DACOUT2/ RC3 ...

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... Oscillator Block Block Block 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow • ...

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... PIC16(L)F1454/5/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 Automatic Context for more information. 2.2 16-Level Stack with Overflow and ...

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... PIC16LF1455 PIC16F1459 PIC16LF1459 Note 1: High-endurance Flash applies to low byte of each address in the range. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 The following features are associated with access and control of program memory and data memory: PCL and PCLATH Stack Indirect Addressing 3 ...

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... PIC16(L)F1454/5/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1454/5/9 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 Page 1 On-chip Program Memory Page 2 Page 3 Rollover to Page 0 Rollover to Page 3 DS41639A-page 24 3.1.1 READING PROGRAM MEMORY AS ...

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... RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ; LOTS OF CODE MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Preliminary DS41639A-page 25 ...

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... PIC16(L)F1454/5/9 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): 12 core registers 20 Special Function Registers (SFR) • bytes of General Purpose RAM (GPR) • bytes of Dual-Port General Purpose RAM (DPR) • ...

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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...

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... PIC16(L)F1454/5/9 3.3.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appro- priate peripheral chapter of this data sheet ...

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... If the USB module is disabled, data Note 1: memory is GPR. If enabled, data memory can be DPR. Refer to Mem- ory Map for RAM type details. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 3.3.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1454/5/9 are as shown in Table 3-8 (1) Preliminary and Table 3-9. DS41639A-page 29 ...

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... TABLE 3-4: PIC16(L)F1454 MEMORY MAP, BANK 0-7 BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh 08Dh 10Dh 00Eh PORTC 08Eh TRISC 10Eh 00Fh 08Fh ...

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TABLE 3-5: PIC16(L)F1455 MEMORY MAP, BANK 0-7 BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh 08Dh 10Dh 00Eh PORTC 08Eh ...

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TABLE 3-6: PIC16(L)F1459 MEMORY MAP, BANK 0-7 BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh ...

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... TABLE 3-7: PIC16(L)F1454 MEMORY MAP, BANK 8-23 BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch 40Dh 48Dh 50Dh 40Eh 48Eh 50Eh 40Fh 48Fh ...

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TABLE 3-8: PIC16(L)F1455/9 MEMORY MAP, BANK 8-23 BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch 40Dh 48Dh 50Dh 40Eh 48Eh ...

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... TABLE 3-9: PIC16(L)F1454/5/9 MEMORY MAP, BANK 24-31 BANK 24 BANK 25 C00h C80h D00h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) C0Bh C8Bh D0Bh C0Ch C8Ch D0Ch C0Dh C8Dh D0Dh C0Eh C8Eh D0Eh C0Fh C8Fh ...

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... PIC16(L)F1454/5/9 TABLE 3-10: PIC16(L)F1454/5/9 MEMORY MAP, BANK 30-31 Bank 31 F8Ch Unimplemented Read as 0 FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh FECh FEDh STKPTR FEEh TOSL FEFh TOSH Unimplemented data memory locations, Legend: read as ‘ ...

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... Write Buffer for the upper 7 bits of the Program Counter x8Ah x0Bh or INTCON GIE PEIE x8Bh x unknown unchanged value depends on condition unimplemented, read as 0’ reserved. Legend: Shaded locations are unimplemented, read as 0. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 can be Bit 5 Bit 4 Bit 3 Bit 2 — ...

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... PIC16(L)F1454/5/9 TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY Addres Name Bit 7 Bit 6 s Bank 0 00Ch PORTA (1) 00Dh PORTB RB7 RB6 (1) (1) 00Eh PORTC RC7 RC6 00Fh Unimplemented 010h Unimplemented 011h PIR1 TMR1GIF ADIF 012h PIR2 OSFIF C2IF 013h — ...

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... Shaded locations are unimplemented, read as 0. Legend: PIC16(L)F1459 only. Note 1: 2: PIC16(L)F1455/9 only. 3: Unimplemented, read as 1. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 LATA5 LATA4 LATB5 LATB4 — ...

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... PIC16(L)F1454/5/9 TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addres Name Bit 7 Bit 6 s Bank 4 20Ch WPUA (1) 20Dh WPUB WPUB7 WPUB6 20Eh to Unimplemented 210h 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 212h SSP1ADD 213h SSP1MSK 214h SSP1STAT SMP ...

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... Shaded locations are unimplemented, read as 0. Note 1: PIC16(L)F1459 only. PIC16(L)F1455/9 only. 2: Unimplemented, read as 1. 3: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 PWM1DCH<7:0> ...

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... PIC16(L)F1454/5/9 TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addres Name Bit 7 Bit 6 s Bank 29 E8Ch Unimplemented E8Dh Unimplemented E8Eh UCON PPBRST E8Fh USTAT E90h UIR SOFIF E91h UCFG UTEYE Reserved E92h UIE SOFIE E93h ...

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... Shaded locations are unimplemented, read as 0. Legend: PIC16(L)F1459 only. Note 1: 2: PIC16(L)F1455/9 only. 3: Unimplemented, read as 1. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 Z_SHAD ...

Page 44

... PIC16(L)F1454/5/9 3.4 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. ...

Page 45

... FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 3.5.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

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... PIC16(L)F1454/5/9 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL DS41639A-page 46 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the ...

Page 47

... These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 0x0F Return Address 0x0E Return Address 0x0D Return Address ...

Page 48

... PIC16(L)F1454/5/9 FIGURE 3-8: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41639A-page 48 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved ...

Page 49

... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Indirect Addressing 7 FSRxH Bank Select 11111 Bank 31 Preliminary 7 ...

Page 50

... PIC16(L)F1454/5/9 3.6.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of DPR or GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the ...

Page 51

... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Words is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 by device Preliminary DS41639A-page 51 ...

Page 52

... PIC16(L)F1454/5/9 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 FCMEN bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor is enabled 0 Fail-Safe Clock Monitor is disabled ...

Page 53

... XT oscillator: Crystal/resonator on OSC1 and OSC2 pins 000 LP oscillator: Low-power crystal on OSC1 and OSC2 pins Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: Once enabled (CP 0), code-protect can only be disabled by bulk erasing the device. 2: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Preliminary DS41639A-page 53 ...

Page 54

... PIC16(L)F1454/5/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 LVP bit 13 R/P-1 R/P-1 R/P-1 PLLMULT USBLSCLK CPUDIV<1:0> bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 LVP: Low-Voltage Programming Enable bit 1 Low-voltage programming enabled 0 High-voltage on MCLR must be used for programming bit 12 ...

Page 55

... See Section 11.4 User ID, Device ID and Configuration for more information on accessing these Word Access memory locations. For more information on checksum calculation, see the PIC16(L)F1454/5/9 Memory Programming Specification (DS41620). 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Write ...

Page 56

... PIC16(L)F1454/5/9 4.6 Device ID and Revision ID The memory location 8005h and 8006h are where the Device ID and Revision ID are stored. See Section 11.4 User ID, Device ID and Configuration Word Access for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID ...

Page 57

... MHz HFINTOSC 3x/4x selectable Phase Lock Frequency Multiplier allows operation at 24 MHz. USB with configurable Full/Low speed operation. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low-Power mode (0 MHz to 0 ...

Page 58

... PIC16(L)F1454/5/9 FIGURE 5-1: SIMPLIFIED PIC FOSC<2:0> CLKIN/ OSC1/ SOSCI/ T1CKI Primary Oscillator (OSC) CLKOUT / OSC2 SOSCO/ T1G Secondary Oscillator (SOSC) Active Clock Tuning 16 MHz Internal OSC HFINTOSC Start-Up OSC Start-up Control Logic LFINTOSC 31 kHz Source DS41639A-page 58 ® MCU CLOCK SOURCE BLOCK DIAGRAM ...

Page 59

... High power, 4-20 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low power, 0-0.5 MHz (FOSC 101) 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

Page 60

... PIC16(L)F1454/5/9 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the Oscillator mode F selected (typically between 2 M  . ...

Page 61

... MCU SOSCI C1 32.768 kHz Quartz Crystal SOSCO C2 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Note 1: Quartz according manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the V expected for the application. ...

Page 62

... PIC16(L)F1454/5/9 5.2.1.6 External RC Mode The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words ...

Page 63

... Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 5.2.2.4 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3). Since IRCF< ...

Page 64

... PIC16(L)F1454/5/9 5.2.2.5 Internal Oscillator Frequency Selection Using the PLL The Internal Oscillator Block can be used with the PLL associated with the External Oscillator Block to produce a 24 MHz, 32 MHz or 48 MHz internal system clock source. The following settings are required to use the PLL internal clock sources: • ...

Page 65

... IRCF <3:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary ...

Page 66

... PIC16(L)F1454/5/9 5.3 CPU Clock Divider The CPU Clock divider allows the system clock to run at a slower speed than the Low/Full-Speed USB module clock, while sharing the same clock source. Only the oscillator defined by the settings of the FOSC bits of the Configuration Words may be used with the CPU clock divider. the CPU clock divider is controlled by the CPUDIV< ...

Page 67

... TABLE 5-2: HIGH-SPEED USB CLOCK SETTINGS Clock Clock Mode Frequency HFINTOSC 16 MHz 16 MHz ECH or HS mode 12 MHz 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 PLL Value USBLSCLK CPUDIV<1:0> Preliminary System Clock Frequency (MHz ...

Page 68

... PIC16(L)F1454/5/9 5.5 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: Default system oscillator determined by FOSC bits in Configuration Words • ...

Page 69

... Any clock source Secondary Oscillator 32 kHz PLL Inactive PLL Active PLL inactive. Note 1: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 5.6.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: IESO (of the Configuration Words Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...

Page 70

... PIC16(L)F1454/5/9 5.6.2 TWO-SPEED START-UP SEQUENCE 1. Wake-up from Power-on Reset or Sleep. 2. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. ...

Page 71

... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 5.7.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...

Page 72

... PIC16(L)F1454/5/9 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS41639A-page 72 Oscillator Failure ...

Page 73

... ACT_clk SOSC_clk 0 ACTUD ACTEN 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 5.8.2 ACTIVE CLOCK TUNING SOURCE SELECTION The ACT reference clock is selected with the ACTSRC bit of the ACTCON register. The reference clock sources are provided by the: USB module in full-speed operation (ACT_clk) • ...

Page 74

... PIC16(L)F1454/5/9 5.8.5 ACTIVE CLOCK TUNING UPDATE DISABLE When the ACT is enabled, the OSCTUNE register is continuously updated every ACT_clk period. Setting the ACT Update Disable bit can be used to suspend updates to the OSCTUNE register, without disabling the ACT. If the 16 MHz internal oscillator drifts out of the accuracy range, the ACT Status bits will change and an interrupt can be generated to notify the application ...

Page 75

... SCS<1:0>: System Clock Select bits 1x Internal oscillator block 01 Secondary oscillator 00 Clock determined by FOSC<2:0> in Configuration Words. Duplicate frequency derived from HFINTOSC. Note 1: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-1/1 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Section 5.2.2.1 “ ...

Page 76

... PIC16(L)F1454/5/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q SOSCR PLLRDY OSTS bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN Secondary oscillator is ready 0 Secondary oscillator is not ready ...

Page 77

... Maximum frequency When active clock tuning is enabled (ACTSEL 1) the oscillator is tuned automatically, the user cannot Note 1: write to OSCTUNE. Oscillator is tuned monotonically. 2: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 (1,2) R/W-0/0 R/W-0/0 R/W-0/0 TUN<6:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 78

... PIC16(L)F1454/5/9 REGISTER 5-4: ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER R/W-0/0 R/W-0/0 U-0 ACTEN ACTUD bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ACTEN: Active Clock Tuning Selection bit 1 ACT is enabled, updates to OSCTUNE are exclusive to the ACT ...

Page 79

... ICSP Programming Mode Exit RESET Instruction Stack Pointer MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR (1) Active See Table 6-1 for BOR active conditions. Note 1: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 PWRT R Done PWRTE LFINTOSC Preliminary Device Reset DS41639A-page 79 ...

Page 80

... PIC16(L)F1454/5/9 6.1 Power-On Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

Page 81

... Unimplemented: Read as 0 bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 The Brown-out Reset circuit is active 0 The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 (1) T PWRT < T PWRT PWRT (1) T ...

Page 82

... PIC16(L)F1454/5/9 6.4 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset ...

Page 83

... FIGURE 6-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 T PWRT T MCLR Preliminary DS41639A-page 83 ...

Page 84

... PIC16(L)F1454/5/9 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR ...

Page 85

... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 6-2. R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT RMCLR Bit is set by hardware U Unimplemented bit, read as ‘ ...

Page 86

... PIC16(L)F1454/5/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN BORFS PCON STKOVF STKUNF STATUS WDTCON Legend: unimplemented bit, reads as 0. Shaded cells are not used by Resets. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. ...

Page 87

... The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 7.3 Conflicts with the CLKR Pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...

Page 88

... PIC16(L)F1454/5/9 7.5 Register Definition: Reference Clock Control REGISTER 7-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit ...

Page 89

... Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented locations read as 0 . Shaded cells are not used by reference clock sources. Legend: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC<1:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE< ...

Page 90

... PIC16(L)F1454/5/9 NOTES: DS41639A-page 90 Preliminary 2012 Microchip Technology Inc. ...

Page 91

... A block diagram of the interrupt logic is shown in Figure 8-1. FIGURE 8-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 TMR0IF TMR0IE INTF INTE IOCIF IOCIE PEIE GIE Preliminary Wake-up (If in Sleep mode) ...

Page 92

... PIC16(L)F1454/5/9 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: GIE bit of the INTCON register Interrupt Enable bit(s) for the specific interrupt event(s) PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the ...

Page 93

... Execute 2 Cycle Instruction at PC Interrupt GIE PC PC-1 PC Execute 3 Cycle Instruction at PC Interrupt GIE PC PC-1 PC Execute 3 Cycle Instruction at PC 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Interrupt Sampled during Q1 PC1 0004h Inst(PC) NOP NOP PC1/FSR New PC/ 0004h ADDR PC1 Inst(PC) NOP NOP FSR ADDR ...

Page 94

... PIC16(L)F1454/5/9 FIGURE 8-3: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) INTF (5) GIE INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. ...

Page 95

... ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the users appli- cation, other registers may also need to be saved. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Preliminary DS41639A-page 95 ...

Page 96

... PIC16(L)F1454/5/9 8.6 Register Definitions: Interrupt Control REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 GIE PEIE TMR0IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 Enables all active interrupts ...

Page 97

... Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt PIC16(L)F1455/9 only. Note 1: Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-0/0 R/W-0/0 U-0 TXIE SSP1IE — Unimplemented bit, read as 0 ...

Page 98

... PIC16(L)F1454/5/9 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 Enables the Oscillator Fail interrupt ...

Page 99

... Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-0/0 R/W-0/0 U-0 TXIF SSP1IF ...

Page 100

... PIC16(L)F1454/5/9 REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending ...

Page 101

... PIR1 TMR1GIF ADIF PIR2 OSFIF C2IF Legend: unimplemented location, read as 0. Shaded cells are not used by interrupts. Note 1: PIC16(L)F1455/9 only. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF PSA RCIE TXIE SSP1IE — ...

Page 102

... PIC16(L)F1454/5/9 NOTES: DS41639A-page 102 Preliminary 2012 Microchip Technology Inc. ...

Page 103

... Examples of internal circuitry that might be sourcing current include the FVR module. See Fixed Voltage Reference (FVR) (PIC16(L)F1455/9 for more information on this module. only) 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. ...

Page 104

... PIC16(L)F1454/5/9 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP ...

Page 105

... Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 9.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected ...

Page 106

... PIC16(L)F1454/5/9 9.3 Register Definitions: Voltage Regulator Control REGISTER 9-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Unimplemented: Read as 0 bit 1 VREGPM: Voltage Regulator Power Mode Selection bit ...

Page 107

... Configurable time-out period is from 256 seconds (nominal) Multiple Reset conditions Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41639A-page 107 ...

Page 108

... PIC16(L)F1454/5/9 10.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 29.0 Electrical Specifications LFINTOSC tolerances. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE< ...

Page 109

... WDTE<1:0> and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep System Clock EXTRC, INTOSC, EXTCLK Exit Sleep System Clock XT, HS, LP Change INTOSC divider (IRCF bits) 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Cleared until the end of OST Preliminary WDT Cleared Unaffected DS41639A-page 109 ...

Page 110

... PIC16(L)F1454/5/9 10.6 Register Definitions: Watchdog Control REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits ...

Page 111

... SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Name Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented location, read as 0. Shaded cells are not used by Watchdog Timer. Legend: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 IRCF<3:0> RWDT RMCLR RI — WDTPS<4:0> ...

Page 112

... PIC16(L)F1454/5/9 11.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full V Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: PMCON1 PMCON2 PMDATL • ...

Page 113

... The two instructions following a program Note: memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on instruction after the RD bit is set. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 FIGURE 11-1: Write Latches (words) 32 Program or Configuration Memory to the Instruction Fetched ignored ...

Page 114

... PIC16(L)F1454/5/9 FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) BSF PMCON1,RD INSTR( executed here executed here RD bit PMDATH PMDATL Register EXAMPLE 11-1: FLASH PROGRAM MEMORY READ ...

Page 115

... Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 FIGURE 11-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence ...

Page 116

... PIC16(L)F1454/5/9 11.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. Load the PMADRH:PMADRL register pair with any address within the row to be erased. 2. Clear the CFGS bit of the PMCON1 register. 3. Set the FREE and WREN bits of the PMCON1 register ...

Page 117

... NOP NOP BCF PMCON1,WREN BSF INTCON,GIE 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; Start of required sequence to initiate erase ...

Page 118

... PIC16(L)F1454/5/9 11.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. Load the address in PMADRH:PMADRL of the row to be programmed. 2. Load each write latch with data. 3. Initiate a programming operation. 4. Repeat steps 1 through 3 until all data is written. Before writing to program memory, the word( written must be erased or previously unwritten ...

Page 119

FIGURE 11-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES PMADRH - r10 Row PMADRH<6:0> Address :PMADRL<7:4> Decode ...

Page 120

... PIC16(L)F1454/5/9 FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE 0) Select Program or Config. Memory (CFGS) Select Row Address ...

Page 121

... MOVWF PMCON2 BSF PMCON1,WR NOP NOP BCF PMCON1,WREN BSF INTCON,GIE 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Not configuration space ; Enable writes ; Only Load Write Latches ...

Page 122

... PIC16(L)F1454/5/9 11.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. Load the starting address of the row to be modified ...

Page 123

... Restore interrupts MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 11-2, the Function Read Access User IDs Yes Yes Yes Figure 11-2) Figure 11-2) Preliminary ...

Page 124

... PIC16(L)F1454/5/9 11.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete ...

Page 125

... Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 126

... PIC16(L)F1454/5/9 REGISTER 11-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address REGISTER 11-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER ...

Page 127

... Note 1: 2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR 1). The LWLO bit is ignored during a program memory erase operation (FREE 1). 3: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE WRERR WREN U Unimplemented bit, read as 0 ...

Page 128

... PIC16(L)F1454/5/9 REGISTER 11-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 bit 7 Legend Readable bit W Writable bit S Bit can only be set x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register ...

Page 129

... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 FIGURE 12-1: D Write LATx Write PORTx Data Register ...

Page 130

... SDOSEL: Pin Selection bit 1 SDO function is on RA4 0 SDO function is on RC2 bit 5 SSSEL: Pin Selection bit For 14-Pin Devices (PIC16(L)F1454/5 function is on RA3 function is on RC3 For 20-Pin Devices (PIC16(L)F1455/9 function is on RA3 function is on RC6 bit 4 Unimplemented: Read as ‘ ...

Page 131

... The ANSELA bits default to the Analog Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to 0 by user software. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 EXAMPLE 12-2: BANKSEL PORTA CLRF PORTA BANKSEL ...

Page 132

... PIC16(L)F1454/5/9 12.4 Register Definitions: PORTA REGISTER 12-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x RA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-3 RA<5:3>: PORTA I/O Value bits 1 Port pin is > Port pin is < ...

Page 133

... Unimplemented: Read as 0 When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. PIC16(L)F1455/9 only. 2: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-x/u U-0 U-0 LATA4 — Unimplemented bit, read as 0 ...

Page 134

... WPUA — unknown unchanged, unimplemented locations read as 0 . Shaded cells are not used by PORTA. Legend: Unimplemented, read as 1 . Note 1: 2: PIC16(L)F1454/5 only. 3: PIC16(L)F1455/9 only. TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA Name Bits Bit -/7 Bit -/6 13:8 — ...

Page 135

... Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to 0 by user software. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 12.5.4 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The ...

Page 136

... PIC16(L)F1454/5/9 12.6 Register Definitions: PORTB REGISTER 12-7: PORTB: PORTB REGISTER R/W-x/x R/W-x/x R/W-x/x RB7 RB6 RB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Value bits 1 Port pin is > Port pin is < V ...

Page 137

... Digital I/O. Pin is assigned to port or digital special function. bit 3-0 Unimplemented: Read as 0 When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-x/u U-0 U-0 LATB4 ...

Page 138

... PIC16(L)F1454/5/9 REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 Pull-up enabled 0 Pull-up disabled bit 3-0 Unimplemented: Read as 0 ...

Page 139

... RC1 RC2 RC3 RC4 RC5 RC6 RC7 Priority listed from highest to lowest. Note 1: Default pin (see APFCON register). 2: Alternate pin (see APFCON register PIC16(L)F1454/5 only. PIC16(L)F1455/9 only. 5: Preliminary Table 12-8. PORTC OUTPUT PRIORITY (1) Function Priority ICSPDAT (4) SCL (4) SCK ICSPCLK ...

Page 140

... PIC16(L)F1454/5/9 12.8 Register Definitions: PORTC REGISTER 12-12: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u (1) (1) RC7 RC6 RC5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits 1 Port pin is > Port pin is < ...

Page 141

... TRISC6 x unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTC. Legend: PIC16(L)F1459 only. Note 1: PIC16(L)F1455/9 only. 2: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 142

... PIC16(L)F1454/5/9 NOTES: DS41639A-page 142 Preliminary 2012 Microchip Technology Inc. ...

Page 143

... A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 13.3 Interrupt Flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port ...

Page 144

... PIC16(L)F1454/5/9 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx RAx IOCAPx Q4Q1 Q4Q1 DS41639A-page 144 Q4Q1 Edge Detect Data Bus Write IOCAFx CK From all other IOCAFx individual Pin Detectors Q1 Q2 ...

Page 145

... IOCAN<1:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge Interrupt-on-Change disabled for the associated pin. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-0/0 R/W-0/0 U-0 IOCAP4 IOCAP3 — ...

Page 146

... PIC16(L)F1454/5/9 REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-3 IOCAF<5:3>: Interrupt-on-Change PORTA Flag bits enabled change was detected on the associated pin ...

Page 147

... Set when IOCBPx 1 and a rising edge was detected on RBx, or when IOCBNx 1 and a falling edge was detected on RBx change was detected, or the user cleared the detected change. bit 3-0 Unimplemented: Read as 0 PIC16(L)F1459 only. Note 1: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-0/0 U-0 U-0 IOCBN4 — Unimplemented bit, read as 0 ...

Page 148

... PIC16(L)F1454/5/9 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Name Bit 7 Bit 6 (3) ANSELA INTCON GIE PEIE IOCAF IOCAN IOCAP (2) IOCBF IOCBF7 IOCBF6 (2) IOCBN IOCBN7 IOCBN6 (2) IOCBP IOCBP7 IOCBP6 TRISA (2) TRISB ...

Page 149

... BOREN<1:0> and BORFS 1 LDO All PIC16F1454/5/9 devices, when VREGPM 1 and not in Sleep 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Refer- ence Section 16.0 “ ...

Page 150

... PIC16(L)F1454/5/9 14.3 Register Definitions: FVR Control REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit ...

Page 151

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 FIGURE 15-1: 15.2 Minimum Operating V When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications ...

Page 152

... PIC16(L)F1454/5/9 TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Name Bit 7 Bit 6 FVRCON FVREN FVRRDY Legend: Shaded cells are unused by the temperature indicator module. DS41639A-page 152 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> Preliminary Register Bit 1 Bit 0 on page ADFVR<1:0> ...

Page 153

... The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 (ADC) allows Preliminary DS41639A-page 153 ...

Page 154

... PIC16(L)F1454/5/9 FIGURE 16-1: ADC BLOCK DIAGRAM V DD Reserved Reserved Reserved AN3 V /AN4 REF AN5 AN6 AN7 AN8 AN9 AN10 AN11 Reserved Reserved Temp Indicator DAC FVR Buffer1 CHS<4:0> Note 1: When ADON 0, all multiplexer inputs are disconnected. DS41639A-page 154 ADPREF ADPREF 10 ...

Page 155

... Section 14.0 Fixed Voltage Reference (FVR) for more details on the Fixed (PIC16(L)F1455/9 only) Voltage Reference. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 16.1.4 CONVERSION CLOCK The source of the conversion clock is software select- able via the ADCS bits of the ADCON1 register. There are seven possible clock options: • ...

Page 156

... PIC16(L)F1454/5/9 TABLE 16-1: ADC CLOCK PERIOD (T ADC Clock Period ( ADC ADCS<2:0> 20 MHz Clock Source Fosc/2 000 100 ns Fosc/4 100 200 ns Fosc/8 001 400 ns Fosc/16 101 800 ns 1.6 s Fosc/32 010 3.2 s Fosc/64 110 1.0-6.0  x11 RC Shaded cells are outside of recommended range. ...

Page 157

... MSB bit 7 (ADFM 1 ) bit 7 Unimplemented: Read as 0 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 16.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 16-3 shows the two output formats ...

Page 158

... PIC16(L)F1454/5/9 16.2 ADC Operation 16.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a 1. Setting the GO/ DONE bit of the ADCON0 register to a 1 will start the Analog-to-Digital conversion. The GO/DONE bit should not be set in the Note: same instruction that turns on the ADC ...

Page 159

... Refer to Section 16.4 A/D Acquisition . Requirements 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 EXAMPLE 16-1: ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ; ;Conversion start & polling for completion ...

Page 160

... PIC16(L)F1454/5/9 16.3 Register Definitions: ADC Control REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 Unimplemented: Read as 0 bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 Reserved. No channel connected. ...

Page 161

... When selecting the V pin as the source of the positive reference, be aware that a minimum voltage Note 1: REF specification exists. See Section 29.0 Electrical Specifications 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-0/0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 162

... PIC16(L)F1454/5/9 REGISTER 16-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 Unimplemented: Read as 0 bit 6-4 TRIGSEL<2:0>: Auto-Conversion Trigger Selection bits 000 No auto-conversion trigger selected ...

Page 163

... Bit is set 0 Bit is cleared bit 7-6 ADRES<1:0> : ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved : Do not use. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-x/u ...

Page 164

... PIC16(L)F1454/5/9 REGISTER 16-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 1 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Reserved : Do not use. bit 1-0 ADRES<9:8> : ADC Result Register bits ...

Page 165

... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources . This is required to meet the pin leakage specification. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 166

... PIC16(L)F1454/5/9 FIGURE 16-4: ANALOG INPUT MODEL Analog Input pin Rs C PIN Legend Sample/Hold Capacitance HOLD C Input Capacitance PIN I Leakage current at the pin due to LEAKAGE various junctions R Interconnect Resistance Resistance of Sampling Switch Sampling Switch V Threshold Voltage T Note 1: Refer to Section 29.0 Electrical Specifications ...

Page 167

... Shaded cells are not Legend: used for ADC module. Unimplemented, read as 1 . Note 1: PIC16(L)F1459 only. 2: PIC16(L)F1455/9 only. 3: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ...

Page 168

... PIC16(L)F1454/5/9 NOTES: DS41639A-page 168 Preliminary 2012 Microchip Technology Inc. ...

Page 169

... Section 29.0 . Specifications 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: ...

Page 170

... PIC16(L)F1454/5/9 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM REF DACPSS DACEN FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41639A-page 170 Digital-to-Analog Converter (DAC) V SOURCE Steps SOURCE - ...

Page 171

... Effects of a Reset A device Reset affects the following: DAC is disabled. DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Preliminary DS41639A-page 171 ...

Page 172

... PIC16(L)F1454/5/9 17.6 Register Definitions: DAC Control REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 DACEN DACOE1 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled bit 6 Unimplemented: Read as ‘ ...

Page 173

... the output of the comparator is a digital high level. IN The comparators available for this device are located in Table 18-1. TABLE 18-1: COMPARATOR AVAILABILITY PER DEVICE Device C1 PIC16(L)F1455 PIC16(L)F1459 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 FIGURE 18- Output ...

Page 174

... PIC16(L)F1454/5/9 FIGURE 18-2: COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON 3 0 Reserved 1 C IN1- X MUX C IN2 IN3 CxVN - FVR Buffer2 4 CxVP 0 C IN X MUX 1 DAC CxSP (2) FVR Buffer2 2 3 CxON C PCH<1:0> Note 1: When CxON 0, the Comparator will produce a 0 at the output When CxON 0, all multiplexer inputs are disconnected ...

Page 175

... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 18.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by 18-1) contain setting the CxPOL bit of the CMxCON0 register ...

Page 176

... PIC16(L)F1454/5/9 18.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Section 29.0 Electrical Specifications more information. 18.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1 ...

Page 177

... ECCP Auto-Shutdown mode. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 18.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-3. Since the analog input pins share their ...

Page 178

... PIC16(L)F1454/5/9 FIGURE 18-3: ANALOG INPUT MODEL Analog Input pin Rs < 10K C PIN Legend Input Capacitance PIN I Leakage Current at the pin due to various junctions LEAKAGE R Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 29.0 Electrical Specifications ...

Page 179

... CxSYNC: Comparator Output Synchronous Mode bit 1 Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP ...

Page 180

... PIC16(L)F1454/5/9 REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit ...

Page 181

... Legend: unimplemented location, read as 0 . Shaded cells are unused by the comparator module. Unimplemented, read as 1 . Note 1: PIC16(L)F1459 only. 2: PIC16(L)F1455/9 only, 3: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ...

Page 182

... PIC16(L)F1454/5/9 NOTES: DS41639A-page 182 Preliminary 2012 Microchip Technology Inc. ...

Page 183

... T0CKI 1 TMR0SE TMR0CS 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The value written to the TMR0 register Note: can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...

Page 184

... PIC16(L)F1454/5/9 19.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are eight prescaler options for the Timer0 mod- ule ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...

Page 185

... Unimplemented location, read as 0 . Shaded cells are not used by the Timer0 module. Legend: Page provides register information. Note 1: Unimplemented, read as 1 . PIC16(L)F1455/9 only. 2: 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets /4) ...

Page 186

... PIC16(L)F1454/5/9 NOTES: DS41639A-page 186 Preliminary 2012 Microchip Technology Inc. ...

Page 187

... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: PIC16(L)F1455/9 only. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 20 block diagram of the Timer1 module ...

Page 188

... PIC16(L)F1454/5/9 20.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...

Page 189

... When switching from asynchronous to synchronous operation possible to produce an additional increment. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 20.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...

Page 190

... PIC16(L)F1454/5/9 20.6.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 20-4: TIMER1 GATE SOURCES ...

Page 191

... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 20.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode ...

Page 192

... PIC16(L)F1454/5/9 FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 20-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41639A-page 192 Preliminary 2012 Microchip Technology Inc. ...

Page 193

... T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41639A-page 193 ...

Page 194

... PIC16(L)F1454/5/9 FIGURE 20-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41639A-page 194 Set by hardware on falling edge of T1GVAL Preliminary  ...

Page 195

... Synchronize asynchronous clock input with system clock (F bit 1 Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 and clears Timer1 gate flip-flop 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 196

... PIC16(L)F1454/5/9 REGISTER 20-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON 0 : This bit is ignored If TMR1ON Timer1 counting is controlled by the Timer1 gate function ...

Page 197

... Shaded cells are not used by the Timer1 module. Page provides register information. Unimplemented, read as 1 . Note 1: 2: PIC16(L)F1455 only. only. 3: PIC16(L)F1455/9 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 SSSEL ...

Page 198

... PIC16(L)F1454/5/9 NOTES: DS41639A-page 198 Preliminary 2012 Microchip Technology Inc. ...

Page 199

... Optional use as the shift clock for the MSSP module (Timer2 only) See Figure 21-1 for a block diagram of Timer2. FIGURE 21-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> 2012 Microchip Technology Inc. PIC16(L)F1454/5/9 TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary Sets Flag bit TMR2IF ...

Page 200

... PIC16(L)F1454/5/9 21.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (F /4). OSC TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS< ...

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