Datasheets»Microchip Technology»PIC18F47J53 Datasheet

PIC18F47J53 Datasheet

Download or read online Microchip Technology PIC18F47J53 28/44-Pin, High-Performance USB Microcontrollers With NanoWatt XLP Technology pdf datasheet.



Page
1 of 586
next
PIC18F47J53 Family
Data Sheet
28/44-Pin, High-Performance
USB Microcontrollers
with nanoWatt XLP Technology
Preliminary
 2010 Microchip Technology Inc.
DS39964B

Summary of Contents

Page 1

... Microchip Technology Inc. PIC18F47J53 Family 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet DS39964B ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U ...

Page 3

... Fail-Safe Clock Monitor (FSCM): - Allows for safe shutdown if any clock stops Programmable Reference Clock Output Generator 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Peripheral Highlights: Peripheral Pin Select: - Allows independent I/O mapping of many peripherals - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes • ...

Page 4

... PIC18F47J53 FAMILY PIC18F Device PIC18F26J53 28 64K 3.8K 16 PIC18F27J53 28 128K 3.8K 16 PIC18F46J53 44 64K 3.8K 22 PIC18F47J53 44 128K 3.8K 22 PIC18LF26J53 28 64K 3.8K 16 PIC18LF27J53 28 128K 3.8K 16 PIC18LF46J53 44 64K 3.8K 22 PIC18LF47J53 44 128K 3.8K Dual access RAM for USB and/or general purpose use. DS39964B-page 4 MSSP 4/4 3 4/4 3 4/4 3 4/4 3 ...

Page 5

... Table 10-13 and Table 10-14, respectively. For details on configuring the PPS mod- ule, see Section 10.7 Peripheral Pin Select (PPS). Note: For the QFN package recommended that the bottom pad be connected to V 2010 Microchip Technology Inc. PIC18F47J53 FAMILY ...

Page 6

... PIC18F47J53 FAMILY Pin Diagrams (Continued) 44-Pin QFN RC7/CCP10/PMA4/RX1/DT1/SDO1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 RB0/AN12/C3IND/INT0/RP3 RB1/AN10/C3INC/PMBE/RTCC/RP4 RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5 RPn represents remappable pins. Legend: Shaded pins are 5.5V tolerant. For the QFN package recommended that the bottom pad be connected to V Note: DS39964B-page 6 OSC2/CLKO/RA6 1 33 OSC1/CLKI/RA7 ...

Page 7

... RB0/AN12/C3IND/INT0/RP3 RB1/AN10/C3INC/PMBE/RTCC/RP4 RB2/AN8/C2INC/CTED1/PMA3/VMO/REFO/RP5 RB3/AN9/C3INA/CTED2/PMA2/VPO/RP6 RPn represents remappable pins. Legend: Shaded pins are 5.5V tolerant. Dedicated A /A Note: VDD VSS VDD VSS DD SS 2010 Microchip Technology Inc. PIC18F47J53 FAMILY PIC18F4XJ53 ...

Page 8

... Instruction Set Summary ... 459 30.0 Development Support... 509 31.0 Electrical Characteristics ... 513 32.0 Packaging Information... 555 Appendix A: Revision History... 569 Appendix B: Migration From PIC18F46J50 to PIC18F47J53... 569 The Microchip Web Site ... 583 Customer Change Notification Service ... 583 Customer Support ... 583 Reader Response ... 584 Product Identification System... 585 ...

Page 9

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Preliminary DS39964B-page 9 ...

Page 10

... PIC18F47J53 FAMILY NOTES: DS39964B-page 10 Preliminary 2010 Microchip Technology Inc. ...

Page 11

... Microchip Technology Inc. PIC18F47J53 FAMILY 1.1.3 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F47J53 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: Two Crystal modes, using crystals or ceramic resonators. ...

Page 12

... Section 31.0 Electrical Characteristics for time-out periods. 1.3 Details on Individual Family Devices Devices in the PIC18F47J53 family are available in 28-pin and 44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in two ways: • ...

Page 13

... I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10/12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2010 Microchip Technology Inc. PIC18F47J53 FAMILY PIC18F26J53 DC 48 MHz 64 32,768 3.8 30 Ports ECCP and 7 CCP MSSP (2), Enhanced USART (2), USB ...

Page 14

... PIC18F47J53 FAMILY FIGURE 1-1: PIC18F2XJ53 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (16 Kbytes-64 Kbytes) Data Latch 8 Instruction Bus <16> Timing Generation OSC2/CLKO OSC1/CLKI 8 MHz INTOSC INTRC Oscillator V USB USB Module Precision Band Gap Reference Voltage Regulator V /V DDCORE ...

Page 15

... Timer0 Timer1 CTMU ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 Note 1: See Table 1-3 for I/O port pin descriptions. 2: The on-chip voltage regulator is always enabled by default. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Data Latch 8 8 Data Memory (3.8 Kbytes) PCLATU ...

Page 16

... PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC (2) MCLR 1 OSC1/CLKI/RA7 9 OSC1 CLKI (1) RA7 OSC2/CLKO/RA6 10 OSC2 CLKO (1) RA6 Legend: TTL TTL compatible input ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. ...

Page 17

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 2: 5.5V tolerant. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Pin Buffer Type Type 28-QFN PORTA is a bidirectional I/O port. 27 I/O TTL/DIG Digital I/O. ...

Page 18

... PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RB0/AN12/C3IND/INT0/RP3 21 RB0 AN12 C3IND INT0 RP3 RB1/AN10/C3INC/RTCC/RP4 22 RB1 AN10 C3INC RTCC RP4 RB2/AN8/C2INC/CTED1/ 23 VMO/REFO/RP5 RB2 AN8 C2INC CTED1 VMO REFO RP5 RB3/AN9/C3INA/CTED2/ 24 VPO/RP6 RB3 AN9 C3INA CTED2 ...

Page 19

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 2: 5.5V tolerant. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Pin Buffer Type Type 28-QFN PORTB (continued) (2) 22 I/O TTL/DIG Digital I/O ...

Page 20

... PIC18F47J53 FAMILY TABLE 1-3: PIC18F2XJ53 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RC0/T1OSO/T1CKI/RP11 11 RC0 T1OSO T1CKI RP11 RC1/CCP8/T1OSI/UOE/RP12 12 RC1 CCP8 T1OSI UOE RP12 RC2/AN11/C2IND/CTPLS/ 13 RP13 RC2 AN11 C2IND CTPLS RP13 RC4/D-/VM 15 RC4 D- VM RC5/D/VP 16 RC5 D VP (2) RC6/CCP9/TX1/CK1/RP17 17 RC6 CCP9 ...

Page 21

... Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 5.5V tolerant. 2: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Pin Buffer Type Type 28-QFN 5 P Ground reference for logic and I/O pins. ...

Page 22

... Legend: TTL TTL compatible input ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: 5.5V tolerant. 3: DS39964B-page 22 Pin Buffer 44- Type ...

Page 23

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Pin Buffer ...

Page 24

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 5.5V tolerant. 3: DS39964B-page 24 Pin Buffer 44- Type Type TQFP PORTB is a bidirectional I/O port ...

Page 25

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Pin Buffer ...

Page 26

... Legend: TTL TTL compatible input ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: 5.5V tolerant. 3: DS39964B-page 26 Pin Buffer 44- Type ...

Page 27

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Pin Buffer ...

Page 28

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: 2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 5.5V tolerant. 3: DS39964B-page 28 Pin Buffer 44- Type Type TQFP PORTD is a bidirectional I/O port ...

Page 29

... ST Schmitt Trigger input with CMOS levels I Input P Power DIG Digital output RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. Note 1: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: 5.5V tolerant. 3: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Pin Buffer ...

Page 30

... PIC18F47J53 FAMILY NOTES: DS39964B-page 30 Preliminary 2010 Microchip Technology Inc. ...

Page 31

... GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F47J53 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: All V and V pins DD SS (see Section 2.2 “ ...

Page 32

... PIC18F47J53 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...

Page 33

... Frequency (MHz) Data for Murata GRM21BF50J106ZE01 shown. Note: Measurements at 25° bias. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ...

Page 34

... PIC18F47J53 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 Oscillator Configurations for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...

Page 35

... Phase Locked Loop (PLL). Its use is described in Section 3.2.5.1 OSCTUNE Register. 3.2 Oscillator Types PIC18F47J53 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC<2:0> Configuration bits to select one of the modes listed in Table 3-1. For oscillator modes which produce a clock output (CLKO) on pin RA6, the output frequency will be one fourth of the peripheral clock frequency ...

Page 36

... PIC18F47J53 FAMILY FIGURE 3-1: PIC18F47J53 FAMILY CLOCK DIAGRAM Primary Oscillator OSC2 F OSC OSC1 CFGPLLEN Secondary Oscillator T1OSO T1OSI Internal Oscillator Block 8 MHz 8 MHz INTRC 31 kHz Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit in the OSCTUNE register is set ...

Page 37

... DD See the notes following Table 3-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz 2010 Microchip Technology Inc. PIC18F47J53 FAMILY TABLE 3-3: Osc Type HS the crystal Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...

Page 38

... OSC2/CLKO F /4 OSC 3.2.4 PLL FREQUENCY MULTIPLIER PIC18F47J53 family devices include a PLL circuit. This is provided specifically for USB applications with lower speed oscillators and can also be used as a microcontroller clock source. The PLL can be enabled in HSPLL, ECPLL, INTOSCPLL and INTOSCPLLO Oscillator modes by setting the PLLEN bit (OSCTUNE< ...

Page 39

... INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 3.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency ...

Page 40

... When the CFGPLLEN Configuration bit is used to enable the PLL, clearing OSCTUNE<6> will not disable the PLL. 3.3 Oscillator Settings for USB When the PIC18F47J53 family devices are used for USB connectivity MHz or 48 MHz clock must be provided to the USB module for operation in either Low-Speed or Full-Speed modes, respectively. This may require some forethought in selecting an oscillator frequency and programming the device ...

Page 41

... MHz 1 (111) 4 MHz 1: The 24 MHz EC mode (without PLL) is only compatible with low-speed USB. Full-speed USB requires a 48 MHz system Note clock. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Clock Mode MCU Clock Division (FOSC<2:0>) (CPDIV<1:0>) None (11) 2 (10) EC  ...

Page 42

... PIC18F47J53 FAMILY 3.4 USB From INTOSC The 8 MHz INTOSC included in all PIC18F47J53 family devices is extremely accurate. When the 8 MHz INTOSC is used with the 96 MHz PLL, it may be used to derive the USB module clock. The high accuracy of the INTOSC will allow the application to meet low-speed USB signal rate specifications ...

Page 43

... Microchip Technology Inc. PIC18F47J53 FAMILY 3.5.2 OSCILLATOR TRANSITIONS PIC18F47J53 family devices contain circuitry to prevent clock glitches when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...

Page 44

... PIC18F47J53 FAMILY REGISTER 3-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 (ACCESS F87h) (2) U-0 R-0 U-0 SOSCRUN bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 Unimplemented: Read as 0 bit 6 SOSCRUN: SOSC Run Status bit 1 System clock comes from secondary SOSC ...

Page 45

... Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F47J53 family can also be configured to provide a reference clock output signal to a port pin. This feature is avail- able in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...

Page 46

... RTC. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PMP, INTx pins, etc.). Peripherals that may add significant current Section 31.2 DC Characteristics: Power-Down and Supply Current PIC18F47J53 Family (Industrial). 3.8 Power-up Delays Power-up delays are controlled by two timers so that no of the external Reset circuitry is required for most applica- tions ...

Page 47

... The power-managed modes include power-saving features offered on previous PIC devices, such as clock switching, ULPWU and Sleep mode. In addition, the PIC18F47J53 family devices add a new power-managed Deep Sleep mode. 4.1 Selecting Power-Managed Modes Selecting a power-managed mode requires these decisions: Will the CPU be clocked? • ...

Page 48

... PIC18F47J53 FAMILY TABLE 4-1: LOW-POWER MODES DSCONH<7> OSCCON<7,1:0> Mode (1) (1) DSEN IDLEN SCS<1:0> Sleep 0 0 Deep 1 0 (3) Sleep PRI_RUN N/A 0 SEC_RUN N/A 0 RC_RUN N/A 0 PRI_IDLE 0 1 SEC_IDLE 0 1 RC_IDLE 0 1 Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed. 2: Deep Sleep turns off the internal core voltage regulator to power down core logic. See Section 4.6 Deep Sleep Mode” ...

Page 49

... Note 1024 OST OSC 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to 01, entry to SEC_RUN mode will not occur. If the ...

Page 50

... PIC18F47J53 FAMILY 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications, which are not highly timing-sensitive or do not require high-speed clocks at all times ...

Page 51

... T OST OSC PLL 2010 Microchip Technology Inc. PIC18F47J53 FAMILY When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 4-6 will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 28 ...

Page 52

... PIC18F47J53 FAMILY 4.4 Idle Modes The Idle modes allow the controllers CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to 1 when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS< ...

Page 53

... TRANSITION TIMING FOR ENTRY TO IDLE MODE OSC1 CPU Clock Peripheral Clock Program PC Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 OSC1 CPU Clock Peripheral Clock Program Counter Wake Event 2010 Microchip Technology Inc. PIC18F47J53 FAMILY CSD PC Preliminary DS39964B-page 53 ...

Page 54

... PIC18F47J53 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP ...

Page 55

... Executing the SLEEP instruction immediately after setting DSEN (no delay or interrupts in between) 2010 Microchip Technology Inc. PIC18F47J53 FAMILY In order to minimize the possibility of inadvertently enter- ing Deep Sleep, the DSEN bit is cleared in hardware two instruction cycles after having been set. Therefore, ...

Page 56

... PIC18F47J53 FAMILY 4.6.2 I/O PINS DURING DEEP SLEEP During Deep Sleep, the general purpose I/O pins will retain their previous states. Pins that are configured as inputs (TRIS bit set) prior to entry into Deep Sleep will remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRIS bit clear) prior to entry into Deep Sleep will remain as output pins during Deep Sleep ...

Page 57

... Deep Sleep bit, DS (WDTCON<3>). This bit will be set if there was an exit from Deep Sleep mode. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 14. Clear the Deep Sleep bit, DS (WDTCON<3>). 15. Determine the wake-up source by reading the DSWAKEH and DSWAKEL registers. 16. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCONL< ...

Page 58

... PIC18F47J53 FAMILY 4.6.9 DEEP SLEEP MODE REGISTERS Deep Sleep mode registers are Register 4-1 through Register 4-6. REGISTER 4-1: DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh) R/W-0 U-0 U-0 (1) DSEN bit Reserved bit Legend Readable bit W Writable bit -n Value at POR 1 Bit is set ...

Page 59

... DSINT0: Interrupt-on-Change bit 1 Interrupt-on-change was asserted during Deep Sleep 0 Interrupt-on-change was not asserted during Deep Sleep 2010 Microchip Technology Inc. PIC18F47J53 FAMILY (1) R/W-xxxx U Unimplemented bit, read as 0 0 Bit is cleared drops below the normal BOR threshold outside of Deep ...

Page 60

... PIC18F47J53 FAMILY REGISTER 4-6: DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah) R/W-0 U-0 R/W-0 DSFLT DSULP bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 DSFLT: Deep Sleep Fault Detected bit Deep Sleep Fault was detected during Deep Sleep ...

Page 61

... Configure Sleep mode. 8. Enter Sleep mode. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY When the voltage on RA0 drops below V will be generated, which will cause the device to wake-up and execute the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. ...

Page 62

... PIC18F47J53 FAMILY EXAMPLE 4-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION // //Configure a remappable output pin with interrupt capability //for ULPWU function (RP21 > RD4/INT1 in this example) // RPOR21 13;// ULPWU function mapped to RP21/RD4 RPINR1 21;// INT1 mapped to RP21 (RD4) // //Charge the capacitor on RA0 // TRISAbits.TRISA0 0; PORTAbits.RA0 1; for < 10000; i) Nop(); ...

Page 63

... ECCP3MD ECCP2MD ECCP1MD UART2MD UART1MD Not implemented on 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). Note 1: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 4.8 Peripheral Module Disable All peripheral modules (except for I/O ports) also have a second control bit that can disable their functionality. ...

Page 64

... PIC18F47J53 FAMILY NOTES: DS39964B-page 64 Preliminary 2010 Microchip Technology Inc. ...

Page 65

... RESET The PIC18F47J53 family of devices differentiates among various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset i) Stack Underflow Reset ...

Page 66

... PIC18F47J53 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER (ACCESS FD0h) R/W-0 U-0 R/W-1 IPEN CM bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 Enable priority levels on interrupts 0 Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘ ...

Page 67

... POR is not reset to 1 by any hardware event. To capture multiple events, the user manually resets the bit to 1 in software following any POR. 5.4 Brown-out Reset (BOR) The F devices in the PIC18F47J53 family incorporate two types of BOR circuits: one which monitors V and one which monitors V DDCORE DD circuit can be active at a time ...

Page 68

... Electrostatic always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F47J53 family devices is a 5-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval  ms. While the PWRT is counting, the device is held in Reset ...

Page 69

... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F47J53 FAMILY T PWRT T PWRT , V RISE > 3. PWRT Preliminary ): CASE 1 ...

Page 70

... PIC18F47J53 FAMILY 5.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a Reset state depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...

Page 71

... See Table 5-1 for Reset value for specific condition Not implemented for PIC18F2XJ53 devices. Not implemented for LF devices. 6: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...

Page 72

... PIC18F47J53 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F2XJ53 PIC18F4XJ53 POSTINC2 PIC18F2XJ53 PIC18F4XJ53 POSTDEC2 PIC18F2XJ53 PIC18F4XJ53 PREINC2 PIC18F2XJ53 PIC18F4XJ53 PLUSW2 PIC18F2XJ53 PIC18F4XJ53 FSR2H PIC18F2XJ53 PIC18F4XJ53 FSR2L PIC18F2XJ53 PIC18F4XJ53 STATUS PIC18F2XJ53 PIC18F4XJ53 TMR0H PIC18F2XJ53 PIC18F4XJ53 TMR0L PIC18F2XJ53 ...

Page 73

... See Table 5-1 for Reset value for specific condition Not implemented for PIC18F2XJ53 devices. Not implemented for LF devices. 6: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...

Page 74

... PIC18F47J53 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR1 PIC18F2XJ53 PIC18F4XJ53 PIR1 PIC18F2XJ53 PIC18F4XJ53 PIE1 PIC18F2XJ53 PIC18F4XJ53 RCSTA2 PIC18F2XJ53 PIC18F4XJ53 OSCTUNE PIC18F2XJ53 PIC18F4XJ53 T1GCON PIC18F2XJ53 PIC18F4XJ53 T3GCON PIC18F2XJ53 PIC18F4XJ53 (5) TRISE PIC18F2XJ53 PIC18F4XJ53 (5) TRISD PIC18F2XJ53 PIC18F4XJ53 TRISC PIC18F2XJ53 ...

Page 75

... See Table 5-1 for Reset value for specific condition Not implemented for PIC18F2XJ53 devices. Not implemented for LF devices. 6: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...

Page 76

... PIC18F47J53 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PMCONL PIC18F2XJ53 PIC18F4XJ53 PMMODEH PIC18F2XJ53 PIC18F4XJ53 PMMODEL PIC18F2XJ53 PIC18F4XJ53 PMDOUT2H PIC18F2XJ53 PIC18F4XJ53 PMDOUT2L PIC18F2XJ53 PIC18F4XJ53 PMDIN2H PIC18F2XJ53 PIC18F4XJ53 PMDIN2L PIC18F2XJ53 PIC18F4XJ53 PMEH PIC18F2XJ53 PIC18F4XJ53 PMEL PIC18F2XJ53 PIC18F4XJ53 PMSTATH PIC18F2XJ53 ...

Page 77

... See Table 5-1 for Reset value for specific condition Not implemented for PIC18F2XJ53 devices. Not implemented for LF devices. 6: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...

Page 78

... PIC18F47J53 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices TMR8 PIC18F2XJ53 PIC18F4XJ53 PR8 PIC18F2XJ53 PIC18F4XJ53 T8CON PIC18F2XJ53 PIC18F4XJ53 PSTR3CON PIC18F2XJ53 PIC18F4XJ53 ECCP3AS PIC18F2XJ53 PIC18F4XJ53 ECCP3DEL PIC18F2XJ53 PIC18F4XJ53 CCPR3H PIC18F2XJ53 PIC18F4XJ53 CCPR3L PIC18F2XJ53 PIC18F4XJ53 CCP3CON PIC18F2XJ53 PIC18F4XJ53 CCPR4H PIC18F2XJ53 ...

Page 79

... See Table 5-1 for Reset value for specific condition Not implemented for PIC18F2XJ53 devices. Not implemented for LF devices. 6: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction Wake From Deep Stack Resets ...

Page 80

... PIC18F47J53 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RPOR5 PIC18F2XJ53 PIC18F4XJ53 RPOR4 PIC18F2XJ53 PIC18F4XJ53 RPOR3 PIC18F2XJ53 PIC18F4XJ53 RPOR2 PIC18F2XJ53 PIC18F4XJ53 RPOR1 PIC18F2XJ53 PIC18F4XJ53 RPOR0 PIC18F2XJ53 PIC18F4XJ53 Legend unchanged unknown unimplemented bit, read as 0’ value depends on condition. ...

Page 81

... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address returns all 0s (a NOP instruction). The PIC18F47J53 family offers a range of on-chip Flash program memory sizes, from 64 Kbytes (up to 32,768 single-word (65,536 single-word instructions). ...

Page 82

... CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. Table 6-1 provides the actual addresses of the Flash Configuration Word for devices in the PIC18F47J53 family. Figure 6-2 displays their location in the memory map with other memory vectors. Additional details on the device Configuration Words are provided in Section 28.1 “ ...

Page 83

... Microchip Technology Inc. PIC18F47J53 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs) ...

Page 84

... PIC18F47J53 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off of the stack ...

Page 85

... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...

Page 86

... PIC18F47J53 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by 4 to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the PC is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...

Page 87

... ADDWF 2010 Microchip Technology Inc. PIC18F47J53 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...

Page 88

... DS39964B-page 88 6.3.1 USB RAM All 3.8 Kbytes of the GPRs implemented on the PIC18F47J53 family devices can be accessed simulta- neously by both the microcontroller core and the Serial Interface Engine (SIE) of the USB module. The SIE uses a dedicated USB DMA engine to store any incoming data packets (OUT/SETUP) directly into the main system data memory ...

Page 89

... The relationship between the BSRs value and the bank division in data memory is illustrated in Figure 6-7. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Because registers can share the same low-order address, the user must always be careful to ensure that the proper bank is selected before perform- ing a data read or write ...

Page 90

... PIC18F47J53 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18F47J53 FAMILY DEVICES BSR3:BSR0 00h 0000 Bank 0 FFh 00h 0001 Bank 1 FFh 00h 0010 Bank 2 FFh 00h 0011 Bank 3 FFh 00h 0100 Bank 4 FFh 00h 0101 Bank 5 FFh 00h 0110 Bank 6 FFh 00h 0111 ...

Page 91

... BSR and the 8-bit address included in the opcode for the data memory address. When a is 0, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Data Memory 000h 7 00h Bank 0 ...

Page 92

... PIC18F47J53 FAMILY 6.3.5 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and periph- eral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F40h to FFFh) ...

Page 93

... TMR5H F43h F23h TMR5L F42h ODCON1 F22h T5CON F41h ODCON2 F21h T5GCON F40h ODCON3 F20h TMR6 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Address Name Address Name F1Fh PR6 EFFh RPINR24 F1Eh T6CON EFEh RPINR23 F1Dh TMR8 EFDh RPINR22 F1Ch ...

Page 94

... Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). 2: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 3: DS39964B-page 94 PMADDRH/L and PMDOUT2H/L: In this case, these named buffer pairs are actually the same physical registers ...

Page 95

... Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). Note 1: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53 Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Bit 5 Bit 4 ...

Page 96

... Legend: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). Note 1: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). 2: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 3: DS39964B-page 96 Bit 5 Bit 4 Bit 3 ...

Page 97

... Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). Note 1: 2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). 3: Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Bit 5 Bit 4 ...

Page 98

... Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 3: DS39964B-page 98 Bit 5 Bit 4 ...

Page 99

... Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 3: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY ...

Page 100

... Note 1: Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 3: DS39964B-page 100 Bit 5 Bit 4 ...

Page 101

... Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 2: Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53). Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53). 3: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY ...

Page 102

... PIC18F47J53 FAMILY 6.3.6 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled ...

Page 103

... LSB. This address specifies either a register address in one of the banks of data RAM (Section 6.3.4 General Purpose 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Register File” location in the Access Bank (Section 6.3.3 Access Bank) as the data source for the instruction. ...

Page 104

... PIC18F47J53 FAMILY 6.4.3.1 FSR Registers and the INDF Operand (INDF) At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...

Page 105

... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations ...

Page 106

... PIC18F47J53 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space ...

Page 107

... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...

Page 108

... PIC18F47J53 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...

Page 109

... Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

Page 110

... PIC18F47J53 FAMILY FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) The Table Pointer actually points to one of 64 holding registers, the address of which is determined by Note 1: TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 Writing to Flash Program Memory. ...

Page 111

... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as 0 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-x R/W-0 FREE WRERR WREN U Unimplemented bit, read as ‘ ...

Page 112

... PIC18F47J53 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TABLE POINTER REGISTER ...

Page 113

... MOVF TABLAT, W MOVWF WORD_ODD 2010 Microchip Technology Inc. PIC18F47J53 FAMILY The TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...

Page 114

... PIC18F47J53 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...

Page 115

... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC the PIC18F47J53 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten sequence. ...

Page 116

... PIC18F47J53 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE ...

Page 117

... FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING). The PIC18F47J53 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1. Load the Table Pointer register with the address of the data to be written ...

Page 118

... PIC18F47J53 FAMILY 7.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.4 UNEXPECTED TERMINATION OF WRITE OPERATION ...

Page 119

... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F47J53 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 ARG2 -> ; PRODH:PRODL ...

Page 120

... PIC18F47J53 FAMILY Example 8-3 provides the instruction sequence for unsigned multiplication. Equation 8-1 provides the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 ARG1H:ARG1L · ARG2H:ARG2L 16 (ARG1H · ARG2H · (ARG1H · ARG2L · 2 ...

Page 121

... INTERRUPTS Devices of the PIC18F47J53 family have multiple inter- rupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...

Page 122

... PIC18F47J53 FAMILY FIGURE 9-1: PIC18F47J53 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> DS39964B-page 122 TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE ...

Page 123

... Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...

Page 124

... PIC18F47J53 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 All PORTB pull-ups are disabled 0 PORTB pull-ups are enabled by individual port latch values ...

Page 125

... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 INT2IE ...

Page 126

... PIC18F47J53 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh) ...

Page 127

... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 USBIF BCL1IF HLVDIF U Unimplemented bit, read as 0 ...

Page 128

... PIC18F47J53 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 R/W-0 R-0 SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 The transmission/reception is complete (must be cleared in software) ...

Page 129

... No TMR register capture occurred Compare Mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode Unused in this mode. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U Unimplemented bit, read as 0 ...

Page 130

... PIC18F47J53 FAMILY REGISTER 9-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 (ACCESS F98h) U-0 U-0 R-0 CM3IF bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-6 Unimplemented: Read as 0 bit 5 CM3IF: Comparator Interrupt Flag bit 1 Comparator3 input has changed (must be cleared in software) ...

Page 131

... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 Enables the TMR1 overflow interrupt 0 Disables the TMR1 overflow interrupt These bits are unimplemented on 28-pin devices. Note 1: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U Unimplemented bit, read as 0 ...

Page 132

... PIC18F47J53 FAMILY REGISTER 9-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 Enabled 0 Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit 1 Enabled ...

Page 133

... CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit 1 Enabled 0 Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 Enabled 0 Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 Enabled 0 Disabled 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CTMUIE U Unimplemented bit, read as 0 0 Bit is cleared Preliminary R/W-0 R/W-0 ...

Page 134

... PIC18F47J53 FAMILY REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 (ACCESS F8Eh) R/W-0 R/W-0 R/W-0 CCP10IE CCP9IE CCP8IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-1 CCP10IE:CCP4IE: CCP<10:4> Interrupt Enable bits 1 Enabled 0 Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 Enabled 0 Disabled ...

Page 135

... High priority 0 Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 High priority 0 Low priority These bits are unimplemented on 28-pin devices. Note 1: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 136

... PIC18F47J53 FAMILY REGISTER 9-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h) R/W-1 R/W-1 R/W-1 OSCFIP CM2IP CM1IP bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 High priority 0 Low priority bit 6 CM2IP: Comparator 2 Interrupt Priority bit ...

Page 137

... TMR3GIP: Timer3 Gate Interrupt Priority bit 1 High priority 0 Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 High priority 0 Low priority 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CTMUIP U Unimplemented bit, read as 0 0 Bit is cleared Preliminary ...

Page 138

... PIC18F47J53 FAMILY REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 (ACCESS F90h) R/W-1 R/W-1 R/W-1 CCP10IP CCP9IP CCP8IP bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-1 CCP10IP:CCP4IP: CCP<10:4> Interrupt Priority bits 1 High priority 0 Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit ...

Page 139

... For details on bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register 5-1. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-1 R-1 R Unimplemented bit, read as 0 ...

Page 140

... PIC18F47J53 FAMILY 9.6 INTx Pin Interrupts External interrupts on the INT0, INT1, INT2 and INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set ( 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit and INTxIF are set ...

Page 141

... RD PORT Note 1: I/O pins have diode protection 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...

Page 142

... PIC18F47J53 FAMILY 10.1.3 INTERFACING SYSTEM Though the V of the PIC18F47J53 family is 3.6V, DDMAX these devices are still capable of interfacing with 5V systems, even if the V of the target system is above IH 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 10-2), clearing the LAT bit for that ...

Page 143

... ECCP2OD: ECCP2 Open-Drain Output Enable bit 1 Open-drain capability is enabled 0 Open-drain capability is disabled bit 0 ECCP1OD: ECCP1 Open-Drain Output Enable bit 1 Open-drain capability is enabled 0 Open-drain capability is disabled 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 CCP5OD CCP4OD ECCP3OD U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 144

... PIC18F47J53 FAMILY REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h) U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-4 Unimplemented: Read as 0 bit 3 CCP10OD: CCP10 Open-Drain Output Enable bit 1 Open-drain capability is enabled 0 Open-drain capability is disabled ...

Page 145

... CMCON register. To use RA<3:0> as digital inputs also necessary to turn off the comparators Power-on Reset (POR), RA5 and Note: RA<3:0> are configured as analog inputs and read as 0. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY U-0 U-0 R/W-0 (1) RTSECSEL1 U Unimplemented bit, read as ‘ ...

Page 146

... Legend: DIG Digital level output; TTL TTL input buffer Schmitt Trigger input buffer; ANA Analog level input/output Dont care (TRIS bit does not affect port direction or is overridden for this option) This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and Note 1: PIC18LF47J53) ...

Page 147

... Legend: DIG Digital level output; TTL TTL input buffer Schmitt Trigger input buffer; ANA Analog level input/output Dont care (TRIS bit does not affect port direction or is overridden for this option) This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and Note 1: PIC18LF47J53) ...

Page 148

... PIC18F47J53 FAMILY 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit ( 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit ( 0) will make the corresponding PORTB pin an output (i ...

Page 149

... Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting Note 1: the appropriate bits in the ANCON1 register. 2: All other pin functions are disabled when ICSP or ICD is enabled. Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 3: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY I/O ...

Page 150

... Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting the appropriate bits in the ANCON1 register. All other pin functions are disabled when ICSP or ICD is enabled Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). DS39964B-page 150 I/O I/O Type ...

Page 151

... Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting Note 1: the appropriate bits in the ANCON1 register. All other pin functions are disabled when ICSP or ICD is enabled. 2: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53). 3: TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name ...

Page 152

... PIC18F47J53 FAMILY 10.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISC. Setting a TRISC bit ( 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit ( 0) will make the corresponding PORTC pin an output (i ...

Page 153

... C/SMBus input buffer Dont care (TRIS bit does not affect port direction or is overridden for this option) Enhanced PWM output is available only on PIC18F4XJ53 devices. Note 1: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and 2: PIC18LF47J53). 2010 Microchip Technology Inc. ...

Page 154

... C/SMBus input buffer Dont care (TRIS bit does not affect port direction or is overridden for this option) Enhanced PWM output is available only on PIC18F4XJ53 devices. Note 1: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and 2: PIC18LF47J53). TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC ...

Page 155

... All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output POR, these pins are configured as Note: digital inputs. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY EXAMPLE 10-5: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ...

Page 156

... Legend: DIG Digital level output; TTL TTL input buffer Schmitt Trigger input buffer; I input buffer Dont care (TRIS bit does not affect port direction or is overridden for this option). This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and Note 1: PIC18LF47J53) ...

Page 157

... Legend: DIG Digital level output; TTL TTL input buffer Schmitt Trigger input buffer; I input buffer Dont care (TRIS bit does not affect port direction or is overridden for this option). This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and Note 1: PIC18LF47J53) ...

Page 158

... PORTE, TRISE and LATE Registers PORTE is available only in 44-pin devices. Note: Depending on the particular PIC18F47J53 family device selected, PORTE is implemented in two different ways. For 44-pin devices, PORTE is a 3-bit wide port. Three pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ AN7/PMCS) are individually configurable as inputs or outputs ...

Page 159

... All PORTD pull-ups are disabled 1 PORTD pull-ups are enabled for any input pad bit 6 REPU: PORTE Pull-up Enable bit 0 All PORTE pull-ups are disabled 1 PORTE pull-ups are enabled for any input pad 2010 Microchip Technology Inc. PIC18F47J53 FAMILY I/O I/O Type I ST PORTE< ...

Page 160

... I/O pins. The challenge is even greater on low pin count devices similar to the PIC18F47J53 family application that needs to use more than one peripheral, multi- plexed on a single pin, inconvenient workarounds in application code or a complete redesign may be the only option ...

Page 161

... Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. Note 1: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY with one of the pin selectable peripherals. Programming a given peripherals bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral. ...

Page 162

... PIC18F47J53 FAMILY 10.7.3.2 Output Mapping In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control reg- ister associated with a particular pin dictates the periph- eral output to be mapped. The RPORx registers are used to control output mapping. The value of the bit field corre- sponds to one of the peripherals and that peripheral’ ...

Page 163

... ESD or other external events), a Configuration Mismatch Reset will be triggered. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 10.7.4.3 Configuration Bit Pin Select Lock As an additional level of safety, the device can be con- figured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CONFIG3H< ...

Page 164

... PIC18F47J53 FAMILY Choosing the configuration requires the review of all PPSs and their pin assignments, especially those that will not be used in the application. In all cases, unused pin selectable peripherals should be disabled com- pletely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output ...

Page 165

... PERIPHERAL PIN SELECT REGISTERS The PIC18F47J53 family of devices implements a total of 37 registers for remappable peripheral configuration of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. REGISTER 10-5: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED PPSCON) U-0 U-0 U-0 bit 7 Legend: ...

Page 166

... PIC18F47J53 FAMILY REGISTER 10-8: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE3h) U-0 U-0 U-0 bit 7 Legend: R/W Readable bit, Writable bit if IOLOCK Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 INTR3R<4:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits ...

Page 167

... W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 IC3R<4:0>: Assign Input Capture 3 (ECCP3) to the Corresponding RPn Pin bits 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-1 R/W-1 R/W-1 IC1R4 IC1R3 IC1R2 U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 168

... PIC18F47J53 FAMILY REGISTER 10-14: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h) U-0 U-0 U-0 bit 7 Legend: R/W Readable bit, Writable bit if IOLOCK Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 T1GR<4:0>: Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits ...

Page 169

... Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-1 R/W-1 R/W-1 RX2DT2R4 RX2DT2R3 RX2DT2R2 U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 170

... PIC18F47J53 FAMILY REGISTER 10-21: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFDh) U-0 U-0 U-0 bit 7 Legend: R/W Readable bit, Writable bit if IOLOCK Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 SCK2R<4:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits ...

Page 171

... Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-14 for peripheral function numbers) 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 RP0R4 RP0R3 RP0R2 U Unimplemented bit, read as 0 ...

Page 172

... PIC18F47J53 FAMILY REGISTER 10-27: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC3h) U-0 U-0 U-0 bit 7 Legend: R/W Readable bit, Writable bit if IOLOCK Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits ...

Page 173

... Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 10-14 for peripheral function numbers) 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 RP6R4 RP6R3 RP6R2 U Unimplemented bit, read as 0 ...

Page 174

... PIC18F47J53 FAMILY REGISTER 10-33: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED EC9h) U-0 U-0 U-0 bit 7 Legend: R/W Readable bit, Writable bit if IOLOCK Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits ...

Page 175

... Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 10-14 for peripheral function numbers) 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 RP12R4 RP12R3 RP12R2 U Unimplemented bit, read as 0 ...

Page 176

... PIC18F47J53 FAMILY REGISTER 10-39: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED2h) U-0 U-0 U-0 bit 7 Legend: R/W Readable bit, Writable bit if IOLOCK Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits ...

Page 177

... Unimplemented: Read as 0 bit 4-0 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 10-14 for peripheral function numbers) RP23 pins are not available on 28-pin devices. Note 1: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 RP21R3 RP21R2 U Unimplemented bit, read as 0 ...

Page 178

... PIC18F47J53 FAMILY REGISTER 10-45: RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED ED8h) U-0 U-0 U-0 bit 7 Legend: R/W Readable bit, Writable bit if IOLOCK Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-5 Unimplemented: Read as 0 bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 10-14 for peripheral function numbers) RP24 pins are not available on 28-pin devices ...

Page 179

... PIC18LF46J53 and PIC18LF47J53. FIGURE 11-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Key features of the PMP module are: • bits of addressing when using data/address multiplexing • Programmable Address Lines One Chip Select Line • ...

Page 180

... PIC18F47J53 FAMILY 11.1 Module Registers The PMP module has a total of 14 Special Function Registers (SFRs) for its operation, plus one additional register to set configuration options. Of these, eight registers are used for control and six are used for PMP data transfer. 11.1.1 CONTROL REGISTERS The eight PMP Control registers are: • ...

Page 181

... Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) This register is only available on 44-pin devices. Note 1: 2: These bits have no effect when their corresponding pins are used as address lines. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY (2) (2) U-0 R/W-0 CS1P U Unimplemented bit, read as 0 ...

Page 182

... PIC18F47J53 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh) R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7 BUSY: Busy bit (Master mode only Port is busy 0 Port is not busy bit 6-5 IRQM<1:0>: Interrupt Request Mode bits 11 Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode read or write operation when PMA< ...

Page 183

... Wait This register is only available on 44-pin devices. Note 1: 2: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> 0000. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U Unimplemented bit, read as 0 0 Bit is cleared ; multiplexed address phase ...

Page 184

... PIC18F47J53 FAMILY REGISTER 11-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h) R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-6 PTEN<15:14>: PMCS1 Port Enable bits 1 PMA<15:14> function as either PMA<15:14> or PMCS2 and PMCS1 0 PMA<15:14> function as port I/O bit 5-0 PTEN< ...

Page 185

... OB<3:0>E: Output Buffer x Status Empty bits 1 Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted Note 1: This register is only available on 44-pin devices. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY U-0 R-0 R-0 IB3F IB2F U Unimplemented bit, read as ‘ ...

Page 186

... PIC18F47J53 FAMILY 11.1.2 DATA REGISTERS The PMP module uses eight registers for transferring data into and out of the microcontroller. They are arranged as four pairs to allow the option of 16-bit data operations: PMDIN1H and PMDIN1L PMDIN2H and PMDIN2L PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L • ...

Page 187

... Bit is set bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. Note 1: 2010 Microchip Technology Inc. PIC18F47J53 FAMILY (1) R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> Unimplemented bit, read as 0 ...

Page 188

... PIC18F47J53 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is configured using the MODE<1:0> PMMODEH register. The setting affects whether the module acts as a slave or a master, and it determines the usage of the control pins. 11.2.1 LEGACY MODE (PSP) In Legacy mode (PMMODEH< ...

Page 189

... PMRD PMD<7:0> IBF OBE PMPIF 2010 Microchip Technology Inc. PIC18F47J53 FAMILY 11.2.3 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCSx 1 and PMRD 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented on to PMD<7:0>. Figure 11-4 provides the timing for the control signals in Read mode ...

Page 190

... PIC18F47J53 FAMILY 11.2.4 BUFFERED PARALLEL SLAVE PORT MODE Buffered Parallel Slave Port mode is functionally identical to the legacy PSP mode with one exception, the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM<1:0> bits are set to ‘ ...

Page 191

... ADDR<1:0>. Table 11-1 provides the corresponding FIGURE 11-7: PARALLEL SLAVE PORT READ WAVEFORMS PMCSx PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF 2010 Microchip Technology Inc. PIC18F47J53 FAMILY TABLE 11-1: SLAVE MODE BUFFER ADDRESSING Output PMA<1:0> Register (Buffer) PMDOUT1L (0) 00 PMDOUT1H (1) 01 ...

Page 192

... PIC18F47J53 FAMILY 11.2.5.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCSx 1 and PMWR 1), the data from PMD<7:0> is captured into one of the four input buffer bytes. Which byte is written depends on the 2-bit address placed on ADDRL<1:0>. Table 11-1 provides the corresponding input registers and their associated address ...

Page 193

... PMCONL register. Note that the polarity of control signals that share the 2010 Microchip Technology Inc. PIC18F47J53 FAMILY same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used. ...

Page 194

... PIC18F47J53 FAMILY FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 11-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) ...

Page 195

... Then, the read line (PMRD) is strobed. The read data is placed into the PMDIN1L register. 2010 Microchip Technology Inc. PIC18F47J53 FAMILY If the 16-bit mode is enabled (MODE16 1), the read of the low byte of the PMDIN1L register will initiate two bus reads. The first read data byte is placed into the PMDIN1L register and the second read data is placed into the PMDIN1H ...

Page 196

... PIC18F47J53 FAMILY 11.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states. FIGURE 11-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS ...

Page 197

... READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY 2010 Microchip Technology Inc. PIC18F47J53 FAMILY Data Data WAITE<1:0> WAITM<3:0> 0010 ...

Page 198

... PIC18F47J53 FAMILY FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMALL ...

Page 199

... FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY 2010 Microchip Technology Inc. PIC18F47J53 FAMILY LSB MSB LSB MSB ...

Page 200

... PIC18F47J53 FAMILY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD ...

Comments to this Datasheet