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RE46C152 Datasheet - Page 6

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CMOS Ionization Smoke Detector ASIC with Interconnect,
R&E International
Timer Mode and Tone Select
A Subsidiary of Microchip Technology Inc.
Product Specification
Internal Timing – With external components as indicated on the application drawing the period of the oscillator is
nominally 1.67 seconds in standby. Every 1.66 seconds the detection circuitry is powered up for 10.5mS and the status
of the smoke comparator is latched. In addition every 40 seconds the LED driver is turned on for 10.5mS and the status
of the low battery comparator is latched. The smoke comparator status is not checked during the low battery test, during
the low battery horn warning chirp, or when the horn is on due to an alarm condition.
If an alarm condition is detected the oscillator period increases to 41.5mS.
Due to the low currents used in the oscillator the capacitor on pin 12 should be a low leakage type. Oscillator accuracy
will depend mainly on the tolerance of the RBIAS resistor and OSCAP capacitor.
Smoke Detection Circuit – The smoke comparator compares the ionization chamber voltage to a voltage derived from a
resistor divider across VDD. This divider voltage is available externally on pin 13 (VSEN). When smoke is detected this
voltage is internally increased by 130mV nominal to provide hysteresis and make the detector less sensitive to false
Pin 13 (VSEN) can be used to modify the internal set point for the smoke comparator by use of external resistors to
VDD or VSS. Nominal values for the internal resistor divider are indicated on the block diagram. These internal resistor
values can vary by up to ±20% but the resistor matching should be <2% on any one device.
The guard amplifier and outputs are always active and will be within 50mV of the DETECT input to reduce surface
leakage. The guard outputs also allow for measurement of the DETECT input without loading the ionization chamber.
Low Battery Detection - An internal reference is compared to the voltage divided VDD supply. The battery can be
checked under load via the LED low side driver output since low battery status is latched at the end of the 10.5mS LED
pulse. A Transmission switch on VSEN prevents any interaction from external adjustment resistance during the low
battery test
LED Pulse – The LED is pulsed on for 10.5mS every 40S in standby. In alarm the LED is pulsed on for 10.5mS every
Interconnect – Pin 2 (IO) provides the capability to common many detectors in a single system. If a single unit goes into
alarm the IO pin is driven high. This high signal causes the interconnected units to alarm. The LED flashes every 1S for
10.5mS on the signaling unit and is inhibited on the units that are in alarm due to the IO signal. An internal sink device
on the IO pin helps to discharge the interconnect line. This charge dump device is active for 1 clock cycle after the unit
exits the alarm condition (1.67S).
The interconnect input has a 500mS nominal digital filter. This allows for interconnection to other types of alarms
(carbon monoxide for example) that may have a pulsed interconnect signal.
Testing – At power up all internal registers are reset. The low battery set point can be tested at power up by holding
FEED and OSCAP low at power up. HB will change state as VDD passes through the low battery set point. By holding
pin 12 (OSCAP) low the internal power strobe is active. Functional testing can be accelerated by driving pin 12 with a
4kHZ square wave however the 10.5mS strobe period must be maintained for proper operation of the analog circuitry.
Please refer to the timing diagrams.
Timer Mode – The transition of pin 1 (TSTART) from a high to low level initiates an eight minute timer. During this 8
minute period the open drain NMOS on pin 4 (TSTROBE) is strobed on with the internal clock. A resistor connected to
this pin could be used to modify the detector sensitivity for the timer period.
Horn Tone – Pin 3 selects the NFPA72 horn tone (high or floating) or the 2/3 duty cycle continuous tone (low). If this pin
is externally connected high, use a current limiting resistor from pin 3 to VDD.
Reverse Battery Protection – The RE46c152 internally limits the current from VSS to VDD in the event of accidental
polarity reversal. If an input is connected to VDD it should be done through a resistance of at least 1.5K to limit the
reverse current through this path.
© 2009 Microchip Technology Inc.
DS22175A-page 6

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