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PIC16(L)F1825 Datasheet

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PIC16(L)F1825/1829
Data Sheet
14/20-Pin Flash Microcontrollers
with XLP Technology
 2010-2012 Microchip Technology Inc.
DS41440C

Summary of Contents

Page 1

... Flash Microcontrollers 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Data Sheet with XLP Technology DS41440C ...

Page 2

... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010-2012, Microchip Technology Incorporated, Printed in the U ...

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... In-Circuit Debug (ICD) via Two Pins Enhanced Low-Voltage Programming (LVP) Programmable Code Protection Power-Saving Sleep mode 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Extreme Low-Power Management PIC16LF1825/1829 with XLP: Sleep mode 1.8V, typical Watchdog Timer: 300 nA @ 1.8V, typical • ...

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... DS41441 PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers. DS41419 PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers. 3: DS41440 PIC16(L)F1825/1829 Data Sheet, 14/20-Pin Flash Microcontrollers. 4: DS41391 PIC16(L)F1826/1827 Data Sheet, 18/20/28-Pin Flash Microcontrollers. 5: DS41453 PIC16(L)F1847 Data Sheet, 18/20/28-Pin Flash Microcontrollers. 6: ...

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... FIGURE 1: 14-PIN DIAGRAM FOR PIC16(L)F1825 PDIP, SOIC, TSSOP MCLR/V FIGURE 2: 16-PIN DIAGRAM FOR PIC16(L)F1825 QFN MCLR/V 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 RA0/ICSPDAT RA5 13 2 RA4 RA1/ICSPCLK 12 3 /RA3 RA2 RC5 RC0 5 10 RC1 ...

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... PIC16(L)F1825/1829 TABLE 1: 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1825) RA0 13 12 AN0 V - CPS0 REF DACOUT RA1 12 11 AN1 V CPS1 C12IN0- REF RA2 11 10 AN2 CPS2 RA3 4 3 RA4 3 2 AN3 CPS3 RA5 2 1 ...

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... FIGURE 3: 20-PIN DIAGRAM FOR PIC16(L)F1829 PDIP, SOIC, SSOP FIGURE 4: PIC16(L)F1829 20-PIN QFN QFN 4x4 MCLR/V 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 RA5 RA0/ICSPDAT 19 2 RA4 RA1/ICSPCLK 18 3 RA2 MCLR/V /RA3 RC5 RC0 16 5 RC4 ...

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... PIC16(L)F1825/1829 TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F1829) RA0 19 16 AN0 V - CPS0 C1IN REF DACOUT RA1 18 15 AN1 V CPS1 C12IN0- REF RA2 17 14 AN2 CPS2 C1OUT RA3 4 1 RA4 3 20 AN3 CPS3 RA5 2 19 ...

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... Appendix B: Migrating From Other PIC® Devices ... 437 The Microchip Web Site ... 447 Customer Change Notification Service ... 447 Customer Support ... 447 Reader Response ... 448 Product Identification System ... 449 Worldwide Sales and Service ... 450 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 DS41440C-page 9 ...

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... PIC16(L)F1825/1829 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

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... DEVICE OVERVIEW The PIC16(L)F1825/1829 are described within this data sheet. They are available in 14/20 pin packages. Figure 1-1 shows a block diagram PIC16(L)F1825/1829 devices. Tables 1-2 the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral ADC Capacitive Sensing (CPS) Module ...

Page 12

... PIC16(L)F1825/1829 FIGURE 1-1: PIC16(L)F1825/1829 BLOCK DIAGRAM CLKR Clock Reference OSC2/CLKOUT Timing Generation OSC1/CLKIN INTRC Oscillator MCLR ADC Timer0 10-Bit SR ECCP1 Latch Note 1: See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. 2: PIC16(L)F1829 only. 3: DS41440C-page 12 ...

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... TABLE 1-2: PIC16(L)F1825 PINOUT DESCRIPTION Name Function RA0/AN0/CPS0/C1IN/V -/ RA0 REF (1) (1) DACOUT/TX /CK / AN0 ICSPDAT/ICDDAT CPS0 C1IN V REF DACOUT TX CK ICSPDAT ICDDAT RA1/AN1/CPS1/C12IN0-/V / RA1 REF (1) (1) SRI/RX /DT /ICSPCLK/ AN1 ICDCLK CPS1 C12IN0- V REF SRI RX DT ICSPCLK ICDCLK RA2/AN2/CPS2/T0CKI/INT/ RA2 C1OUT/SRQ/CCP3/FLT0 AN2 CPS2 ...

Page 14

... PIC16(L)F1825/1829 TABLE 1-2: PIC16(L)F1825 PINOUT DESCRIPTION (CONTINUED) Name Function RA4/AN3/CPS3/OSC2/ RA4 CLKOUT/T1OSO/CLKR/ AN3 (1) (1) (1,2) SDO1 /P2B /T1G CPS3 OSC2 CLKOUT T1OSO CLKR SDO1 P2B T1G RA5/CLKIN/OSC1/T1OSI/ RA5 (1) (1) T1CKI/P2A /CCP2 CLKIN OSC1 T1OSI T1CKI P2A CCP2 RC0/AN4/CPS4/C2IN/SCL/ RC0 (1) SCK/P1D ...

Page 15

... TABLE 1-2: PIC16(L)F1825 PINOUT DESCRIPTION (CONTINUED) Name Function RC3/AN7/CPS7/C12IN3-/ RC3 (1,2) (1,2) (1,2) P2A /CCP2 /P1C / AN7 (1,2) SS1 /MDMIN CPS7 C12IN3- P2A CCP2 P1C SS1 MDMIN (1,2) RC4/C2OUT/SRNQ/P1B/TX / RC4 (1,2) CK /MDOUT C2OUT SRNQ P1B TX CK MDOUT (1,2) (1,2) RC5/P1A/CCP1/DT /RX / RC5 MDCIN2 P1A CCP1 RX DT MDCIN2 ...

Page 16

... PIC16(L)F1825/1829 TABLE 1-3: PIC16(L)F1829 PINOUT DESCRIPTION Name Function RA0/AN0/CPS0/C1IN/V -/ RA0 REF DACOUT/ICSPDAT/ICDDAT AN0 CPS0 C1IN V REF DACOUT ICSPDAT ICDDAT RA1/AN1/CPS1/C12IN0-/V / RA1 REF SRI/ICSPCLK/ICDCLK AN1 CPS1 C12IN0- V REF SRI ICSPCLK ICDCLK RA2/AN2/CPS2/T0CKI/INT/ RA2 C1OUT/SRQ/CCP3/FLT0 AN2 CPS2 T0CKI INT C1OUT SRQ CCP3 ...

Page 17

... Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input High Voltage XTAL Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Input Output Type Type TTL CMOS General purpose I/O. CMOS — ...

Page 18

... PIC16(L)F1825/1829 TABLE 1-3: PIC16(L)F1829 PINOUT DESCRIPTION (CONTINUED) Name Function RC2/AN6/CPS6/C12IN2-/ RC2 (1,2) (1,2) P1D /P2B /MDCIN1 AN6 CPS6 C12IN2- P1D P2B MDCIN1 RC3/AN7/CPS7/C12IN3-/ RC3 (1,2) (1,2) (1,2) P2A /CCP2 /P1C / AN7 MDMIN CPS7 C12IN3- P2A CCP2 P1C MDMIN (1) RC4/C2OUT/SRNQ/P1B/TX / RC4 (1) CK /MDOUT C2OUT SRNQ P1B ...

Page 19

... Section 3.5 Indirect Addressing 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 Instruction Set Summary details. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Saving, Section 3.4 for more DS41440C-page 19 ...

Page 20

... PIC16(L)F1825/1829 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control OSC1/CLKIN Timing Timing ...

Page 21

... The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. implemented for the PIC16(L)F1825/1829 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is ...

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... PIC16(L)F1825/1829 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1825/1829 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 Page 1 On-chip Program Memory Page 2 Page 3 Rollover to Page 0 Rollover to Page 3 DS41440C-page 22 3.1.1 READING PROGRAM MEMORY AS ...

Page 23

... Microchip Technology Inc. PIC16(L)F1825/1829 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16(L)F1825/1829. These registers are listed below: INDF0 INDF1 PCL STATUS Example 3-2 • ...

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... PIC16(L)F1825/1829 3.2.1.1 STATUS Register The STATUS register, shown in Register the arithmetic status of the ALU the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...

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... DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC16(L)F1825 PIC16(L)F1829 BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM (80 bytes maximum) Common RAM ...

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... TABLE 3-3: PIC16(L)F1825/1829 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H 105h 006h FSR1L 086h ...

Page 27

... TABLE 3-4: PIC16(L)F1825/1829 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 480h INDF0 500h 400h 401h INDF1 481h INDF1 501h 402h PCL 482h PCL 502h 403h STATUS 483h STATUS 503h 404h FSR0L 484h FSR0L 504h 405h FSR0H 485h FSR0H 505h 406h FSR1L 486h ...

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... TABLE 3-5: PIC16(L)F1825/1829 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H 905h 806h FSR1L 886h ...

Page 29

... TABLE 3-6: PIC16(L)F1825/1829 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H D05h C06h FSR1L C86h ...

Page 30

... PIC16(L)F1825/1829 TABLE 3-7: PIC16(L)F1825/1829 MEMORY MAP, BANK 31 (1) Bank 31 F8Ch Unimplemented Read as 0 FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh FECh STKPTR FEDh TOSL FEEh TOSH FEFh Legend: Unimplemented data memory locations, read as ‘ ...

Page 31

... Legend: Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 ...

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... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. DS41440C-page 32 Bit 5 Bit 4 Bit 3 — — ...

Page 33

... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 — ...

Page 34

... ABDOVF RCIDL Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. DS41440C-page 34 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 35

... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 — ...

Page 36

... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. DS41440C-page 36 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 37

... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 ...

Page 38

... MDCHODIS MDCHPOL MDCHSYNC x unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. DS41440C-page 38 Bit 5 Bit 4 Bit 3 Bit 2 — ...

Page 39

... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 ...

Page 40

... Legend: Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. DS41440C-page 40 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 41

... Legend: Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1829 only. 3: PIC16(L)F1825 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 ...

Page 42

... PIC16(L)F1825/1829 3.3 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. ...

Page 43

... FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

Page 44

... PIC16(L)F1825/1829 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL DS41440C-page 44 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the ...

Page 45

... These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 0x0F Return Address 0x0E Return Address 0x0D Return Address ...

Page 46

... PIC16(L)F1825/1829 FIGURE 3-8: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41440C-page 46 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved ...

Page 47

... TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Indirect Addressing 7 FSRxH Bank Select 11111 Bank 31 7 FSRxL ...

Page 48

... PIC16(L)F1825/1829 3.5.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger ...

Page 49

... Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 by device DS41440C-page 49 ...

Page 50

... PIC16(L)F1825/1829 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 FCMEN bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor is enabled 0 Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit ...

Page 51

... Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase The entire program memory will be erased when the code protection is turned off. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 DS41440C-page 51 ...

Page 52

... PIC16(L)F1825/1829 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 (1) LVP bit 13 U-1 U-1 U-1 bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set Legend: bit 13 LVP: Low-Voltage Programming Enable bit 1 Low-voltage programming enabled 0 High-voltage on MCLR must be used for programming ...

Page 53

... See Section 11.5 User ID, Device ID and Configuration for more information on accessing these Word Access memory locations. For more information on checksum calculation, see the PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification (DS41390). 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Write such as DS41440C-page 53 ...

Page 54

... PIC16(L)F1825/1829 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 User ID, Device ID and Configuration for more information on accessing Word Access ...

Page 55

... XT, HS modes) and switch automatically to the internal oscillator. Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low-Power mode (0 MHz to 0 ...

Page 56

... PIC16(L)F1825/1829 FIGURE 5-1: SIMPLIFIED PIC External Oscillator OSC2 Sleep OSC1 Timer1 Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI Internal Oscillator Block HFPLL 16 MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) DS41440C-page 56 ® MCU CLOCK SOURCE BLOCK DIAGRAM LP, XT, HS, RC PLL FOSC< ...

Page 57

... High power, 4-32 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low power, 0-0.5 MHz (FOSC 101) 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

Page 58

... PIC16(L)F1825/1829 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the Oscillator mode F selected (typically between 2 M M. ...

Page 59

... MCU T1OSI C1 32.768 kHz Quartz Crystal T1OSO C2 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Note 1: Quartz according manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. Section 30.0 2: Always verify oscillator performance over the V expected for the application. ...

Page 60

... PIC16(L)F1825/1829 FIGURE 5-6: EXTERNAL RC MODES V DD ® PIC MCU R EXT OSC1/CLKIN C EXT V SS OSC2/CLKOUT ( I/O OSC Recommended values: 10 k R 100 k, <3V EXT 3 k R 100 k, 3-5V EXT C > 20 pF, 2-5V EXT Output depends upon CLKOUTEN bit of the Note 1: Configuration Word 1 ...

Page 61

... OSCCON register to 1x The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 5.2.2.3 The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by (Register 5-3) ...

Page 62

... PIC16(L)F1825/1829 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The outputs of the 16 MHz HFINTOSC postscaler and the LFINTOSC connect to multiplexer (see The Internal Oscillator Frequency IRCF< ...

Page 63

... If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 30.0 Specifications 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Electrical DS41440C-page 63 ...

Page 64

... PIC16(L)F1825/1829 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC 0 IRCF <3:0> System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time ...

Page 65

... Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the Timer1 Oscillator. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 5.3.3 TIMER1 OSCILLATOR The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral optimized for timekeeping operations with a 32 ...

Page 66

... PIC16(L)F1825/1829 5.4 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device ...

Page 67

... OSC2 Program Counter System Clock 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator ...

Page 68

... PIC16(L)F1825/1829 5.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1 ...

Page 69

... Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Oscillator Failure Test Test Failure Detected Test ...

Page 70

... PIC16(L)F1825/1829 5.6 Oscillator Control Registers REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 SPLLEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Word SPLLEN bit is ignored. 4xPLL is always enabled (subject to oscillator requirements) ...

Page 71

... LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 LFINTOSC is ready 0 LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 HFINTOSC is at least 0.5% accurate 0 HFINTOSC is not 0.5% accurate 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 72

... PIC16(L)F1825/1829 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 Maximum frequency 011110 • ...

Page 73

... The users firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 6.3 Conflicts with the CLKR Pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...

Page 74

... PIC16(L)F1825/1829 6.5 Reference Clock Control Register REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 Reference Clock module is enabled ...

Page 75

... Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE Unimplemented locations read as 0. Shaded cells are not used by reference clock sources. Legend: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC<1:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE< ...

Page 76

... PIC16(L)F1825/1829 NOTES: DS41440C-page 76 2010-2012 Microchip Technology Inc. ...

Page 77

... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 PWRT Zero 64 ms LFINTOSC PWRTEN Device Reset DS41440C-page 77 ...

Page 78

... PIC16(L)F1825/1829 7.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

Page 79

... If BOREN <1:0> in Configuration Word BOR Enabled 0 BOR Disabled bit 6-1 Unimplemented: Read as 0 bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 The Brown-out Reset circuit is active 0 The Brown-out Reset circuit is inactive 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 (1) T PWRT < T PWRT PWRT (1) T (1) T ...

Page 80

... PIC16(L)F1825/1829 7.3 MCLR The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table 7-2). TABLE 7-2: MCLR CONFIGURATION MCLRE LVP 7.3.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset ...

Page 81

... FIGURE 7-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 T PWRT T MCLR T OST DS41440C-page 81 ...

Page 82

... PIC16(L)F1825/1829 7.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset conditions of these registers. TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR ...

Page 83

... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 7-2. U-0 R/W/HC-1/q R/W/HC-1/q RMCLR ...

Page 84

... PIC16(L)F1825/1829 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN PCON STKOVF STKUNF STATUS WDTCON Legend: Unimplemented bit, reads as 0. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. ...

Page 85

... IOCBNx RBx IOCBPx Q4Q1 Q4Q1 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Q4Q1 edge detect data bus write IOCBFx CK from all other IOCBFx individual pin detectors Q4Q1 to data bus ...

Page 86

... PIC16(L)F1825/1829 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: GIE bit of the INTCON register Interrupt Enable bit(s) for the specific interrupt event(s) PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the ...

Page 87

... Execute 2 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Interrupt Sampled during Q1 PC1 0004h Inst(PC) NOP NOP PC1/FSR New PC/ 0004h ADDR PC1 Inst(PC) NOP NOP FSR ADDR ...

Page 88

... PIC16(L)F1825/1829 FIGURE 8-3: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) INTF (5) GIE INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. ...

Page 89

... ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the users application, other registers may also need to be saved. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 DS41440C-page 89 ...

Page 90

... PIC16(L)F1825/1829 8.6 Interrupt Control Registers 8.6.1 INTCON REGISTER The INTCON register is a readable and writable register, that contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 GIE PEIE ...

Page 91

... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...

Page 92

... PIC16(L)F1825/1829 8.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 8-3. REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 (1) OSFIE C2IE C1IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 93

... TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 Enables the TMR4 to PR4 match interrupt 0 Disables the TMR4 to PR4 match interrupt bit 0 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 ...

Page 94

... PIC16(L)F1825/1829 (1) 8.6.5 PIE4 REGISTER The PIE4 register contains the interrupt enable bits, as shown in Register 8-5. REGISTER 8-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Unimplemented: Read as ‘ ...

Page 95

... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. ...

Page 96

... PIC16(L)F1825/1829 8.6.7 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 8-7. REGISTER 8-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 (1) OSFIF C2IF C1IF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 97

... Interrupt is pending 0 Interrupt is not pending bit 0 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...

Page 98

... PIC16(L)F1825/1829 (1) 8.6.9 PIR4 REGISTER The PIR4 register contains the interrupt flag bits, as shown in Register 8-9. REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as ‘ ...

Page 99

... Converter (DAC) Module and Section 14.0 Fixed Voltage Reference (FVR) for more information on these modules. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 100

... PIC16(L)F1825/1829 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. ...

Page 101

... Configurable time-out period is from 256 seconds (typical) Multiple Reset conditions Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> WDT Time-out DS41440C-page 101 ...

Page 102

... PIC16(L)F1825/1829 10.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 25.0 Electrical Specifications LFINTOSC tolerances. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE< ...

Page 103

... If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as 0 -m/n Value at POR and BOR/Value at all other Resets (1) ...

Page 104

... PIC16(L)F1825/1829 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 OSCCON SPLLEN STATUS WDTCON — unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by Watchdog Timer. Legend: TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER ...

Page 105

... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

Page 106

... PIC16(L)F1825/1829 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not ...

Page 107

... Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 EEADRH,EEADRL PC3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here INSTR ( ...

Page 108

... See Table 11-1 for details. TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Erase Block Device (Row) Size/ Write Latches/ Boundary PIC16(L)F1825 32 words, PIC16(L)F1829 EEADRL<4:0> EEADRL<4:0> 00000 DS41440C-page 108 11.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: programming 1 ...

Page 109

... Initiate read NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 (Figure 11-1) (Figure 11-1) DS41440C-page 109 ...

Page 110

... PIC16(L)F1825/1829 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. Load the EEADRH:EEADRL register pair with the address of new row to be erased. 2. Clear the CFGS bit of the EECON1 register. 3. Set the EEPGD, FREE, and WREN bits of the EECON1 register ...

Page 111

... EEADRL<4:0> 00000 EEADRL<4:0> 00001 Buffer Register 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 continue to run. The processor does not stall when LWLO 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...

Page 112

... PIC16(L)F1825/1829 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF INTCON,GIE BANKSEL EEADRL MOVF ADDRL,W MOVWF ...

Page 113

... MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...

Page 114

... PIC16(L)F1825/1829 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. Load the starting address of the row to be modified ...

Page 115

... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 DS41440C-page 115 ...

Page 116

... PIC16(L)F1825/1829 11.7 EEPROM and Flash Control Registers REGISTER 11-1: EEDATL: EEPROM LOW BYTE DATA REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory ...

Page 117

... RD: Read Control bit 1 Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W/HC-0/0 R/W-x/q R/W-0/0 FREE ...

Page 118

... PIC16(L)F1825/1829 REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 bit 7 Legend Readable bit W Writable bit S Bit can only be set x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register ...

Page 119

... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 FIGURE 12-1: D Write LATx Write PORTx Data Register ...

Page 120

... PIC16(L)F1825/1829 12.1 Alternate Pin Function The Alternate Pin Function Control 0 (APFCON0) and Alternate Pin Function Control 1 (APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and APFCON1 registers are shown in Register 12-1 Register 12-2. For this device family, the following functions can be moved between different pins. • ...

Page 121

... T1GSEL: Pin Selection bit 0 T1G function is on RA4 1 T1G function is on RA3 bit 2 TXCKSEL: Pin Selection bit For 14 Pin Devices (PIC16(L)F1825 TX/CK function is on RC4 1 TX/CK function is on RA0 For 20 Pin Devices (PIC16(L)F1829 TX/CK function is on RB7 1 TX/CK function is on RC4 bit 1-0 Unimplemented: Read as ‘ ...

Page 122

... PIC16(L)F1825/1829 REGISTER 12-2: APFCON1: ALTERNATE PIN FUNCTION CONTROL REGISTER 1 U-0 U-0 R/W-0/0 SDO2SEL bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5 SDO2SEL: Pin Selection bit 0 SDO2 function is on RC1 ...

Page 123

... Microchip Technology Inc. PIC16(L)F1825/1829 12.2.1 ANSELA REGISTER The ANSELA register configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘ ...

Page 124

... PIC16(L)F1825/1829 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists ...

Page 125

... TRISA3: RA3 Port Tri-State Control bit This bit is always 1 as RA3 is an input only bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 PORTA pin configured as an input (tri-stated PORTA pin configured as an output 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-x/x R-x/x R/W-x/x RA4 RA3 RA2 U Unimplemented bit, read as ‘ ...

Page 126

... PIC16(L)F1825/1829 REGISTER 12-5: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u LATA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits bit 3 Unimplemented: Read as ‘ ...

Page 127

... Unimplemented: Read as 0 bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits For RA<5:0> pins, respectively input used for port reads and interrupt-on-change 0 TTL input used for port reads and interrupt-on-change 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-1/1 R/W-1/1 R/W-1/1 WPUA4 WPUA3 WPUA2 U Unimplemented bit, read as ‘ ...

Page 128

... TRISA WPUA — unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by PORTA. Legend: PIC16(L)F1829 only. Note 1: PIC16(L)F1825 only. 2: TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA Name Bits Bit -/7 Bit -/6 13:8 CONFIG1 ...

Page 129

... Microchip Technology Inc. PIC16(L)F1825/1829 12.3.1 ANSELB REGISTER The ANSELB register configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all ...

Page 130

... PIC16(L)F1825/1829 12.3.2 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists ...

Page 131

... LATB<7:4>: PORTB Output Latch Value bits bit 3-0 Unimplemented: Read as 0 Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is Note 1: return of actual I/O pin values. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-x/u U-0 U-0 RB4 — Unimplemented bit, read as 0 ...

Page 132

... PIC16(L)F1825/1829 REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 ANSB7 ANSB6 ANSB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 ANSB<7:4>: Analog Select between Analog or Digital Function on pins RB<7:4>, respectively 0 Digital I/O. Pin is assigned to port or digital special function. ...

Page 133

... TRISB7 TRISB6 WPUB WPUB7 WPUB6 Legend unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTB. PIC16(L)F1829 only. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 INLVLB5 INLVLB4 ...

Page 134

... PORTC register and also the level at which an Interrupt-on-Change occurs, if that feature is enabled. See Section 30.4 DC Character- for more information istics: PIC16(L)F1825/1829-I/E on threshold levels. Changing the input threshold selection Note: should be performed while all peripheral modules are disabled ...

Page 135

... Certain digital input functions override other port functions and are included in the priority list. TABLE 12-7: PORTC OUTPUT PRIORITY Pin Name Function Priority RC0 SCL (PIC16(L)F1825 only) SCK (PIC16(L)F1825 only) (2) P1D RC1 SDA1 (PIC16(L)F1825 only) SDA1 (PIC16(L)F1825 only) ...

Page 136

... PIC16(L)F1825/1829 REGISTER 12-15: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u (1) (1) RC7 RC6 RC5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits 1 Port pin is > Port pin is < RC< ...

Page 137

... Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is in configured as an output WPUC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 U-0 R/W-1/1 R/W-1/1 ANSC3 ANSC2 U Unimplemented bit, read as ‘ ...

Page 138

... TTL input used for port reads and interrupt-on-change INLVLC<7:6> available on PIC16(L)F1829 only. Otherwise, they are unimplemented and read as 0. Note 1: 2: PIC16(L)F1829 only, reset default value. PIC16(L)F1825 only, reset default value. 3: TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name ...

Page 139

... A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 13.3 Interrupt Flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port ...

Page 140

... PIC16(L)F1825/1829 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx RAx IOCAPx Q4Q1 Q4Q1 13.6 Interrupt-on-Change Registers REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 IOCAP5 bit 7 Legend Readable bit W Writable bit ...

Page 141

... Interrupt-on-change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge Interrupt-on-change disabled for the associated pin. bit 3-0 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-0/0 R/W-0/0 R/W-0/0 IOCAN4 IOCAN3 IOCAN2 U Unimplemented bit, read as ‘ ...

Page 142

... PIC16(L)F1825/1829 REGISTER 13-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER (PIC16(L)F1829 ONLY) R/W-0/0 R/W-0/0 R/W-0/0 IOCBN7 IOCBN6 IOCBN5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 IOCAN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 Interrupt-on-change enabled on the pin for a negative going edge ...

Page 143

... TRISA (1) TRISB7 TRISB6 TRISB Legend: Unimplemented location, read as 0. Shaded cells are not used by interrupt-on-change. PIC16(L)F1829 only. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 ANSB5 ANSB4 — ...

Page 144

... PIC16(L)F1825/1829 NOTES: DS41440C-page 144 2010-2012 Microchip Technology Inc. ...

Page 145

... FVREN Any peripheral requiring the Fixed Reference (See Table 14-1) 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, DAC and CPS are routed through two independent programmable gain amplifiers. Each , with 1.024V, ...

Page 146

... PIC16(L)F1825/1829 14.3 FVR Control Registers REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 0 Fixed Voltage Reference is disabled ...

Page 147

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 FIGURE 15-1: 15.2 Minimum Operating V Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications ...

Page 148

... PIC16(L)F1825/1829 NOTES: DS41440C-page 148 2010-2012 Microchip Technology Inc. ...

Page 149

... FVR Buffer1 CHS<4:0> When ADON 0, all multiplexer inputs are disconnected. Note 1: PIC16(L)F1829 only. 2: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADNREF 1 ...

Page 150

... Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. 16.1.2 CHANNEL SELECTION There are channel selections available: AN<7:0> pins (PIC16(L)F1825 only) AN<11:0> pins (PIC16(L)F1829 only) Temperature Indicator DAC_output FVR Buffer1 Refer to Section 17.0 “ ...

Page 151

... Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) ...

Page 152

... PIC16(L)F1825/1829 16.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...

Page 153

... Timer1 counter resets to zero. TABLE 16-2: SPECIAL EVENT TRIGGER Device CCPx/ECCPx PIC16(L)F1825/1829 CCP4 Using the Special Event Trigger does not assure proper ADC timing the users responsibility to ensure that the ADC timing requirements are met. Refer to Section 24.0 “ ...

Page 154

... PIC16(L)F1825/1829 16.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: Disable pin output driver (Refer to the TRIS register) Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: Select ADC conversion clock • ...

Page 155

... Section 17.0 Digital-to-Analog Converter (DAC) Module See 3: Section 14.0 Fixed Voltage Reference (FVR) See 4: Section 15.0 Temperature Indicator Module 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (4) (3) for more information ...

Page 156

... PIC16(L)F1825/1829 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 Right justified. Six Most Significant bits of ADRESH are set to 0 when the conversion result is loaded Left justified. Six Least Significant bits of ADRESL are set to ‘ ...

Page 157

... Bit is set 0 Bit is cleared bit 7-6 ADRES<1:0> : ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved : Do not use. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-x/u ...

Page 158

... PIC16(L)F1825/1829 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 1 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Reserved : Do not use. bit 1-0 ADRES<9:8> : ADC Result Register bits ...

Page 159

... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources . This is required to meet the pin leakage specification. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 160

... PIC16(L)F1825/1829 FIGURE 16-4: ANALOG INPUT MODEL Analog Input pin Rs C PIN Legend Sample/Hold Capacitance HOLD C Input Capacitance PIN I Leakage current at the pin due to LEAKAGE various junctions R Interconnect Resistance Resistance of Sampling Switch Sampling Switch V Threshold Voltage T Note 1: Refer to Section 30.0 Electrical ...

Page 161

... Shaded cells are not used for ADC Legend: module. PIC16(L)F1829 only. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ADCS<2:0> ADNREF ...

Page 162

... PIC16(L)F1825/1829 NOTES: DS41440C-page 162 2010-2012 Microchip Technology Inc. ...

Page 163

... Section 30.0 . Specifications 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: ...

Page 164

... PIC16(L)F1825/1829 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACLPS DACNSS V - REF V SS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41440C-page 164 Digital-to-Analog Converter (DAC) V SOURCE ...

Page 165

... DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 This is also the method used to output the voltage level from the FVR to an output pin. See Operation During Sleep ...

Page 166

... PIC16(L)F1825/1829 17.7 DAC Control Registers REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 DACEN DACLPS DACOE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled ...

Page 167

... FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 Unimplemented, read as 0. Shaded cells are unused by the DAC module. Legend: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> DACOE DACPSS<1:0> DACR<4:0> ...

Page 168

... PIC16(L)F1825/1829 NOTES: DS41440C-page 168 2010-2012 Microchip Technology Inc. ...

Page 169

... The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to Set or Reset the SR latch, respectively. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time ...

Page 170

... PIC16(L)F1825/1829 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse (2) Gen SRI SRSPE SRCLK SRSCKE (3, 4) sync_C2OUT (4) SRSC2E (3) sync_C1OUT SRSC1E SRPR Pulse (2) Gen SRI SRRPE SRCLK SRRCKE (3, 4) sync_C2OUT (4) SRRC2E (3) sync_C1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. ...

Page 171

... No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 Pulse Reset input for 1 Q-clock period effect on Reset input. Note 1: Set only, always reads back 0. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 MHz MHz OSC OSC 39.0 kHz 31 ...

Page 172

... PIC16(L)F1825/1829 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit latch is set when the SRI pin is high ...

Page 173

... TRISC TRISC7 TRISC6 Unimplemented, read as 0. Shaded cells are unused by the SR latch module. Legend: PIC16(L)F1829 only. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 INLVLA5 INLVLA4 INLVLA3 ...

Page 174

... PIC16(L)F1825/1829 NOTES: DS41440C-page 174 2010-2012 Microchip Technology Inc. ...

Page 175

... Note 1: When CxON 0, all multiplexer inputs are disconnected. 2: Output of comparator can be frozen during debugging. 3: 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 comparator is a digital low level. When the analog voltage the output of the comparator is a digital high level. IN FIGURE 19-1: ...

Page 176

... PIC16(L)F1825/1829 19.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register Control and Status bits for the following: Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization ...

Page 177

... CxPOL bit of the CMxCON0 register switching the comparator on or off with the CxON bit of the CMxCON0 register. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 19.6 Comparator Positive Input Selection Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • ...

Page 178

... PIC16(L)F1825/1829 19.9 Interaction with ECCP Logic In some devices, a comparator output signal can be used to trigger the auto-shutdown feature found within the ECCP module. When the ECCP auto-shutdown feature is enabled and a comparator output signal is selected as the source, the comparator can be used simultaneously as a general purpose comparator and as the ECCP auto-shutdown source ...

Page 179

... CxSYNC: Comparator Output Synchronous Mode bit 1 Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP ...

Page 180

... PIC16(L)F1825/1829 REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit ...

Page 181

... TRISC TRISC7 TRISC6 Legend: Unimplemented location, read as 0. Shaded cells are unused by the comparator module. Note 1: PIC16(L)F1829 only. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 C1OE C1POL C1SP C1PCH1 C1PCH0 ...

Page 182

... PIC16(L)F1825/1829 NOTES: DS41440C-page 182 2010-2012 Microchip Technology Inc. ...

Page 183

... From CPSCLK 1 TMR0SE TMR0CS T0XCS 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...

Page 184

... PIC16(L)F1825/1829 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256 ...

Page 185

... Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module. Legend: Page provides register information. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 186

... PIC16(L)F1825/1829 NOTES: DS41440C-page 186 2010-2012 Microchip Technology Inc. ...

Page 187

... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...

Page 188

... PIC16(L)F1825/1829 21.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module ...

Page 189

... When switching from asynchronous to synchronous operation possible to produce an additional increment. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 21.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...

Page 190

... PIC16(L)F1825/1829 21.6.2 TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register ...

Page 191

... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 21.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

Page 192

... PIC16(L)F1825/1829 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41440C-page 192 2010-2012 Microchip Technology Inc. ...

Page 193

... T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Cleared by software DS41440C-page 193 ...

Page 194

... PIC16(L)F1825/1829 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41440C-page 194 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL  ...

Page 195

... This bit is ignored. bit 1 Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 Clears Timer1 gate flip-flop 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ) ...

Page 196

... PIC16(L)F1825/1829 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 21-2, is used to control Timer1 Gate. REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set ‘ ...

Page 197

... TRISA T1CON TMR1CS<1:0> T1GCON TMR1GE T1GPOL Unimplemented location, read as 0. Shaded cells are not used by the Timer1 module. Legend: Page provides register information. 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 DC1B<1:0> ...

Page 198

... PIC16(L)F1825/1829 NOTES: DS41440C-page 198 2010-2012 Microchip Technology Inc. ...

Page 199

... Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 22-1 for a block diagram of Timer2/4/6. FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> 2010-2012 Microchip Technology Inc. PIC16(L)F1825/1829 T6CON. PRx TMRx Output Reset TMRx Postscaler Comparator 1 PRx TxOUTPS<3:0> Sets Flag ...

Page 200

... PIC16(L)F1825/1829 22.1 Timer2/4/6 Operation The clock input to the Timer2/4/6 modules is the system instruction clock (F /4). OSC TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS< ...

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