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PIC16(L)F1823 Datasheet

Download or read online Microchip Technology PIC16(L)F1823 8/14-Pin Flash Microcontrollers With XLP Technology pdf datasheet.



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PIC12(L)F1822/PIC16(L)F1823
Data Sheet
8/14-Pin Flash Microcontrollers
with XLP Technology
 2010-2012 Microchip Technology Inc.
DS41413C

Summary of Contents

Page 1

... PIC12(L)F1822/PIC16(L)F1823 2010-2012 Microchip Technology Inc. 8/14-Pin Flash Microcontrollers with XLP Technology Data Sheet DS41413C ...

Page 2

... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010-2012, Microchip Technology Incorporated, Printed in the U ...

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... Programmable Code Protection Self-Programmable under Software Control 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Extreme Low-Power Management PIC12LF1822/PIC16LF1823 with XLP: Sleep mode 1.8V, typical Watchdog Timer: 300 nA @ 1.8V, typical Timer1 Oscillator: 650 kHz, typical • ...

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... I - Debugging, Integrated on Chip Debugging, available using Debug Header. One pin is input-only. 2: Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41413 PIC12(L)F1822/PIC16(L)F1823 Data Sheet, 8/14-Pin Flash Microcontrollers. DS41441 PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers DS41419 PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers. ...

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... C1IN1- RA5 2 — — SS Note 1: Pin function is selectable via the APFCON register. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 RA0/ICSPDAT RA5 7 2 RA4 6 3 RA1/ICSPCLK 4 /RA3 5 PP RA2 ...

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... PIC12(L)F1822/PIC16(L)F1823 FIGURE 2: 14-PIN DIAGRAM FOR PIC16(L)F1823 PDIP, SOIC, TSSOP MCLR/V FIGURE 3: 16-PIN DIAGRAM FOR PIC16(L)F1823 QFN MCLR/V DS41413C-page RA0/ICSPDAT RA5 13 2 RA4 RA1/ICSPCLK 12 3 /RA3 PP RA2 4 11 RC5 RC0 5 10 RC4 6 9 RC1 RC2 ...

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... TABLE 3: 14-PIN ALLOCATION TABLE (PIC16(L)F1823) RA0 13 12 AN0 DACOUT CPS0 RA1 12 11 AN1 V CPS1 REF RA2 11 10 AN2 CPS2 RA3 4 3 RA4 3 2 AN3 CPS3 RA5 2 1 RC0 10 9 AN4 CPS4 ...

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... PIC12(L)F1822/PIC16(L)F1823 Table of Contents 1.0 Device Overview ... 11 2.0 Enhanced Mid-Range CPU ... 19 3.0 Memory Organization ... 21 4.0 Device Configuration ... 49 5.0 Oscillator Module (With Fail-Safe Clock Monitor)... 55 6.0 Reference Clock Module ... 73 7.0 Resets ... 77 8.0 Interrupts ... 87 9.0 Power-Down Mode (Sleep) ... 99 10.0 Watchdog Timer (WDT) ... 103 11.0 Data EEPROM and Flash Program Memory Control ... 107 12.0 I/O Ports ... 121 13 ...

Page 9

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 to receive the most current information on all of our products. DS41413C-page 9 ...

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... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 10 2010-2012 Microchip Technology Inc. ...

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... Data EEPROM Digital-to-Analog Converter (DAC) Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) SR Latch Capture/Compare/PWM Modules ECCP1 Comparators C1 C2 Master Synchronous Serial Ports MSSP Timers Timer0 Timer1 Timer2 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 of the 1-2 and 1-3 DS41413C-page 11 ...

Page 12

... OSC1/CLKIN INTRC Oscillator MCLR SR Timer0 Latch ECCP1 MSSP Note 1: See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. 2: PIC16(L)F1823 only. 3: DS41413C-page 12 Program Flash Memory RAM CPU (Figure 2-1) ADC Timer1 DAC Comparators 10-Bit Modulator FVR EUSART CapSense  ...

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... Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input High Voltage XTAL Crystal Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Input Output Type Type TTL CMOS General purpose I/O. AN — ...

Page 14

... PIC12(L)F1822/PIC16(L)F1823 TABLE 1-2: PIC12(L)F1822 PINOUT DESCRIPTION (CONTINUED) Name Function RA4/AN3/CPS3/OSC2/ RA4 CLKOUT/T1OSO/C1IN1-/CLKR/ AN3 (1) (1) (1) (1) SDO /CK /TX /P1B / CPS3 (1) T1G /MDCIN2 OSC2 CLKOUT T1OSO C1IN1- CLKR SDO CK TX P1B T1G MDCIN2 RA5/CLKIN/OSC1/T1OSI/ RA5 (1) (1) T1CKI/SRNQ/P1A /CCP1 / CLKIN (1) (1) ...

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... TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION Name Function RA0/AN0/CPS0/C1IN/ RA0 (1) (1) DACOUT/TX /CK /ICSPDAT/ AN0 ICDDAT CPS0 C1IN DACOUT TX CK ICSPDAT RA1/AN1/CPS1/C12IN0-/V / RA1 REF (1) (1) SRI/RX /DT /ICSPCLK/ AN1 ICDCLK CPS1 C12IN0- V REF SRI RX DT ICSPCLK RA2/AN2/CPS2/T0CKI/INT/ RA2 C1OUT/SRQ/FLT0 AN2 CPS2 T0CKI INT C1OUT ...

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... PIC12(L)F1822/PIC16(L)F1823 TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION (CONTINUED) Name Function RA5/CLKIN/OSC1/T1OSI/T1CKI RA5 CLKIN OSC1 T1OSI T1CKI RC0/AN4/CPS4/C2IN/SCL/ RC0 SCK AN4 CPS4 C2IN SCL SCK RC1/AN5/CPS5/C12IN1-/SDA/ RC1 SDI AN5 CPS5 C12IN1- SDA SDI RC2/AN6/CPS6/C12IN2-/P1D/ RC2 (1) SDO /MDCIN1 AN6 ...

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... TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION (CONTINUED) Name Function Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input High Voltage XTAL Crystal Pin functions can be assigned to one of two pin locations via software. See APFCON register Note 1:  ...

Page 18

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 18 2010-2012 Microchip Technology Inc. ...

Page 19

... Section 3.5 Indirect Addressing 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 Instruction Set Summary details. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Saving, for more for more DS41413C-page 19 ...

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... PIC12(L)F1822/PIC16(L)F1823 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control OSC1/CLKIN Timing ...

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... TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC12(L)F1822 PIC16(L)F1823 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 The following features are associated with access and control of program memory and data memory: PCL and PCLATH Stack Indirect Addressing 3 ...

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... PIC12(L)F1822/PIC16(L)F1823 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1822/16(L)F1823 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector On-chip Program Page 0 Memory Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Wraps to Page 0 ...

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... File Select Registers (FSR). See Section 3.5 Addressing for more information. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the PIC12(L)F1822/16(L)F1823. These registers are listed below: • ...

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... PIC12(L)F1822/PIC16(L)F1823 3.2.1.1 STATUS Register The STATUS register, shown in Register the arithmetic status of the ALU the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...

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... Common RAM (16 bytes) 7Fh 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC12(L)F1822 PIC16(L)F1823 Section 3.5.2 MEMORY MAP TABLES Banks Table No. 0-7 Table 3-3 8-15 Table 3-4 16-23 Table 3-5 24-31 Table 3-6 31 ...

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... TABLE 3-3: PIC12(L)F1822/PIC16(L)F1823 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H 105h 006h FSR1L ...

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TABLE 3-4: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...

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TABLE 3-5: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...

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TABLE 3-6: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...

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... Unimplemented data memory locations, read as 0. DS41413C-page 30 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device Bank( PIC12(L)F1822 PIC16(L)F1823 9-30 31 2010-2012 Microchip Technology Inc. Page No ...

Page 31

... Legend: Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 ...

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... ADFM 09Fh Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. DS41413C-page 32 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

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... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 ...

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... BAUDCON ABDOVF RCIDL Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. DS41413C-page 34 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

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... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 ...

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... Unimplemented 29Fh Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. DS41413C-page 36 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

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... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 ...

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... MDCARH MDCHODIS MDCHPOL MDCHSYNC Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. DS41413C-page 38 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 39

... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 ...

Page 40

... Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. DS41413C-page 40 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

Page 41

... TOSH x unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as 1. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 ...

Page 42

... PIC12(L)F1822/PIC16(L)F1823 3.3 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. ...

Page 43

... FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

Page 44

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL DS41413C-page 44 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the ...

Page 45

... These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 0x0F Return Address 0x0E Return Address 0x0D Return Address ...

Page 46

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 3-8: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41413C-page 46 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 ...

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... TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Indirect Addressing 7 FSRxH Bank Select 11111 Bank FSRxL ...

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... PIC12(L)F1822/PIC16(L)F1823 3.5.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the ...

Page 49

... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 register at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 by device DS41413C-page 49 ...

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... PIC12(L)F1822/PIC16(L)F1823 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 FCMEN bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor is enabled 0 Fail-Safe Clock Monitor is disabled bit 12 ...

Page 51

... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 DS41413C-page 51 ...

Page 52

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 LVP bit 13 U-1 U-1 bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 LVP: Low-Voltage Programming Enable bit 1 Low-voltage programming enabled 0 High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit ...

Page 53

... See Section 11.5 User ID, Device ID and Configuration Word Access for more information on accessing these memory locations. For more information on checksum calculation, see the PIC16F/LF1826/27/PIC12F/LF1822 Memory Programming Specification (DS41390). 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Write such as DS41413C-page 53 ...

Page 54

... PIC12(L)F1822/PIC16(L)F1823 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 User ID, Device ID and Configuration Word Access for more information on accessing these memory locations ...

Page 55

... XT, HS modes) and switch automatically to the internal oscillator. Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low Power mode (0 MHz to 0 ...

Page 56

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 5-1: SIMPLIFIED PIC External Oscillator OSC2 Sleep OSC1 Timer1 Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI Internal Oscillator Block HFPLL 16 MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) DS41413C-page 56 ® MCU CLOCK SOURCE BLOCK DIAGRAM ...

Page 57

... High-power, 4-32 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low-power, 0-0.5 MHz (FOSC 101) 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

Page 58

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the Oscillator mode F selected (typically between 2 M ...

Page 59

... Crystal to a PIC16F690/SS (DS91097) AN1288, Design Practices for Low-Power External Oscillators (DS01288) 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...

Page 60

... PIC12(L)F1822/PIC16(L)F1823 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscil- lator block as the system clock by performing one of the following actions: Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • ...

Page 61

... Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...

Page 62

... PIC12(L)F1822/PIC16(L)F1823 5.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4X PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz inter- nal clock source: • ...

Page 63

... System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 ...

Page 64

... PIC12(L)F1822/PIC16(L)F1823 5.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: Default system oscillator determined by FOSC bits in Configuration Word 1 • ...

Page 65

... Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...

Page 66

... PIC12(L)F1822/PIC16(L)F1823 5.4.2 TWO-SPEED START-UP SEQUENCE 1. Wake-up from Power-on Reset or Sleep. 2. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. ...

Page 67

... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...

Page 68

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS41413C-page 68 Oscillator ...

Page 69

... SCS<1:0>: System Clock Select bits 1x Internal oscillator block 01 Timer1 oscillator 00 Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) Section 5.2.2.1 “ ...

Page 70

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q T1OSCR PLLR OSTS bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN Timer1 oscillator is ready 0 Timer1 oscillator is not ready ...

Page 71

... C2IE PIE2 OSFIE (1) OSFIF C2IF PIR2 T1CON TMR1CS<1:0> Legend: unimplemented location, read as 0. Shaded cells are not used by clock sources. Note 1: PIC16(L)F1823 only. TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Name Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE — ...

Page 72

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 72 2010-2012 Microchip Technology Inc. ...

Page 73

... The users firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 6.3 Conflicts with the CLKR pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...

Page 74

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 Reference clock module is enabled ...

Page 75

... Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented locations read as 0. Shaded cells are not used by reference clock sources. Legend: 2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO ...

Page 76

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 76 2012 Microchip Technology Inc. ...

Page 77

... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 PWRT Zero 64 ms LFINTOSC PWRTEN Device Reset DS41413C-page 77 ...

Page 78

... PIC12(L)F1822/PIC16(L)F1823 7.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

Page 79

... V DD Internal Reset V DD Internal Reset V DD Internal Reset Note 1: T delay only if PWRTE bit is programmed to 0. PWRT 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 level. T BORRDY BOR Protection Active PWRT (1) T < T PWRT (1) T PWRT (1) T PWRT V BOR ...

Page 80

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 SBOREN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 1 01: SBOREN is read/write, but has no effect on the BOR. If BOREN < ...

Page 81

... Programming Mode Exit Upon exit of Programming mode, the device will behave POR had just occurred. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 7.8 Power-Up Timer The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to ...

Page 82

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC DS41413C-page 82 T PWRT T MCLR T OST 2010-2012 Microchip Technology Inc. ...

Page 83

... Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution Status bit is not implemented, that bit will be read as 0. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 POR BOR TO ...

Page 84

... PIC12(L)F1822/PIC16(L)F1823 7.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR) ...

Page 85

... WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN Legend: unimplemented bit, reads as 0. Shaded cells are not used by Resets. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 Bit 3 Bit 2 — ...

Page 86

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 86 2010-2012 Microchip Technology Inc. ...

Page 87

... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Interrupt to CPU DS41413C-page 87 ...

Page 88

... PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE EEIF EEIE OSFIF OSFIE C1IF C1IE (1) C2IF (1) C2IE BCLIF BCLIE PIC16(L)F1823 only. Note 1: DS41413C-page 88 To Interrupt Logic (Figure 8-1) 2010-2012 Microchip Technology Inc. ...

Page 89

... Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...

Page 90

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 8-3: INTERRUPT LATENCY OSC1 CLKOUT Interrupt GIE PC Execute 1 Cycle Instruction at PC Interrupt GIE PC Execute 2 Cycle Instruction at PC Interrupt GIE PC-1 PC FSR ADDR ...

Page 91

... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 ...

Page 92

... PIC12(L)F1822/PIC16(L)F1823 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector ...

Page 93

... The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register Note 1: have been cleared by software. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...

Page 94

... PIC12(L)F1822/PIC16(L)F1823 8.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 8-2. REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 95

... BCLIE: MSSP Bus Collision Interrupt Enable bit 1 Enables the MSSP Bus Collision Interrupt 0 Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...

Page 96

... PIC12(L)F1822/PIC16(L)F1823 8.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 8-4. REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 TMR1GIF ADIF RCIF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 97

... BCLIF: MSSP Bus Collision Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending bit 2-0 Unimplemented: Read as 0 Note 1: PIC16(L)F1823 only. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...

Page 98

... TMR1GIE ADIE (1) OSFIE C2IE PIE2 TMR1GIF ADIF PIR1 (1) OSFIF C2IF PIR2 unimplemented locations read as 0. Shaded cells are not used by Interrupts. Legend: PIC16(L)F1823 only. Note 1: DS41413C-page 98 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF TMR0CS TMR0SE PSA PS2 ...

Page 99

... Converter (DAC) Module and Section 14.0 Fixed Voltage Reference (FVR) for more information on these modules. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 100

... PIC12(L)F1822/PIC16(L)F1823 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP ...

Page 101

... OSFIF C2IF STATUS WDTCON WDTPS4 Legend: unimplemented, read as 0. Shaded cells are not used in Power-down mode. PIC16(L)F1823 only. Note 1: 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 Bit 3 Bit 2 INTE IOCIE TMR0IF ...

Page 102

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 102 2010-2012 Microchip Technology Inc. ...

Page 103

... Configurable time-out period is from 256 seconds (typical) Multiple Reset conditions Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> WDT Time-out DS41413C-page 103 ...

Page 104

... PIC12(L)F1822/PIC16(L)F1823 10.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1. 10.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Word 1 are set to ‘ ...

Page 105

... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> 1x: This bit is ignored. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as 0 -m/n Value at POR and BOR/Value at all other Resets 17 ) (Interval 4s typ) ...

Page 106

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 106 2010-2012 Microchip Technology Inc. ...

Page 107

... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

Page 108

... PIC12(L)F1822/PIC16(L)F1823 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program vari- ables or other data that are updated often). When vari- ables in one section change frequently, while variables ...

Page 109

... Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 EEADRH,EEADRL PC3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here INSTR ( ...

Page 110

... TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Erase Block Device (Row) Size/ Write Latches/ Boundary PIC12(L)F1822/ 16 words, PIC16(L)F1823 EEADRL<3:0> EEADRL<3:0> 0000 DS41413C-page 110 11.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair ...

Page 111

... Initiate read NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 (Figure 11-1) (Figure 11-1) DS41413C-page 111 ...

Page 112

... PIC12(L)F1822/PIC16(L)F1823 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. Load the EEADRH:EEADRL register pair with the address of new row to be erased. 2. Clear the CFGS bit of the EECON1 register. 3. Set the EEPGD, FREE, and WREN bits of the EECON1 register ...

Page 113

... EEADRL<3:0> 0000 EEADRL<3:0> 0001 Buffer Register 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 continue to run. The processor does not stall when LWLO 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...

Page 114

... PIC12(L)F1822/PIC16(L)F1823 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF INTCON,GIE BANKSEL EEADRL MOVF ADDRL,W ...

Page 115

... MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...

Page 116

... PIC12(L)F1822/PIC16(L)F1823 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. Load the starting address of the row to be mod- ified ...

Page 117

... BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 DS41413C-page 117 ...

Page 118

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 11-1: EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER ...

Page 119

... RD: Read Control bit 1 Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W/HC-0/0 R/W-x/q R/W-0/0 FREE ...

Page 120

... C1IE (1) PIR2 OSFIF C2IF C1IF Legend: unimplemented location, read as 0. Shaded cells are not used by Data EEPROM module. Page provides register information. PIC16(L)F1823 only. Note 1: 2: Unimplemented. Read as 1. DS41413C-page 120 W-0/0 W-0/0 W-0/0 EEPROM Control Register Unimplemented bit, read as 0 ...

Page 121

... Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 FIGURE 12-1: Write LATx Write PORTx Data Bus Read PORTx To peripherals ...

Page 122

... PIC12(L)F1822/PIC16(L)F1823 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register 12-1. For this device family, the following functions can be moved between different pins. • ...

Page 123

... P1BSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822 P1B function is on RA0 1 P1B function is on RA4 For 14-Pin Devices (PIC16(L)F1823): P1B function is always on RC4 bit 0 CCP1SEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822 CCP1/P1A function is on RA2 ...

Page 124

... PIC12(L)F1822/PIC16(L)F1823 12.2 PORTA Registers PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit ( 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit ( 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin) ...

Page 125

... RX/DT (EUSART) 5. SCK (PIC12(L)F1822 only) RA2 1. SRQ 2. C1OUT (Comparator) 3. SDA (PIC12(L)F1822 only) 4. CCP1/P1A (PIC12(L)F1822 only) 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 RA3 No output priorities. Input only pin. RA4 1. OSC2 2. CLKOUT 3. T1OSO (Timer1 Oscillator) 4. CLKR 5. TX/CK (PIC12(L)F1822 only) 6 ...

Page 126

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 12-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x RA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 RA<5:0>: PORTA I/O Value bits 1 Port pin is > Port pin is < V ...

Page 127

... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-x/u U-0 R/W-x/u LATA4 ...

Page 128

... TRISA WPUA Legend unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by PORTA. Note 1: PIC12F1822/16F1823 only. 2: PIC16(L)F1823 only. TABLE 12-3: SUMMARY OF CONFIGURATION WORD WITH PORTA Name Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 ...

Page 129

... PORTC Registers (PIC16(L)F1823 only) PORTC is a 6-bit wide, bidirectional port. The corresponding data direction register (Register 12-8). Setting a TRISC bit ( 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit ( 0) will make the corresponding PORTC pin an output (i ...

Page 130

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 12-7: PORTC: PORTC REGISTER U-0 U-0 R/W-x/u RC5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 RC<5:0>: PORTC General Purpose I/O Pin bits 1 Port pin is > Port pin is < ...

Page 131

... TRISC WPUC Legend unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTC. Note 1: PIC16(L)F1823 only. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 U-0 R/W-1/1 R/W-1/1 ANSC3 ANSC2 U Unimplemented bit, read as 0 ...

Page 132

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 132 2010-2012 Microchip Technology Inc. ...

Page 133

... IOCAPx bit and the IOCANx bit of the IOCAP and IOCAN registers, respectively. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 13.3 Interrupt Flags The IOCAFx bits located in the IOCAF register are status flags that correspond to the Interrupt-on-change pins of PORTA ...

Page 134

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx RBx IOCBPx Q4Q1 Q4Q1 DS41413C-page 134 Q4Q1 edge detect data bus write IOCBFx CK from all other IOCBFx individual pin detectors ...

Page 135

... An enabled change was detected on the associated pin. Set when IOCAPx 1 and a rising edge was detected on RAx, or when IOCANx 1 and a falling edge was detected on RAx change was detected, or the user cleared the detected change. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-0/0 R/W-0/0 R/W-0/0 IOCAP4 ...

Page 136

... PIC12(L)F1822/PIC16(L)F1823 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Name Bit 7 Bit 6 ANSELA INTCON GIE PEIE IOCAF IOCAN IOCAP TRISA Legend: unimplemented location, read as 0. Shaded cells are not used by Interrupt-on-Change. ...

Page 137

... VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each , with 1.024V, ...

Page 138

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 0 Fixed Voltage Reference is disabled ...

Page 139

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 FIGURE 15-1: 15.2 Minimum Operating V Minimum Sensing Temperature ...

Page 140

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 140 2010-2012 Microchip Technology Inc. ...

Page 141

... FVR Buffer1 CHS<4:0> Note 1: When ADON 0, all multiplexer inputs are disconnected. 2: Not available on PIC12(L)F1822. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) ...

Page 142

... CHANNEL SELECTION There are channel selections available: AN<3:0> pins (PIC12(L)F1822 only) AN<7:0> pins (PIC16(L)F1823 only) Temperature Indicator DAC Output FVR (Fixed Voltage Reference) Output Refer to Section 17.0 Digital-to-Analog Converter , (DAC) Module” ...

Page 143

... Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) ...

Page 144

... PIC12(L)F1822/PIC16(L)F1823 16.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...

Page 145

... Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...

Page 146

... PIC12(L)F1822/PIC16(L)F1823 16.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: Disable pin output driver (Refer to the TRIS register) Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: Select ADC conversion clock • ...

Page 147

... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 ADC is enabled 0 ADC is disabled and consumes no operating current PIC16(L)F1823 only. For PIC12(L)F1822 it is Reserved. No channel connected. Note 1: 2: See Section 17.0 Digital-to-Analog Converter (DAC) Module See 3: Section 14.0 “ ...

Page 148

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 Right justified. Six Most Significant bits of ADRESH are set to 0 when the conversion result is loaded Left justified. Six Least Significant bits of ADRESL are set to ‘ ...

Page 149

... Bit is cleared bit 7-6 ADRES<1:0> : ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved : Do not use. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 150

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 1 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Reserved : Do not use. bit 1-0 ADRES<9:8> : ADC Result Register bits ...

Page 151

... The maximum recommended impedance for analog sources . This is required to meet the pin leakage specification. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 152

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 16-4: ANALOG INPUT MODEL Analog Input pin Rs C PIN Legend Sample/Hold Capacitance HOLD C Input Capacitance PIN I Leakage current at the pin due to LEAKAGE various junctions R Interconnect Resistance Resistance of Sampling Switch Sampling Switch V Threshold Voltage T Note 1: Refer to Section 30.0 “ ...

Page 153

... TRISC Legend: unimplemented read as 0. Shaded cells are not used for ADC module. Page provides register information. PIC16(L)F1823 only. Note 1: 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 ...

Page 154

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 154 2010-2012 Microchip Technology Inc. ...

Page 155

... Section 30.0 . Specifications 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations:  ...

Page 156

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACLPS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41413C-page 156 Digital-to-Analog Converter (DAC) V SOURCE ...

Page 157

... DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 This is also the method used to output the voltage level from the FVR to an output pin. See Operation During Sleep ...

Page 158

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 DACEN DACLPS DACOE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit ...

Page 159

... The latch can be Set or Reset by: Software control (SRPS and SRPR bits) Comparator C1 output (SYNCC1OUT) Comparator C2 output (SYNCC2OUT) (PIC16(L)F1823 only) SRI pin Programmable clock (SRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR latch, respectively. ...

Page 160

... SYNCC2OUT (4) SRRC2E (3) SYNCC1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. PIC16(L)F1823 only. 4: DS41413C-page 160 SRLEN SRQEN S Q SRQ SR (1) Latch R Q SRNQ ...

Page 161

... SRPR: Pulse Reset Input of the SR Latch bit 1 Pulse reset input for 1 Q-clock period effect on reset input. Note 1: Set only, always reads back 0. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 MHz MHz OSC OSC 39.0 kHz 31 ...

Page 162

... SR latch is reset when the C2 Comparator output is high Comparator output has no effect on the reset input of the SR latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit latch is reset when the C1 Comparator output is high Comparator output has no effect on the reset input of the SR latch PIC16(L)F1823 only. Note 1: DS41413C-page 162 R/W-0/0 R/W-0/0 R/W-0/0 ...

Page 163

... SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA Legend: unimplemented, read as 0. Shaded cells are unused by the SR latch module. Note 1: PIC16(L)F1823 only. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 ...

Page 164

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 164 2010-2012 Microchip Technology Inc. ...

Page 165

... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 FIGURE 19- ...

Page 166

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 19-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM (PIC12(L)F1822) CxNCH<1:0> C1ON 2 C1IN0- 0 MUX (2) C1IN1- 1 C1VN - C1VP 0 C1IN C1HYS MUX 1 DAC C1SP (2) FVR Buffer2 2 3 C1ON V SS C1PCH<1:0> 2 Note 1: When C1ON 0, the Comparator will produce a 0 at the output. 2: When C1ON 0, all multiplexer inputs are disconnected. ...

Page 167

... C PCH<1:0> Note 1: When CxON 0, the Comparator will produce a 0 at the output. 2: When CxON 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 (1) Interrupt Interrupt C POL CxHYS ...

Page 168

... PIC12(L)F1822/PIC16(L)F1823 19.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 18-1) contain Control and Status bits for the following: Enable Output selection Output polarity Speed/Power selection Hysteresis enable • ...

Page 169

... Timer1 Block Diagram (Figure 21-1) information. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. When either edge detector is triggered and its associ- ...

Page 170

... PIC12(L)F1822/PIC16(L)F1823 19.7 Comparator Negative Input Selection The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. To use CxIN and CxINx- pins as analog Note: input, the appropriate bits must be set in the ANSEL register and the correspond- ing TRIS bits must also be set to disable the output drivers ...

Page 171

... Leakage Current at the pin due to various junctions LEAKAGE R Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 Electrical Specifications 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 V DD 0. (1) I LEAKAGE 0. Vss To Comparator DS41413C-page 171 ...

Page 172

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 CxON CxOUT CxOE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CxON: Comparator Enable bit 1 Comparator is enabled and consumes no active power 0 Comparator is disabled ...

Page 173

... Bit is set 0 Bit is cleared bit 7-2 Unimplemented: Read as 0 bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit PIC16(L)F1823 only. Note 1: 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as 0 ...

Page 174

... OSFIF C2IF PIR2 TRISA (1) TRISC unimplemented, read as 0. Shaded cells are unused by the comparator module. Legend: Note 1: PIC16(L)F1823 only. DS41413C-page 174 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 C1OE C1POL C1SP C1PCH1 C1PCH0 — ...

Page 175

... From CPSCLK 1 TMR0SE TMR0CS T0XCS 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...

Page 176

... PIC12(L)F1822/PIC16(L)F1823 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are eight prescaler options for the Timer0 mod- ule ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...

Page 177

... TRISA Legend: Unimplemented locations, read as 0. Shaded cells are not used by the Timer0 module. Page provides register information. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 178

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 178 2010-2012 Microchip Technology Inc. ...

Page 179

... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...

Page 180

... PIC12(L)F1822/PIC16(L)F1823 21.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. ...

Page 181

... This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...

Page 182

... PIC12(L)F1822/PIC16(L)F1823 21.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 Gate circuitry. 21.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 Gate circuitry ...

Page 183

... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 21.9 ECCP/CCP Capture/Compare Time Base The CCP1 module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

Page 184

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41413C-page 184 2010-2012 Microchip Technology Inc. ...

Page 185

... T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Cleared by software DS41413C-page 185 ...

Page 186

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41413C-page 186 Cleared by hardware on falling edge of T1GVAL ...

Page 187

... This bit is ignored. bit 1 Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 Clears Timer1 Gate flip-flop 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ) ...

Page 188

... PIC12(L)F1822/PIC16(L)F1823 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 21-2, is used to control Timer1 Gate. REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set ‘ ...

Page 189

... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend: unimplemented, read as 0. Shaded cells are not used by the Timer1 module. Page provides register information. Note 1: PIC16(L)F1823 only. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 — ...

Page 190

... PIC12(L)F1822/PIC16(L)F1823 NOTES: DS41413C-page 190 2010-2012 Microchip Technology Inc. ...

Page 191

... Optional use as the shift clock for the MSSP1 modules (Timer2 only) See Figure 22-1 for a block diagram of Timer2. FIGURE 22-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Sets Flag bit TMR2IF DS41413C-page 191 ...

Page 192

... PIC12(L)F1822/PIC16(L)F1823 22.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (F /4). OSC TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS< ...

Page 193

... Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 Prescaler Prescaler Prescaler Prescaler is 64 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 T2CKPS<1:0> ...

Page 194

... PIC12(L)F1822/PIC16(L)F1823 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Name Bit 7 Bit 6 INTCON GIE PEIE PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF PR2 Timer2 Module Period Register T2CON TMR2 Holding Register for the 8-bit TMR2 Register Legend: unimplemented location, read as 0. Shaded cells are not used for Timer2 module. ...

Page 195

... No Channel Selected 1111 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 Using this method, the DSM can generate the following types of Key Modulation schemes: Frequency-Shift Keying (FSK) Phase-Shift Keying (PSK) On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...

Page 196

... CCP1 Signal MSSP1 SDO1 Signal (SPI mode Only) Comparator C1 Signal Comparator C2 Signal (PIC16(L)F1823 only) EUSART TX Signal External Signal on MDMIN pin MDBIT bit in the MDCON register The modulator signal is selected by configuring the MDMS < ...

Page 197

... Active Carrier State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC 1, MDCLSYNC 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC 1 MDCLSYNC 0 Active Carrier CARH State 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 CARL CARL both CARH CARL CARH CARL both DS41413C-page 197 ...

Page 198

... PIC12(L)F1822/PIC16(L)F1823 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC 0, MDCLSYNC 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC 0 MDCLSYNC 1 Active Carrier CARH State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC 1, MDCLSYNC 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC 1 ...

Page 199

... The modulator source default connection to a pin can be disabled by setting the MDMSODIS bit in the MDSRC register. 2010-2012 Microchip Technology Inc. PIC12(L)F1822/PIC16(L)F1823 23.9 Modulated Output Polarity The modulated output signal provided on the MDOUT pin can also be inverted. Inverting the modulated out- put signal is enabled by setting the MDOPOL bit of the MDCON register ...

Page 200

... PIC12(L)F1822/PIC16(L)F1823 REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 MDEN MDOE MDSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 Modulator module is enabled and mixing input signals ...

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