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SST49LF008A Datasheet

Download or read online Microchip Technology SST49LF008A 8 Mbit Firmware Hub pdf datasheet.



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A Microchip Technology Company
The SST49LF008A flash memory devices are designed to be read-compatible
with the Intel® 82802 Firmware Hub (FWH) device for PC-BIOS application.
These devices provide protection for the storage and update of code and data in
addition to adding system design flexibility through five general purpose inputs.
Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH)
Interface mode for in-system programming and Parallel Programming (PP) mode
for fast factory programming of PC-BIOS applications.
Features
• Firmware Hub for Intel 8xx Chipsets
• 8 Mbit SuperFlash memory array for code/data
storage
– 1024K x8
• Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top Boot Block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance:100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 15 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
©2011 Silicon Storage Technology, Inc.
8 Mbit Firmware Hub
• Two Operational Modes
– Firmware Hub Interface (FWH) Mode for
In-System operation
– Parallel Programming (PP) Mode for fast
production programming
• Firmware Hub Hardware Interface Mode
– 5-signal communication interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Register for all blocks
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Writedetection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and
8-pin data I/O interface
– Supports fast In-System or PROM programming for
manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 40-lead TSOP (10mm x 20mm)
– Non-Pb (lead-free) packages available
• All non-Pb (lead-free) devices are RoHS compliant
www.microchip.com
SST49LF008A
Data Sheet
DS25085A
10/11

Summary of Contents

Page 1

... These devices provide protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of PC-BIOS applications ...

Page 2

... To meet high density, surface mount requirements, the SST49LF008A devices are offered in a 32-lead TSOP package. In addition, the SST49LF008A is offered in 32-lead PLCC and 40-lead TSOP pack- ages. See Figures 2, 3, and 4 for pin assignments and Table 1 for pin descriptions. ...

Page 3

... FWH4 ID[3:0] FGPI[4:0] R/C# A[10:0] DQ[7:0] OE# WE# Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc. TBL# WP# INIT# FWH Address Buffers Latches Interface Control Logic Programmer Interface Mbit Firmware Hub SST49LF008A SuperFlash X-Decoder Memory Y-Decoder I/O Buffers and Data Latches RST# DS25085A Data Sheet 1161 B1.2 10/11 ...

Page 4

... A4 (TBL#) 8 32-lead PLCC A3 (ID3) 9 Top View A2 (ID2 (ID1 (ID0) DQ0 (FWH0 Designates FWH Mode 4 8 Mbit Firmware Hub SST49LF008A 32 OE# (INIT#) WE# (FWH4 DQ7 (RES) 28 DQ6 (RES) 27 DQ5 (RES) 26 DQ4 (RES) 25 DQ3 (FWH3) 24 ...

Page 5

... Die Up NC (NC (NC (FGPI3 (FGPI2 (FGPI1 (FGPI0) A5 (WP (TBL Designates FWH Mode 5 8 Mbit Firmware Hub SST49LF008A Data Sheet (FWH4) WE# 37 (INIT#) OE# 36 (NC (RES) DQ7 34 (RES) DQ6 33 (RES) DQ5 32 (RES) DQ4 ...

Page 6

... Select For the Programming interface, this pin determines whether the address pins are pointing to the row addresses the column addresses. X These pins must be left unconnected. PWR provide power supply (3.0-3.6V) PWR X X Circuit ground (OV reference) All Unconnected pins 6 SST49LF008A Data Sheet pins must be grounded. SS T1.4 25085 DS25085A 10/11 ...

Page 7

... A Microchip Technology Company Device Memory Map WP# for Block 0 14 Figure 5: Device Memory Map for SST49LF008A ©2011 Silicon Storage Technology, Inc. Block 15 TBL# Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 (64 KByte Mbit Firmware Hub ...

Page 8

... To write data to the top Boot Block sectors, the TBL# pin must also remain stable at V entire duration of the Erase and Program operations. Product Identification The product identification mode identifies the device as the SST49LF008A and manufacturer as SST. Table 2: Product Identification Manufacturers ID ...

Page 9

... FWH4 is low and no activity is on the FWH bus. Firmware Hub Interface Cycles Addresses and data are transferred to and from the SST49LF008A by a series of fields, where each field contains 4 bits of data. SST49LF008A supports only single-byte Read and Write, and all fields are one clock cycle in length. Field sequences and contents are strictly defined for Read and Write opera- tions. Addresses in this section refer to addresses as seen from the SST49LF008A’ ...

Page 10

... YYYY is the most-significant nibble of the least-significant data byte. 1111 OUT In this clock cycle, the SST49LF008A has driven the bus to all then Float ones and then floats the bus prior to the next clock cycle. This is the first part of the bus turnaround cycle. ...

Page 11

... OUT then Float In this clock cycle, the SST49LF008A has driven the bus to all then float 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus turn- around cycle.” ...

Page 12

... The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF008A. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest flash memory address range for the SST49LF008A. WP# pin write protects the remain- ing sectors in the flash memory ...

Page 13

... Multiple Device Selection The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID strapping in a system. When the SST49LF008A is used as a boot device, ID[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). ...

Page 14

... The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on the SST49LF008A recommended that the FGPI[4:0] pins are in the desired state before FWH4 is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register ...

Page 15

... A Microchip Technology Company Block Locking Registers SST49LF008A provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and it is accessible through standard addressable memory locations specified in Table 6. Unused register locations will read as 00H. Table 6: Block Locking Registers for SST49LF008A ...

Page 16

... Register is not available for read when the device is in Erase/Program operation. Unused register location will read as 00H. Refer to the relevant application note for details. See Table 2 for the device ID code. ©2011 Silicon Storage Technology, Inc. 8 Mbit Firmware Hub 16 SST49LF008A Data Sheet DS25085A 10/11 ...

Page 17

... RST# pin initiates a device reset. IL Read The Read operation of the SST49LF008A device is controlled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 13, for further details. Byte-Program Operation The SST49LF008A device is programmed on a byte-by-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased ...

Page 18

... Data# Polling or Toggle Bit methods. See Figure 19 for timing waveforms. Any commands written during the Block-Erase operation will be ignored. Chip-Erase The SST49LF008A device provides a Chip-Erase operation only in PP Mode, which allows the user to erase the entire memory array to the 1s state. This is useful when the entire device must be quickly erased. ...

Page 19

... A Microchip Technology Company Write Operation Status Detection The SST49LF008A device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ after the rising edge of WE# which initiates the internal Program or Erase operation. ...

Page 20

... The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of a six-byte load sequence. The SST49LF008A device is shipped with the Software Data Protection permanently enabled. See Table 9 for the specific software command codes ...

Page 21

... AAH 2AAAH 55H 5555H 90H 9 XXH F0H 9 5555H AAH 2AAAH 55H 5555H F0H -A (Hex), Addresses A -A can Mbit Firmware Hub SST49LF008A 3rd 4th 5th Write Cycle Write Cycle Data Addr Data Addr Data Addr 3 BA Data ...

Page 22

... Ambient Temp 0°C to 85°C 1,2 Input Rise/Fall Time 3ns 22 8 Mbit Firmware Hub SST49LF008A -2.0V to ° C capable in both non-Pb and with-Pb solder versions. ° C for 10 seconds; please consult the factory for the latest ...

Page 23

... For FWH mode 1/T IH Mbit Firmware Hub SST49LF008A 1 Test Conditions LCLK and Address Input (FWH mode) ( f33 MHz ( mode) FWH mode ILT IHT ( ) PP Mode min All other inputs All outputs open, V ...

Page 24

... Parameter Minimum Specification Endurance Data Retention Latch Up Parameter CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate (peak-to-peak) RST# or INIT# Slew Rate 24 8 Mbit Firmware Hub SST49LF008A Minimum 100 100 Test Condition I Units Test Method ...

Page 25

... Minimum and maximum times have different loads. See PCI spec. ©2011 Silicon Storage Technology, Inc. 8 Mbit Firmware Hub T cyc T high 0 low 0 3.0-3.6V (FWH Mode) DD Min SST49LF008A Data Sheet 0.4 V p-to-p DD (minimum) 1161 F11.0 Max Units µ 100 ms ...

Page 26

... V OUT -25(V 1)/0.015 IN 25(V -V -1)/0.015 3.0-3.6V (FWH Mode) DD stable to Reset Low if a reset procedure is performed during a Program or Erase operation. RSTE 26 8 Mbit Firmware Hub SST49LF008A 3.0-3.6V (FWH Mode) Limits Max Units Test Conditions 0. < V OUT ) mA 0.3V < Equation C 0.7V < ...

Page 27

... Silicon Storage Technology, Inc. T PRST T KRST T RSTF CLK V TEST T VAL FWH [3:0] (Valid Output Data) FWH [3:0] (Float Output Data OFF 27 8 Mbit Firmware Hub SST49LF008A Data Sheet T RSTP Sector-/Block-Erase T RSTE or Program operation aborted T RST 1161 F12 1161 F13.0 DS25085A 10/11 ...

Page 28

... Production testing may MAX use different voltage values, but must correlate results back to these parameters. ©2011 Silicon Storage Technology, Inc. CLK T FWH [3:0] of overdrive over Mbit Firmware Hub SST49LF008A V TEST Inputs V MAX Valid 1161 F14.0 ...

Page 29

... RSTC 1. There will be a reset latency of T ©2011 Silicon Storage Technology, Inc. DD 3.0-3.6V (PP Mode) DD stable to Reset Low reset procedure is performed during a Program or Erase operation. RSTE RSTC 29 8 Mbit Firmware Hub SST49LF008A 3.0-3.6V (PP Mode) Min Max 270 120 3.0-3.6V (PP Mode) ...

Page 30

... PRST T RSTP T T RST RC Row Address Column Address OLZ High Mbit Firmware Hub SST49LF008A Data Sheet Row Address T RSTP Sector-/Block-Erase T RSTE or Program operation aborted T RSTC Chip-Erase aborted T T RSTF RST Row Address Column Address T AH ...

Page 31

... Figure 15:Data# Polling Timing Diagram (PP Mode) ©2011 Silicon Storage Technology, Inc. T RSTP T RST Row Address Column Address CWH T OES Row Column T OEP Mbit Firmware Hub SST49LF008A Data Sheet T OEH T WPH Data Valid 1161 F17 1161 F18.0 DS25085A 10/11 ...

Page 32

... Silicon Storage Technology, Inc. Row Column T OET D Four-Byte Code for Byte-Program 5555 2AAA WPH SB0 SB1 Byte-Program Address 32 8 Mbit Firmware Hub SST49LF008A 5555 Internal Program Starts SB2 SB3 A0 Data DS25085A Data Sheet D 1161 F19.0 1161 F20.0 10/11 ...

Page 33

... Six-Byte code for Block-Erase Operation 5555 2AAA 5555 5555 WPH SB0 SB1 SB2 SB3 Mbit Firmware Hub SST49LF008A Data Sheet 2AAA SB4 SB5 Internal Erasure Starts 55 30 1161 F21.0 2AAA Internal Erasure Starts SB4 ...

Page 34

... Three-byte sequence for Software ID Entry 5555 2AAA 5555 T T IDA WP T WPH SW0 SW1 SW2 Device ID 5AH for SST49LF008A 34 8 Mbit Firmware Hub SST49LF008A 2AAA 5555 T SCE SB3 SB4 SB5 Internal Erasure Starts 1161 F23.0 0000 0001 T AA ...

Page 35

... SW1 SW2 INPUT REFERENCE POINTS IT (0.9 ) for a logic 1 and V V IHT DD 90%) are <5 ns. TO DUT 1161 F27 Mbit Firmware Hub SST49LF008A Data Sheet V OUTPUT OT 1161 F26.0 (0.1 ) for a logic 0. Mea- V ILT DD (0.5 ) and V (0.5 ). Input rise ...

Page 36

... Mbit Firmware Hub Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program ( Data# Polling bit, or Toggle bit operation) Program Completed 1161 F28.0 36 SST49LF008A Data Sheet DS25085A 10/11 ...

Page 37

... Silicon Storage Technology, Inc. 8 Mbit Firmware Hub Toggle Bit Byte- Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match Yes Program/Erase Completed 37 SST49LF008A Data Sheet Data# Polling Byte- Program/Erase Initiated Read true data Yes Program/Erase Completed 1161 F29.0 DS25085A 10/11 ...

Page 38

... Address: 2AAAH Address: 2AAAH Write data: 90H Write data: F0H Address: 5555H Address: 5555H Wait T IDA Return to normal 38 8 Mbit Firmware Hub SST49LF008A Software Product ID Exit Reset Command Sequence Write data: F0H Address: XXH Wait T IDA Return to normal operation Wait T IDA operation 1161 F30 ...

Page 39

... Address: 5555H Address Wait Options Wait Options Chip erased Block erased to FFH to FFH 39 8 Mbit Firmware Hub SST49LF008A Data Sheet Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH ...

Page 40

... Product Ordering Information SST Valid combinations for SST49LF008A SST49LF008A-33-4C-WHE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. ©2011 Silicon Storage Technology, Inc. ...

Page 41

... R. x 30° .023 MAX .032 .026 .050 BSC .050 BSC .140 .125 41 8 Mbit Firmware Hub SST49LF008A Data Sheet BOTTOM VIEW .040 R. .030 .021 .013 .400 .530 BSC .490 .015 Min. .095 .075 .032 .026 32-plcc-NH-3 DS25085A ...

Page 42

... Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. Figure 30:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2011 Silicon Storage Technology, Inc. Pin # 1 Identifier 12.50 12.30 14.20 13. Mbit Firmware Hub SST49LF008A Data Sheet 1.05 0.95 0.50 BSC 8.10 0.27 7.90 0.17 0.15 0.05 DETAIL 1 ...

Page 43

... Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. Figure 31:40-lead Thin Small Outline Package (TSOP) 10mm x 20mm SST Package Code: EI ©2011 Silicon Storage Technology, Inc. 8 Mbit Firmware Hub 10.10 9.90 18.50 18.30 20.20 19.80 43 SST49LF008A Data Sheet 1.05 0.95 0.50 BSC 0.27 0.17 0.15 0.05 DETAIL 1.20 max. 0°- 5° ...

Page 44

... Updated footnote for Output Short Circuit Current. Updated Data# Polling description Corrected the values in Table 5 on page 14: General Purpose Inputs Register Added note to Table 12 on page 23: DC Operating Characteristics Added 40-lead TSOP for SST49LF008A only Corrected the I Test Conditions in Table 12 on page 23 DD 2004 Data Book ...

Page 45

... SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. ©2011 Silicon Storage Technology, Inc. 8 Mbit Firmware Hub Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com 45 SST49LF008A Data Sheet DS25085A 10/11 ...

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