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PIC16(L)F1508 Datasheet

Download or read online Microchip Technology PIC16(L)F1508 20-Pin Flash, 8-Bit Microcontrollers With NanoWatt XLP Technology pdf datasheet.



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PIC16(L)F1508/9
Data Sheet
20-Pin Flash, 8-Bit Microcontrollers
with nanoWatt XLP Technology
Preliminary
 2011 Microchip Technology Inc.
DS41609A

Summary of Contents

Page 1

... Flash, 8-Bit Microcontrollers 2011 Microchip Technology Inc. PIC16(L)F1508/9 with nanoWatt XLP Technology Preliminary Data Sheet DS41609A ...

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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...

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... Low-Power Sleep mode - Low-Power BOR (LPBOR) Integrated Temperature Indicator 128 Bytes High-Endurance Flash - 100,000 write Flash endurance (minimum) 2011 Microchip Technology Inc. PIC16(L)F1508/9 with nanoWatt XLP Technology Extreme Low-Power Management with nanoWatt XLP (PIC16LF1508/9): Standby Current 1.8V, typical • ...

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... DS41607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers. 2: DS41586 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers. 3: DS41609 PIC16(L)F1508/1509 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers. 4: DS41609A-page 4 Numerically Controlled Oscillator (NCO): - 20-bit accumulator - 16-bit increment - True linear frequency control ...

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... FIGURE 1: 20-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1508/9 PDIP, SOIC, SSOP MCLR/V Note: See Table 1 for location of all peripheral functions. FIGURE 2: 20-PIN QFN PACKAGE DIAGRAM FOR PIC16(L)F1508/9 QFN 4x4 MCLR/V /RA3 PP RC5 RC4 RC3 RC6 Note: See Table 1 for location of all peripheral functions.  ...

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... PIC16(L)F1508/9 TABLE 1: 20-PIN ALLOCATION TABLE (PIC16(L)F1508/9) RA0 19 16 AN0 DACOUT1 C1IN RA1 18 15 AN1 V C1IN0- REF C2IN0- RA2 17 14 AN2 DACOUT2 C1OUT RA3 4 1 RA4 3 20 AN3 RA5 2 19 RB4 13 10 AN10 — ...

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... Development Support... 359 32.0 Packaging Information... 363 Appendix A: Data Sheet Revision History... 373 Index ... 375 The Microchip Web Site ... 381 Customer Change Notification Service ... 381 Customer Support ... 381 Reader Response ... 382 Product Identification System ... 383 2011 Microchip Technology Inc. PIC16(L)F1508/9 Preliminary DS41609A-page 7 ...

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... PIC16(L)F1508/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

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... DEVICE OVERVIEW The PIC16(L)F1508/9 are described within this data sheet. They are available in 14-pin packages. shows a block diagram of the PIC16(L)F1508/9 devices. Tables 1-2 shows the pinout descriptions. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral Analog-to-Digital Converter (ADC) Complementary Wave Generator (CWG) ...

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... PIC16(L)F1508/9 FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM Timing OSC2/CLKOUT Generation OSC1/CLKIN INTRC Oscillator MCLR CLC1 CLC2 C1 C2 Temp. ADC EUSART Indicator 10-Bit Note 1: See applicable chapters for more information on peripherals. See Table 1-1 2: DS41609A-page 10 Program Flash Memory CPU (Figure 2-1) CLC3 CLC4 Timer0 ...

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... TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN/DACOUT1/ RA0 ICSPDAT/ICDDAT AN0 C1IN DACOUT1 ICSPDAT ICDDAT RA1/AN1/CLC4IN1/V / RA1 REF C1IN0-/C2IN0-/ICSPCLK/ AN1 ICDCLK CLC4IN1 V REF C1IN0- C2IN0- ICSPCLK ICDCLK RA2/AN2/C1OUT/DACOUT2/ RA2 (1) T0CKI/INT/PWM3/CLC1 / AN2 CWG1FLT C1OUT DACOUT2 T0CKI INT PWM3 CLC1 ...

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... PIC16(L)F1508/9 TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED) Name Function RB4/AN10/CLC3IN0/SDA/SDI RB4 AN10 CLC3IN0 SDA SDI RB5/AN11/CLC4IN0/RX/DT RB5 AN11 CLC4IN0 RX DT RB6/SCL/SCK RB6 SCL SCK RB7/CLC3/TX/CK RB7 CLC3 TX CK RC0/AN4/CLC2/C2IN RC0 AN4 CLC2 C2IN RC1/AN5/C1IN1-/C2IN1-/PWM4/ RC1 (1) NCO1 AN5 C1IN1- ...

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... TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED) Name Function (2) RC5/PWM1/CLC1 / RC5 CWG1A PWM1 CLC1 CWG1A (2) RC6/AN8/NCO1 /CLC3IN1/ RC6 (1) SS AN8 NCO1 CLC3IN1 SS RC7/AN9/CLC1IN1/SDO RC7 AN9 CLC1IN1 SDO Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input ...

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... PIC16(L)F1508/9 NOTES: DS41609A-page 14 Preliminary 2011 Microchip Technology Inc. ...

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... Section 3.5 Indirect Addressing 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 Instruction Set Summary details. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Saving, for more for more Preliminary DS41609A-page 15 ...

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... PIC16(L)F1508/9 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control CLKIN Timing Timing ...

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... PIC16LF1508 PIC16F1509 PIC16LF1509 Note 1: High-endurance Flash applies to low byte of each address in the range. 2011 Microchip Technology Inc. PIC16(L)F1508/9 The following features are associated with access and control of program memory and data memory: PCL and PCLATH Stack Indirect Addressing 3 ...

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... PIC16(L)F1508/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1508 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 On-chip Program Memory Page 1 Rollover to Page 0 Rollover to Page 1 DS41609A-page 18 FIGURE 3-2: CALL, CALLW RETURN, RETLW ...

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... BRW instruction is not available so the older table read method must be used. 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by set- ting bit 7 of the FSRxH register and reading the match- ing INDFx register ...

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... PIC16(L)F1508/9 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): 12 core registers 20 Special Function Registers (SFR) • bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘ ...

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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2011 Microchip Technology Inc. PIC16(L)F1508/9 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...

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... Bank Offset 00h 0Bh 0Ch 1Fh 20h Section 3.5.2 6Fh 70h 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1508/9 are as shown in Table 3-5 and Preliminary BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM ...

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... TABLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 1-7 BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh 00Fh 08Fh ...

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TABLE 3-4: PIC16(L)F1509 MEMORY MAP, BANK 1-7 BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh ...

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... TABLE 3-5: PIC16(L)F1508/9 MEMORY MAP, BANK 8-23 BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch 40Dh 48Dh 50Dh 40Eh 48Eh 50Eh 40Fh 48Fh ...

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... TABLE 3-6: PIC16(L)F1508/9 MEMORY MAP, BANK 24-31 BANK 24 BANK 25 C00h C80h D00h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) C0Bh C8Bh D0Bh C0Ch C8Ch D0Ch C0Dh C8Dh D0Dh C0Eh C8Eh D0Eh C0Fh C8Fh ...

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... TABLE 3-7: PIC16(L)F1508/9 MEMORY MAP, BANK 30-31 Bank 30 F0Ch F0Dh F0Eh CLCDATA F0Fh CLC1CON F10h CLC1POL F11h CLC1SEL0 F12h CLC1SEL1 F13h CLC1GLS0 F14h CLC1GLS1 F15h CLC1GLS2 F16h CLC1GLS3 F17h CLC2CON F18h CLC2POL F19h CLC2SEL0 F1Ah CLC2SEL1 F1Bh CLC2GLS0 F1Ch ...

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... PIC16(L)F1508/9 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-8 addressed from any Bank. TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY Addr Name Bit 7 Bit 6 Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 x80h (not a physical register) ...

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... ADCON2 TRIGSEL<3:0> unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Legend: PIC16F1508/9 only. Note 1: 2: Unimplemented, read as 1. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 RA5 RA4 RA3 RA2 RB5 RB4 — ...

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... PIC16(L)F1508/9 TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 2 10Ch LATA 10Dh LATB LATB7 LATB6 10Eh LATC LATC7 LATC6 10Fh Unimplemented 110h Unimplemented 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 ...

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... NCO1CLK N1PWS<2:0> unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Legend: PIC16F1508/9 only. Note 1: Unimplemented, read as 1. 2: 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 WPUA5 WPUA4 WPUA3 WPUA2 WPUB5 WPUB4 — ...

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... PIC16(L)F1508/9 TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 10 50Ch to Unimplemented 51Fh Bank 11 58Ch to Unimplemented 59Fh Bank 12 60Ch to Unimplemented 610h 611h PWM1DCL PWM1DCL<7:6> 612h PWM1DCH 613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL 614h PWM2DCL PWM2DCL<7:6> ...

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... Unimplemented F6Fh Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: PIC16F1508/9 only. 2: Unimplemented, read as 1. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 MLC4OUT MLC3OUT LC1OUT LC1INTP LC1INTN — ...

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... PIC16(L)F1508/9 TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 31 F8Ch Unimplemented FE3h FE4h STATUS_ SHAD FE5h WREG_ Working Register Shadow SHAD FE6h BSR_ SHAD FE7h PCLATH_ Program Counter Latch High Register Shadow ...

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... PCL register, all 15 bits of the program counter will change to the values con- tained in the PCLATH register and those being written to the PCL register. 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a ...

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... PIC16(L)F1508/9 3.4 Stack All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution ...

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... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL 2011 Microchip Technology Inc. PIC16(L)F1508/9 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the ...

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... PIC16(L)F1508/9 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to 1, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register ...

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... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: 2011 Microchip Technology Inc. PIC16(L)F1508/9 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...

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... PIC16(L)F1508/9 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select ...

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... Location Select 0x2000 0x29AF 2011 Microchip Technology Inc. PIC16(L)F1508/9 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...

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... PIC16(L)F1508/9 NOTES: DS41609A-page 42 Preliminary 2011 Microchip Technology Inc. ...

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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Words is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. PIC16(L)F1508/9 by device Preliminary DS41609A-page 43 ...

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... PIC16(L)F1508/9 REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 FCMEN bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor is enabled 0 Fail-Safe Clock Monitor is disabled bit 12 ...

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... Note 1: See Vbor parameter for specific trip point voltages. 2: The DEBUG bit in Configuration Words is managed automatically by device development tools including 3: debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/P-1 R/P-1 R/P-1 (3) DEBUG LPBOR ...

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... PIC16(L)F1508/9 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words ...

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... PIC16F1509 10 1101 010 PIC16LF1509 10 1101 000 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). 2011 Microchip Technology Inc. PIC16(L)F1508 DEV<8:3> REV<4:0> Unimplemented bit, read as 1 -n/n Value at POR and BOR/Value at all other Resets P Programmable bit DEVICEID< ...

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... PIC16(L)F1508/9 NOTES: DS41609A-page 48 Preliminary 2011 Microchip Technology Inc. ...

Page 49

... Fast start-up oscillator allows internal circuits to power-up and stabilize before switching to the 16 MHz HFINTOSC 2011 Microchip Technology Inc. PIC16(L)F1508/9 The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low-Power mode (0 MHz to 0.5 MHz) 2. ECM – ...

Page 50

... PIC16(L)F1508/9 FIGURE 5-1: SIMPLIFIED PIC CLKIN/ OSC1/ SOSCI/ T1CKI Primary Oscillator (OSC) CLKOUT / OSC2 SOSCO/ T1G Secondary Oscillator (SOSC) Start-up Control Logic 16 MHz Primary OSC Start-Up OSC 31 kHz Source DS41609A-page 50 ® MCU CLOCK SOURCE BLOCK DIAGRAM Primary Clock Secondary Clock INTOSC IRCF< ...

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... High power, 4-20 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low power, 0-0.5 MHz (FOSC 101) 2011 Microchip Technology Inc. PIC16(L)F1508/9 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

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... PIC16(L)F1508/9 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the Oscillator mode F selected (typically between 2 M  . ...

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... Crystal to a PIC16F690/SS (DS91097) AN1288, Design Practices for Low-Power External Oscillators (DS01288) 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.2.1.5 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...

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... PIC16(L)F1508/9 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscil- lator block as the system clock by performing one of the following actions: Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • ...

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... Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.2.2.4 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC and the ...

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... PIC16(L)F1508/9 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC 0 IRCF <3:0> System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock ...

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... OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.3.3 SECONDARY OSCILLATOR The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...

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... PIC16(L)F1508/9 5.4 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device ...

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... OSC2 Program Counter System Clock 2011 Microchip Technology Inc. PIC16(L)F1508/9 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator ...

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... PIC16(L)F1508/9 5.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words ...

Page 61

... Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Oscillator Failure Test Test Preliminary Failure Detected ...

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... PIC16(L)F1508/9 5.6 Oscillator Control Registers REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-0/0 R/W-1/1 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 Unimplemented: Read as 0 bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits ...

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... CONFIG1 7:0 CP MCLRE Legend: unimplemented location, read as 0 . Shaded cells are not used by clock sources. 2011 Microchip Technology Inc. PIC16(L)F1508/9 R-0/q U-0 HFIOFR — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Conditional Bit 5 ...

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... PIC16(L)F1508/9 NOTES: DS41609A-page 64 Preliminary 2011 Microchip Technology Inc. ...

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... ICSP Programming Mode Exit RESET Instruction Stack Pointer MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR (1) Active See Table 6-1 for BOR active conditions. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 PWRT R Done PWRTE LFINTOSC Preliminary Device Reset DS41609A-page 65 ...

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... PIC16(L)F1508/9 6.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

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... Unimplemented: Read as 0 bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 The Brown-out Reset circuit is active 0 The Brown-out Reset circuit is inactive BOREN<1:0> bits are located in Configuration Words. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 PWRT (1) T < T PWRT (1) T PWRT ...

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... PIC16(L)F1508/9 6.3 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset ...

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... FIGURE 6-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16(L)F1508/9 T PWRT T MCLR Preliminary DS41609A-page 69 ...

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... PIC16(L)F1508/9 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR ...

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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16(L)F1508/9 6-2. R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT RMCLR Bit is set by hardware U Unimplemented bit, read as ‘ ...

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... PIC16(L)F1508/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN BORFS PCON STKOVF STKUNF STATUS WDTCON Legend: unimplemented bit, reads as 0. Shaded cells are not used by Resets. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. ...

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... A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2011 Microchip Technology Inc. PIC16(L)F1508/9 TMR0IF TMR0IE INTF INTE IOCIF IOCIE PEIE GIE Preliminary Wake-up (If in Sleep mode) ...

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... PIC16(L)F1508/9 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: GIE bit of the INTCON register Interrupt Enable bit(s) for the specific interrupt event(s) PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the ...

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... Execute 2 Cycle Instruction at PC Interrupt GIE PC PC-1 PC Execute 3 Cycle Instruction at PC Interrupt GIE PC PC-1 PC Execute 3 Cycle Instruction at PC 2011 Microchip Technology Inc. PIC16(L)F1508/9 Interrupt Sampled during Q1 PC1 0004h Inst(PC) NOP NOP PC1/FSR New PC/ 0004h ADDR PC1 Inst(PC) NOP NOP FSR ADDR ...

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... PIC16(L)F1508/9 FIGURE 7-3: INT PIN INTERRUPT TIMING OSC CLKOUT (3) INT pin (1) INTF (4) GIE INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. ...

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... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the users appli- cation, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Preliminary DS41609A-page 77 ...

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... PIC16(L)F1508/9 7.6 Interrupt Control Registers 7.6.1 INTCON REGISTER The INTCON register is a readable and writable register, that contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 GIE PEIE ...

Page 79

... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...

Page 80

... PIC16(L)F1508/9 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 81

... Enables the CLC 2 interrupt 0 Disables the CLC 2 interrupt bit 0 CLC1IE: Configurable Logic Block 1 Interrupt Enable bit 1 Enables the CLC 1 interrupt 0 Disables the CLC 1 interrupt 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. U-0 R/W-0/0 R/W-0/0 — ...

Page 82

... PIC16(L)F1508/9 7.6.5 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 83

... Interrupt is pending 0 Interrupt is not pending bit 1-0 Unimplemented: Read as 0 2011 Microchip Technology Inc. PIC16(L)F1508/9 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register ...

Page 84

... PIC16(L)F1508/9 7.6.7 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as shown in Register 7-7. REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 Unimplemented: Read as ‘ ...

Page 85

... PIR1 TMR1GIF ADIF PIR2 OSFIF C2IF PIR3 Legend: unimplemented location, read as 0. Shaded cells are not used by interrupts. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF PSA RCIE TXIE SSP1IE — ...

Page 86

... PIC16(L)F1508/9 NOTES: DS41609A-page 86 Preliminary 2011 Microchip Technology Inc. ...

Page 87

... FVR module. See Fixed Voltage Reference (FVR) information on this module. 2011 Microchip Technology Inc. PIC16(L)F1508/9 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 88

... PIC16(L)F1508/9 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. ...

Page 89

... Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 2011 Microchip Technology Inc. PIC16(L)F1508/9 8.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected ...

Page 90

... PIC16(L)F1508/9 REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Unimplemented: Read as 0 bit 1 VREGPM: Voltage Regulator Power Mode Selection bit ...

Page 91

... Configurable time-out period is from 256 seconds (typical) Multiple Reset conditions Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16(L)F1508/9 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41609A-page 91 ...

Page 92

... PIC16(L)F1508/9 9.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 29.0 Electrical Specifications LFINTOSC tolerances. 9.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE< ...

Page 93

... If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) ...

Page 94

... PIC16(L)F1508/9 TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 OSCCON PCON STKOVF STKUNF STATUS WDTCON — unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by Watchdog Timer. Legend: TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER ...

Page 95

... See Table 10-1 write latches for Flash program memory. TABLE 10-1: Device PIC16(L)F1508 PIC16(L)F1509 Preliminary for Erase Row size and the number of FLASH MEMORY ORGANIZATION BY DEVICE Write Row Erase ...

Page 96

... PIC16(L)F1508/9 10.2.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the desired address PMADRH:PMADRL register pair. 2. Clear the CFGS bit of the PMCON1 register. 3. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data ...

Page 97

... PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16(L)F1508/9 PMADRH,PMADRL PC3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP ...

Page 98

... PIC16(L)F1508/9 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write pro- gramming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: Row Erase Load program memory write latches • ...

Page 99

... This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 10-4: FLASH PROGRAM MEMORY ERASE FLOWCHART ...

Page 100

... PIC16(L)F1508/9 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE BANKSEL PMADRL MOVF ...

Page 101

... Microchip Technology Inc. PIC16(L)F1508/9 The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO 1 ...

Page 102

FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES PMADRH - Row PMADRH<6:0> Address :PMADRL<7:5> Decode ...

Page 103

... Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Write Operation (FREE 0) Load Write Latches Only (LWLO 1) 2011 Microchip Technology Inc. PIC16(L)F1508/9 Enable Write/Erase Operation (WREN 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Yes Last word to ...

Page 104

... PIC16(L)F1508/9 EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits 00000) is loaded in ADDRH:ADDRL ...

Page 105

... Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure x.x) Figure 10-2 ...

Page 106

... PIC16(L)F1508/9 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User IDs, Device ID/Revision ID and Configuration Words can be accessed when CFGS 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> but not all addresses are accessible. ...

Page 107

... RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 10-2 PMDAT No RAM image ? Fail Yes Verify Operation No Last Word ? Yes End Verify Operation 2011 Microchip Technology Inc. PIC16(L)F1508/9 Preliminary DS41609A-page 107 ...

Page 108

... PIC16(L)F1508/9 10.6 Flash Program Memory Control Registers REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory ...

Page 109

... Note 1: Unimplemented bit, read as 1 . 2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE 2011 Microchip Technology Inc. PIC16(L)F1508/9 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE WRERR WREN U Unimplemented bit, read as ‘ ...

Page 110

... PIC16(L)F1508/9 REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 bit 7 Legend Readable bit W Writable bit S Bit can only be set x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register ...

Page 111

... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 11-1: D Write LATx Write PORTx Data Register ...

Page 112

... PIC16(L)F1508/9 11.1 Alternate Pin Function The Alternate Pin Function Control register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 11-1. For this device family, the following functions can be moved between different pins. SS T1G • ...

Page 113

... MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs 2011 Microchip Technology Inc. PIC16(L)F1508/9 11.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority ...

Page 114

... PIC16(L)F1508/9 REGISTER 11-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x RA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 RA<5:0>: PORTA I/O Value bits 1 Port pin is > Port pin is < Writes to PORTA are actually written to corresponding LATA register ...

Page 115

... Analog input. Pin is assigned as analog input 0 Digital I/O. Pin is assigned to port or digital special function. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-x/u U-0 R/W-x/u LATA4 ...

Page 116

... PIC16(L)F1508/9 REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 WPUA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 WPUA<5:0>: Weak Pull-up Register bits 1 Pull-up enabled 0 Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled ...

Page 117

... Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to 0 by user software. 2011 Microchip Technology Inc. PIC16(L)F1508/9 11.3.2 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The ...

Page 118

... PIC16(L)F1508/9 REGISTER 11-7: PORTB: PORTB REGISTER R/W-x/x R/W-x/x R/W-x/x RB7 RB6 RB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Value bits 1 Port pin is > Port pin is < bit 3-0 Unimplemented: Read as 0 ...

Page 119

... Digital I/O. Pin is assigned to port or digital special function. bit 3-0 Unimplemented: Read as 0 When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-x/u U-0 U-0 LATB4 ...

Page 120

... PIC16(L)F1508/9 REGISTER 11-11: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 Pull-up enabled 0 Pull-up disabled bit 3-0 Unimplemented: Read as 0 ...

Page 121

... Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to 0 by user software. 2011 Microchip Technology Inc. PIC16(L)F1508/9 11.4.2 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The ...

Page 122

... PIC16(L)F1508/9 REGISTER 11-12: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits 1 Port pin is > Port pin is < ...

Page 123

... RC7 RC6 TRISC TRISC7 TRISC6 Legend unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTC. 2011 Microchip Technology Inc. PIC16(L)F1508/9 U-0 R/W-1/1 R/W-1/1 ANSC3 ANSC2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) ...

Page 124

... PIC16(L)F1508/9 NOTES: DS41609A-page 124 Preliminary 2011 Microchip Technology Inc. ...

Page 125

... A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. 2011 Microchip Technology Inc. PIC16(L)F1508/9 12.3 Interrupt Flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port ...

Page 126

... PIC16(L)F1508/9 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx RAx IOCAPx Q4Q1 Q4Q1 DS41609A-page 126 Q4Q1 Edge Detect Data Bus Write IOCAFx CK From all other IOCAFx individual Pin Detectors Q1 Q2 ...

Page 127

... An enabled change was detected on the associated pin. Set when IOCAPx 1 and a rising edge was detected on RAx, or when IOCANx 1 and a falling edge was detected on RAx change was detected, or the user cleared the detected change. 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-0/0 R/W-0/0 R/W-0/0 IOCAP4 ...

Page 128

... PIC16(L)F1508/9 REGISTER 12-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 Interrupt-on-Change enabled on the pin for a positive going edge. ...

Page 129

... TRISB TRISB7 TRISB6 unimplemented location, read as 0 . Shaded cells are not used by interrupt-on-change. Legend: Note 1: Unimplemented, read as 1 . 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 TMR0IE INTE ...

Page 130

... PIC16(L)F1508/9 NOTES: DS41609A-page 130 Preliminary 2011 Microchip Technology Inc. ...

Page 131

... BOREN<1:0> and BORFS 1 LDO All PIC16F1508/9 devices, when VREGPM 1 and not in Sleep 2011 Microchip Technology Inc. PIC16(L)F1508/9 The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Refer- ence Section 15.0 “ ...

Page 132

... PIC16(L)F1508/9 13.3 FVR Control Registers REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 1 Fixed Voltage Reference is enabled ...

Page 133

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 14-1: 14.2 Minimum Operating V When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications ...

Page 134

... PIC16(L)F1508/9 TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Name Bit 7 Bit 6 FVRCON FVREN FVRRDY Shaded cells are unused by the temperature indicator module. Legend: DS41609A-page 134 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> Preliminary Register Bit 1 Bit 0 on page ADFVR<1:0> ...

Page 135

... Temp Indicator DAC FVR Buffer1 CHS<4:0> When ADON 0, all multiplexer inputs are disconnected. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADPREF 00 ...

Page 136

... PIC16(L)F1508/9 15.1 ADC Configuration When configuring and using the ADC the following functions must be considered: Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...

Page 137

... Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc. PIC16(L)F1508 DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 16 MHz 8 MHz (2) (2) (2) 125 ns 250 ns (2) (2) (2) ...

Page 138

... PIC16(L)F1508/9 15.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...

Page 139

... Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16(L)F1508/9 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...

Page 140

... PIC16(L)F1508/9 15.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: Disable pin output driver (Refer to the TRIS register) Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: Select ADC conversion clock • ...

Page 141

... Section 14.0 Temperature Indicator Module See 2: Section 16.0 Digital-to-Analog Converter (DAC) Module See 3: Section 13.0 Fixed Voltage Reference (FVR) 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) (2) (3) for more information ...

Page 142

... PIC16(L)F1508/9 REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 Right justified. Six Most Significant bits of ADRESH are set to 0 when the conversion result is loaded Left justified. Six Least Significant bits of ADRESL are set to ‘ ...

Page 143

... Unimplemented: Read as 0 This is a rising edge sensitive input for all sources. Note 1: 2: Signal also sets its corresponding interrupt flag. 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-0/0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 144

... PIC16(L)F1508/9 REGISTER 15-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 0 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 ADRES<9:2> : ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 15-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM 0 ...

Page 145

... Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 ADRES<7:0> : ADC Result Register bits Lower 8 bits of 10-bit conversion result 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-x/u R/W-x/u R/W-x/u — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 146

... PIC16(L)F1508/9 15.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (R ) and the internal sampling switch (R S impedance directly affect the time required to charge the capacitor C ...

Page 147

... T Note 1: Refer to Section 29.0 Electrical Specifications FIGURE 15-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 03h 02h 01h 00h V - REF 2011 Microchip Technology Inc. PIC16(L)F1508 Sampling Switch 0.  Rss R IC LEAKAGE (1) I 0. ...

Page 148

... PIC16(L)F1508/9 TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Name Bit 7 Bit 6 ADCON0 ADCON1 ADFM ADCS<2:0> ADCON2 TRIGSEL<3:0> ADRESH A/D Result Register High ADRESL A/D Result Register Low ANSELA ANSELB ANSELC ANSC7 ANSC6 INTCON GIE PEIE PIE1 TMR1GIE ADIE ...

Page 149

... Section 29.0 Specifications . 2011 Microchip Technology Inc. PIC16(L)F1508/9 16.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: ...

Page 150

... PIC16(L)F1508/9 FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM REF DACPSS DACEN FIGURE 16-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41609A-page 150 Digital-to-Analog Converter (DAC) V SOURCE Steps SOURCE - ...

Page 151

... Effects of a Reset A device Reset affects the following: DAC is disabled. DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Preliminary DS41609A-page 151 ...

Page 152

... PIC16(L)F1508/9 16.6 DAC Control Registers REGISTER 16-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 DACEN DACOE1 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled bit 6 Unimplemented: Read as ‘ ...

Page 153

... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2011 Microchip Technology Inc. PIC16(L)F1508/9 FIGURE 17- ...

Page 154

... PIC16(L)F1508/9 FIGURE 17-2: COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON 3 0 C12IN0- 1 C12IN1- MUX C12IN2- 2 (2) C12IN3- 3 CxVN - FVR Buffer2 4 CxVP 0 C IN X MUX 1 DAC CxSP (2) FVR Buffer2 2 3 CxON C PCH<1:0> Note 1: When CxON 0, the Comparator will produce a 0 at the output When CxON 0, all multiplexer inputs are disconnected ...

Page 155

... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2011 Microchip Technology Inc. PIC16(L)F1508/9 17.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by 17-1) contain setting the CxPOL bit of the CMxCON0 register ...

Page 156

... PIC16(L)F1508/9 17.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Section 29.0 Electrical Specifications more information. 17.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1 ...

Page 157

... ECCP Auto-Shutdown mode. 2011 Microchip Technology Inc. PIC16(L)F1508/9 17.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 17-3. Since the analog input pins share their ...

Page 158

... PIC16(L)F1508/9 FIGURE 17-3: ANALOG INPUT MODEL Analog Input pin Rs < 10K C PIN Legend Input Capacitance PIN I Leakage Current at the pin due to various junctions LEAKAGE R Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 29.0 Electrical Specifications ...

Page 159

... CxSYNC: Comparator Output Synchronous Mode bit 1 Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP ...

Page 160

... PIC16(L)F1508/9 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit ...

Page 161

... TRISC TRISC7 TRISC6 Legend: unimplemented location, read as 0 . Shaded cells are unused by the comparator module. Unimplemented, read as 1 . Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 ...

Page 162

... PIC16(L)F1508/9 NOTES: DS41609A-page 162 Preliminary 2011 Microchip Technology Inc. ...

Page 163

... T0CKI 1 TMR0SE TMR0CS 2011 Microchip Technology Inc. PIC16(L)F1508/9 18.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...

Page 164

... PIC16(L)F1508/9 18.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...

Page 165

... Legend: Unimplemented location, read as 0 . Shaded cells are not used by the Timer0 module. Page provides register information. Unimplemented, read as 1 . Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 166

... PIC16(L)F1508/9 NOTES: DS41609A-page 166 Preliminary 2011 Microchip Technology Inc. ...

Page 167

... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. PIC16(L)F1508/9 Gate Single-Pulse mode Gate Value Status Gate Event Interrupt Figure 19 block diagram of the Timer1 module. ...

Page 168

... PIC16(L)F1508/9 19.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...

Page 169

... Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. 2011 Microchip Technology Inc. PIC16(L)F1508/9 When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count ...

Page 170

... PIC16(L)F1508/9 19.5.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 gate circuitry. 19.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to- high pulse will automatically be generated and inter- nally supplied to the Timer1 gate circuitry ...

Page 171

... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16(L)F1508/9 19.7.1 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON ...

Page 172

... PIC16(L)F1508/9 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 19-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41609A-page 172 Preliminary 2011 Microchip Technology Inc. ...

Page 173

... T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16(L)F1508/9 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41609A-page 173 ...

Page 174

... PIC16(L)F1508/9 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41609A-page 174 Set by hardware on falling edge of T1GVAL Preliminary  ...

Page 175

... Synchronize asynchronous clock input with system clock (F bit 1 Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 and clears Timer1 gate flip-flop 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 176

... PIC16(L)F1508/9 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON 0 : This bit is ignored If TMR1ON Timer1 counting is controlled by the Timer1 gate function ...

Page 177

... TMR1GE T1GPOL Legend: unimplemented location, read as 0 . Shaded cells are not used by the Timer1 module. Page provides register information. Unimplemented, read as 1 . Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 — ...

Page 178

... PIC16(L)F1508/9 NOTES: DS41609A-page 178 Preliminary 2011 Microchip Technology Inc. ...

Page 179

... Interrupt on TMR2 match with PR2, respectively See Figure 20-1 for a block diagram of Timer2. FIGURE 20-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> 2011 Microchip Technology Inc. PIC16(L)F1508/9 TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary Sets Flag bit TMR2IF ...

Page 180

... PIC16(L)F1508/9 20.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (F /4). OSC TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS< ...

Page 181

... TMR2ON: Timer2 On bit 1 Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 Prescaler Prescaler Prescaler Prescaler is 64 2011 Microchip Technology Inc. PIC16(L)F1508/9 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 T2CKPS< ...

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... PIC16(L)F1508/9 TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Name Bit 7 Bit 6 INTCON GIE PEIE PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF PR2 Timer2 Module Period Register PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL PWM4CON ...

Page 183

... Daisy-chain connection of slave devices Figure 21 block diagram of the SPI interface module. FIGURE 21-1: MSSPX BLOCK DIAGRAM (SPI MODE) SDI SDO SS SCK 2011 Microchip Technology Inc. PIC16(L)F1508/9 Data Bus Read Write SSPBUF Reg SSPSR Reg bit 0 Shift Clock SSx Control 2 (CKP, CKE) ...

Page 184

... PIC16(L)F1508/9 2 The I C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching • ...

Page 185

... FIGURE 21-3: MSSP BLOCK DIAGRAM (I SCLx SDAx 2011 Microchip Technology Inc. PIC16(L)F1508/9 2 C SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg Shift Clock SSPxSR Reg MSb LSb SSPxMSK Reg Addr Match Match Detect SSPxADD Reg Set, Reset Start and ...

Page 186

... PIC16(L)F1508/9 21.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select ...

Page 187

... When SSPxSR receives a complete byte transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. 2011 Microchip Technology Inc. PIC16(L)F1508/9 SCKx SDIx SDOx SSx SCKx SDIx ...

Page 188

... PIC16(L)F1508/9 21.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) • ...

Page 189

... Input Sample (SMP 1 ) SSPxIF SSPxSR to SSPxBUF 2011 Microchip Technology Inc. PIC16(L)F1508/9 The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as Figure 21-5) ...

Page 190

... PIC16(L)F1508/9 21.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin ...

Page 191

... SSPxBUF SSPxBUF to SSPxSR SDOx bit 7 SDIx bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF 2011 Microchip Technology Inc. PIC16(L)F1508/9 SCK SDIx SDOx SSx SCK SDIx SDOx SSx SCK SDIx SDOx SSx Shift register SSPxSR and bit count are reset ...

Page 192

... PIC16(L)F1508/9 FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE 0) SSx Optional SCKx (CKP 0 CKE 0 ) SCKx (CKP 1 CKE 0 ) Write to SSPxBUF Valid SDOx bit 7 SDIx bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE 1) ...

Page 193

... TRISC5 Legend: Unimplemented location, read as 0 . Shaded cells are not used by the MSSP in SPI mode. Page provides register information. Unimplemented, read as 1 . Note 1: 2011 Microchip Technology Inc. PIC16(L)F1508/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 ...

Page 194

... PIC16(L)F1508/9 2 21.3 MODE OVERVIEW The Inter-Integrated Circuit Bus ( multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. 2 The I C bus specifies two signal connections: Serial Clock (SCLx) • ...

Page 195

... Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state ...

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... PIC16(L)F1508/9 2 21.4 MODE OPERATION All MSSP I C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC troller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with ...

Page 197

... Condition 2 FIGURE 21-13 RESTART CONDITION 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.4.7 RESTART CONDITION A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, ...

Page 198

... PIC16(L)F1508/9 21.4.9 ACKNOWLEDGE SEQUENCE The 9th SCLx pulse for any transferred byte in I dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release con- trol of the line during this time to shift in the response. ...

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... Steps 8-12 are repeated for all received bytes from the Master. 13. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. 2011 Microchip Technology Inc. PIC16(L)F1508/9 21.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set 2 ...

Page 200

Receiving Address SDAx SCLx SSPxIF BF SSPOV From Slave to Master Receiving Data ACK ACK D7 9 ...

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