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PIC24HJ128GP204 Datasheet

Download or read online Microchip Technology PIC24HJ128GP204 16-Bit Microcontrollers (up to 128 KB Flash and 8K SRAM) With Advanced Analog pdf datasheet.



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16-bit Microcontrollers
(up to 128 KB Flash and 8K SRAM) with Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
Clock Management
• 2% internal oscillator
• Programmable PLL and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Low-power management modes
• Fast wake-up and start-up
High-Efficiency Math Engine
• Single-cycle MUL plus hardware divide
Advanced Analog Features
• 10/12-bit ADC with 1.1Msps/500 ksps conversion
rate:
- Up to 13 ADC input channels and four S&H
- Flexible/Independent trigger sources
• 150 ns Comparators:
- Up to two Analog Comparator modules
- 4-bit DAC with two ranges for Analog Comparators
Input/Output
• Software remappable pin functions
• 5V-tolerant pins
• Selectable open drain and internal pull-ups
• Up to 5 mA overvoltage clamp current/pin
• Multiple external interrupts
Packages
Type
SPDIP
Pin Count
28
I/O Pins
21
Contact Lead/Pitch
.100''
Dimensions
1.365x.285x.135
''
Note:
All dimensions are in millimeters (mm) unless specified.
© 2007-2012 Microchip Technology Inc.
PIC24HJ32GP302/304,
PIC24HJ64GPX02/X04 and
PIC24HJ128GPX02/X04
System Peripherals
• Cyclic Redundancy Check (CRC) module
• Up to five 16-bit and up to two 32-bit Timers/
Counters
• Up to four Input Capture (IC) modules
• Up to four Output Compare (OC) modules
• Real-Time Clock and Calendar (RTCC) module
Communication Interfaces
• Parallel Master Port (PMP)
• Two UART modules (10 Mbps)
- Supports LIN 2.0 protocols
- RS-232, RS-485, and IrDA
• Two 4-wire SPI modules (15 Mbps)
• Enhanced CAN (ECAN) module (1 Mbaud) with
2.0B support
2
• I
C module (100K, 400K and 1Mbaud) with
SMBus support
Direct Memory Access (DMA)
• 8-channel hardware DMA with no CPU stalls or
overhead
• UART, SPI, ADC, ECAN, IC, OC, INT0
Qualification and Class B Support
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)
• Class B Safety Library, IEC 60730, VDE certified
Debugger Development Support
• In-circuit and in-application programming
• Two program breakpoints
• Trace and run-time watch
SOIC
QFN-S
28
28
21
21
1.27
0.65
17.9x7.50x2.05
6x6x0.9
®
support
QFN
TQFP
44
44
35
35
0.65
0.80
8x8x0.9
10x10x1
DS70293G-page 1

Summary of Contents

Page 1

... Contact Lead/Pitch .100'' Dimensions 1.365x.285x.135 '' Note: All dimensions are in millimeters (mm) unless specified. © 2007-2012 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 System Peripherals Cyclic Redundancy Check (CRC) module • five 16-bit and up to two 32-bit Timers/ Counters • four Input Capture (IC) modules • ...

Page 2

... The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CONTROLLER FAMILIES Device PIC24HJ128GP504 44 128 8 PIC24HJ128GP502 28 128 8 PIC24HJ128GP204 44 128 8 PIC24HJ128GP202 28 128 8 PIC24HJ64GP504 PIC24HJ64GP502 28 64 ...

Page 3

... Note 1: The RPx pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected Refer to Section 2.3 CPU Logic Filter Capacitor Connection (V © 2007-2012 Microchip Technology Inc. MCLR ...

Page 4

... AN12/RP12 24 10 PGEC2/RP11 25 9 PGED2/RP10 26 PIC24HJ32GP304 8 CAP ( PIC24HJ64GP204 7 V PIC24HJ64GP504 (1) RP25 PIC24HJ128GP204 29 5 (1) RP24 PIC24HJ128GP504 30 4 (1) RP23 31 3 (1) RP22 32 2 SDA1/RP9 33 1 Table 1 in this section for the list of available peripherals. ) for proper connection to this pin. CAP ...

Page 5

... Microchip Technology Inc. AN11/RP13 AN12/RP12 25 PGEC2/RP11 9 PIC24HJ32GP304 26 8 PGED2/EMCD2/RP10 (2) PIC24HJ64GP204 CAP PIC24HJ64GP504 (1) PIC24HJ128GP204 29 RP25 /CN19/PMA6/RC9 5 (1) PIC24HJ128GP504 4 RP24 /CN20/PMA5/RC8 30 (1) 3 RP23 /CN17/PMA0/RC7 31 ( RP22 /CN18/PMA1/RC6 33 1 SDA1/RP9 Table 1 in this section for the list of available peripherals. ...

Page 6

... High Temperature Electrical Characteristics ... 345 32.0 DC and AC Device Characteristics Graphs... 357 33.0 Packaging Information... 361 Appendix A: Revision History... 371 The Microchip Web Site ... 385 Customer Change Notification Service ... 385 Customer Support ... 385 Reader Response ... 386 Product Identification System... 387 DS70293G-page 6 © 2007-2012 Microchip Technology Inc. ...

Page 7

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2007-2012 Microchip Technology Inc. to receive the most current information on all of our products. DS70293G-page 7 ...

Page 8

... Section 36. Programmable Cyclic Redundancy Check (CRC) (DS70298) Section 37. Real-Time Clock and Calendar (RTCC) (DS70301) Section 38. Direct Memory Access (DS70215) Section 39. Oscillator (Part III) (DS70216) DS70293G-page 8 web site 2 C) (DS70195) © 2007-2012 Microchip Technology Inc. ...

Page 9

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices. Figure 1-1 shows a general block diagram of the core and peripheral modules PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2007-2012 Microchip Technology Inc. and families the DS70293G-page 9 ...

Page 10

... W Register Array Divide Support MCLR OC/ Timers UART1, 2 ADC1 PWM1-4 1-5 IC1 CNx I2C1 PORTA DMA RAM PORTB 16 DMA PORTC Controller Remappable Pins 16-bit ALU 16 Pin Diagrams for the specific pins and features © 2007-2012 Microchip Technology Inc. ...

Page 11

... SS2 I/O ST Legend: CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels PPS Peripheral Pin Select © 2007-2012 Microchip Technology Inc. PPS Description Analog input channels. No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...

Page 12

... Positive supply for peripheral logic and I/O pins. No CPU logic filter capacitor connection. No Ground reference for logic and I/O pins. No Analog voltage reference (high) input. No Analog voltage reference (low) input. Analog Analog input O Output TTL TTL input buffer P Power I Input © 2007-2012 Microchip Technology Inc. ...

Page 13

... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2007-2012 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling ...

Page 14

... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met © 2007-2012 Microchip Technology Inc. is ...

Page 15

... ECS Inc. ECS-100-20-5G3XDS-TR ECS Inc. ECS-200-20-5G3XDS-TR ECS Inc. NX3225SA 20MHZ AT-W NDK Legend Through Hole © 2007-2012 Microchip Technology Inc. 2.6 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Configuration ...

Page 16

... Alternatively, connect 10k resistor between V and the unused pins. Frequency Mounting Operating Tolerance Type Temperature ±0.5% TH -40°C to 85°C ±0.5% TH -40°C to 85°C ±0.5% TH -40°C to 85°C ±0.5% TH -40°C to 85°C © 2007-2012 Microchip Technology Inc. SS ...

Page 17

... Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. © 2007-2012 Microchip Technology Inc. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have sixteen, 16-bit working registers in the programmers model. Each of the working registers can serve as a data, and address or address offset register ...

Page 18

... Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2007-2012 Microchip Technology Inc. ...

Page 19

... FIGURE 3-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PROGRAMMERS MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG SRH © 2007-2012 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer ...

Page 20

... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocNameen534555 3.4.1 KEY RESOURCES Section 2. CPU (DS70204) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools DS70293G-page 20 © 2007-2012 Microchip Technology Inc. ...

Page 21

... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15> © 2007-2012 Microchip Technology Inc. U-0 U-0 ...

Page 22

... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70293G-page 22 U-0 U-0 U-0 U-0 R/C-0 R/W-0 (1) IPL3 PSV -n Value at POR U Unimplemented bit, read as 0 (1) © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 U-0 U-0 bit 0 1 Bit is set ...

Page 23

... Microchip Technology Inc. 3.6.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: • ...

Page 24

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293G-page 24 © 2007-2012 Microchip Technology Inc. ...

Page 25

... Reserved Device Configuration Registers Reserved DEVID (2) Reserved Note: Memory areas are not shown to scale. © 2007-2012 Microchip Technology Inc. 4.1 Program Address Space The program PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is 4M instructions. and The space is addressable by a 24-bit value derived ...

Page 26

... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Table. least significant word Instruction Width Section 7.1 Interrupt Vector PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2007-2012 Microchip Technology Inc. ...

Page 27

... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2007-2012 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...

Page 28

... X Data Unimplemented (X) DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. LSb Address 0x0000 0x07FE 0x0800 6 Kbyte Near Data Space 0x13FE 0x1400 0x17FE 0x1800 0x8000 0xFFFE © 2007-2012 Microchip Technology Inc. ...

Page 29

... Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwprod- ucts/Devices.aspx?dDoc- Nameen534555 © 2007-2012 Microchip Technology Inc. LSb 16 bits Address MSb LSb 0x0000 SFR Space ...

Page 30

Special Function Register Maps TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 ...

Page 31

... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE Legend unknown value on Reset, unimplemented, read as 0. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...

Page 32

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI IFS0 0084 DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF ...

Page 33

TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON TSIDL TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

Page 34

TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 OCSIDL OC2RS 0186 OC2R 0188 OC2CON 018A OCSIDL OC3RS 018C ...

Page 35

TABLE 4-10: UART2 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U2MODE 0230 UARTEN USIDL IREN U2STA 0232 UTXISEL1 UTXINV UTXISEL0 U2TXREG 0234 U2RXREG 0236 ...

Page 36

... CSS12 AD1CON4 0332 Legend unknown value on Reset, unimplemented, read as 0. Reset values are shown in hexadecimal. TABLE 4-14: ADC1 REGISTER MAP FOR PIC24HJ64GP204/504, PIC24HJ128GP204/504 AND PIC24HJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ...

Page 37

TABLE 4-15: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A ...

Page 38

TABLE 4-15: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE DMA6STA 03CC DMA6STB ...

Page 39

TABLE 4-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 CSIDL ABAT C1CTRL2 0402 C1VEC 0404 ...

Page 40

TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...

Page 41

TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C C1RXF11EID 046E C1RXF12SID 0470 C1RXF12EID 0472 C1RXF13SID 0474 C1RXF13EID 0476 C1RXF14SID 0478 C1RXF14EID ...

Page 42

... RPOR7 06CE Legend unknown value on Reset, unimplemented, read as 0. Reset values are shown in hexadecimal. TABLE 4-21: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — ...

Page 43

... PMSTAT 060E IBF IBOV Legend: unimplemented, read as 0. Reset values are shown in hexadecimal. TABLE 4-23: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN ...

Page 44

TABLE 4-24: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME RTCVAL 0624 RCFGCAL 0626 RTCEN RTCWREN RTCSYNC HALFSEC PADCFG1 02FC Legend: ...

Page 45

... LATB12 ODCB 02CE Legend unknown value on Reset, unimplemented, read as 0. Reset values are shown in hexadecimal. TABLE 4-30: PORTC REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ...

Page 46

TABLE 4-32: SECURITY REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 BSRAM 0750 SSRAM 0752 Legend unknown value on Reset, unimplemented, read as ...

Page 47

... PC<22:16> W15 (after CALL) POP : [--W15] PUSH : [W15] © 2007-2012 Microchip Technology Inc. 4.4.2 DATA RAM PROTECTION FEATURE The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled ...

Page 48

... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2007-2012 Microchip Technology Inc. ...

Page 49

... Remap/Read) Note 1: Data EA<15> is always 1 in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2007-2012 Microchip Technology Inc. 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers ...

Page 50

... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70293G-page 50 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits 0 1 bits bits Byte Select © 2007-2012 Microchip Technology Inc. ...

Page 51

... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007-2012 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is 1; the lower byte is selected when it is ‘ ...

Page 52

... PSV Area 0x800000 1111 or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2007-2012 Microchip Technology Inc. ...

Page 53

... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2007-2012 Microchip Technology Inc. PGEC2/PGED2 or PGEC3/PGED3), and three other lines for power (V (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the and microcontroller just before shipping the product. This ...

Page 54

... Development Tools MINIMUM ROW WRITE TIME 11064 Cycles × × 0.05 1 0.00375 Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles × × 0.05 1 0.00375 (Register 5-1) controls which 5- write-only register that is for further © 2007-2012 Microchip Technology Inc. ...

Page 55

... Reserved 0011 Memory word program operation 0010 No operation 0001 Memory row program operation 0000 Program a single Configuration register byte Note 1: These bits can only be reset on a POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007-2012 Microchip Technology Inc. (1) U-0 U-0 (1) U-0 R/W-0 — ...

Page 56

... Bit is set bit 15-8 Unimplemented: Read as 0 bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70293G-page 56 U-0 U-0 U-0 W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 W-0 W-0 bit Bit is unknown ...

Page 57

... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007-2012 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see 5. Write the program block to Flash memory: a) Set the NVMOP bits to 0001 to configure for row programming. Clear the ERASE bit and set the WREN bit ...

Page 58

... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2007-2012 Microchip Technology Inc. ...

Page 59

... Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2007-2012 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers and associated with the CPU and peripherals are forced to ...

Page 60

... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocNameen534555 6.1.1 KEY RESOURCES Section 8. Resets (DS70192) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools DS70293G-page 60 © 2007-2012 Microchip Technology Inc. ...

Page 61

... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is 1 (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2007-2012 Microchip Technology Inc. (1) U-0 U-0 ...

Page 62

... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is 1 (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70293G-page 62 (1) (CONTINUED) © 2007-2012 Microchip Technology Inc. ...

Page 63

... T PLL lock time (1.5 ms nominal), if PLL is enabled. LOCK © 2007-2012 Microchip Technology Inc. A warm Reset is the result of all other reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection bits (COSC< ...

Page 64

... BOR. The delay T ensures that the system power supplies have stabilized PWRT for more information. elapsed. FSCM LOCK OST 6 T FSCM 5 Run crosses the DD ensures the voltage regulator output BOR has elapsed, the SYSRST becomes PWRT © 2007-2012 Microchip Technology Inc. ...

Page 65

... POR. Section 28.0 Electrical Characteristics The POR status bit (POR) in the Reset Control register (RCON<0>) is set to indicate the Power-on Reset. © 2007-2012 Microchip Technology Inc. Parameter 6.4.1 Brown-out Reset (BOR) and the Reset Power-up timer (PWRT) The on-chip regulator has a Brown-out Reset (BOR) ...

Page 66

... The Trap Reset Flag bit (TRAPR) in the Reset Control register (RCON<15>) is set to indicate the Trap Conflict Reset. Refer to Section 7.0 Interrupt Controller more information on trap conflict Resets. © 2007-2012 Microchip Technology Inc. V BOR V BOR V BOR ...

Page 67

... IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits can be set or cleared by user software. © 2007-2012 Microchip Technology Inc. each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value. ...

Page 68

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293G-page 68 © 2007-2012 Microchip Technology Inc. ...

Page 69

... The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). © 2007-2012 Microchip Technology Inc. Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority ...

Page 70

... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70293G-page 70 0x000000 0x000002 0x000004 0x000014 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 0x0001FE 0x000200 (1) (1) © 2007-2012 Microchip Technology Inc. ...

Page 71

... Microchip Technology Inc. AIVT Address 0x000104 Reserved 0x000106 Oscillator Failure 0x000108 Address Error 0x00010A Stack Error 0x00010C Math Error 0x00010E DMA Error 0x000110-0x000112 Reserved 0x000114 INT0 External Interrupt 0 0x000116 IC1 – ...

Page 72

... U1E UART1 Error 0x000198 U2E UART2 Error 0x00019A CRC CRC Generator Interrupt 0x00019C DMA6 DMA Channel 6 0x00019E DMA7 DMA Channel 7 0x0001A0 C1TX ECAN1 TX Data Request 0x0001A2-0x0001FE Reserved Interrupt Source © 2007-2012 Microchip Technology Inc. ...

Page 73

... Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP bits in the first position of IPC0 (IPC0<2:0>). © 2007-2012 Microchip Technology Inc. 7.3.6 STATUS/CONTROL REGISTERS Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality ...

Page 74

... U Unimplemented bit, read as 0’ Value at POR x Bit is unknown (2) Register 3-1. (1) U-0 U-0 U-0 R/C-0 (2) IPL3 -n Value at POR U Unimplemented bit, read as 0 (2) Register 3-2. U-0 U-0 R/W-0 DC bit 8 R/W-0 R/W-0 R/W bit 0 U-0 U-0 U-0 bit 8 R/W-0 U-0 U-0 PSV bit 0 1 Bit is set © 2007-2012 Microchip Technology Inc. ...

Page 75

... Stack error trap has occurred 0 Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 Oscillator failure trap has occurred 0 Oscillator failure trap has not occurred bit 0 Unimplemented: Read as 0 © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 ...

Page 76

... INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 Interrupt on negative edge 0 Interrupt on positive edge DS70293G-page 76 U-0 U-0 U-0 U-0 U-0 R/W-0 INT2EP U Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...

Page 77

... DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF ...

Page 78

... Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred DS70293G-page 78 © 2007-2012 Microchip Technology Inc. ...

Page 79

... INT1IF: External Interrupt 1 Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF ...

Page 80

... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred DS70293G-page 80 © 2007-2012 Microchip Technology Inc. ...

Page 81

... Interrupt request has occurred 0 Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred Note 1: Interrupts disabled on devices without ECAN modules. © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 ...

Page 82

... Interrupt request has occurred 0 Interrupt request has not occurred bit 12-0 Unimplemented: Read as 0 DS70293G-page 82 U-0 U-0 U-0 U-0 U-0 U-0 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 U-0 U-0 bit Bit is unknown ...

Page 83

... Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred bit 0 Unimplemented: Read as 0 Note 1: Interrupts disabled on devices without ECAN modules. © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 R/W-0 ...

Page 84

... T1IE: Timer1 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled DS70293G-page 84 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 R/W-0 R/W-0 DMA0IE T1IE OC1IE U Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown ...

Page 85

... Interrupt request enabled 0 Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 Interrupt request enabled 0 Interrupt request not enabled © 2007-2012 Microchip Technology Inc. DS70293G-page 85 ...

Page 86

... CNIE: Input Change Notification Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled DS70293G-page 86 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 R/W-0 INT1IE CNIE CMIE U Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 OC3IE DMA2IE bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown ...

Page 87

... Interrupt request enabled 0 Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled © 2007-2012 Microchip Technology Inc. DS70293G-page 87 ...

Page 88

... Interrupt request not enabled Note 1: Interrupts disabled on devices without ECAN modules. DS70293G-page 88 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 (1) (1) DMA3IE C1IE C1RXIE U Unimplemented bit, read as 0 0 Bit is cleared (1) (1) © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown ...

Page 89

... RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled bit 12-0 Unimplemented: Read as 0 © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 U-0 U-0 U-0 — ...

Page 90

... Unimplemented: Read as 0 Note 1: Interrupts disabled on devices without ECAN modules. DS70293G-page 90 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 DMA6IE CRCIE U2EIE U Unimplemented bit, read as 0 0 Bit is cleared (1) © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 R/W-0 U-0 U1EIE bit Bit is unknown ...

Page 91

... Unimplemented: Read as 0 bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled © 2007-2012 Microchip Technology Inc. R/W-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared ...

Page 92

... DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled DS70293G-page 92 R/W-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 OC2IP<2:0> bit 8 R/W-0 R/W-0 DMA0IP<2:0> bit Bit is unknown ...

Page 93

... Unimplemented: Read as 0 bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled © 2007-2012 Microchip Technology Inc. R/W-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared ...

Page 94

... Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled DS70293G-page 94 U-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 DMA1IP<2:0> bit 8 R/W-0 R/W-0 U1TXIP<2:0> bit Bit is unknown ...

Page 95

... Unimplemented: Read as 0 bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled © 2007-2012 Microchip Technology Inc. R/W-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 ...

Page 96

... Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled DS70293G-page 96 R/W-0 U-0 R/W-1 U-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 IC7IP<2:0> bit 8 R/W-0 R/W-0 INT1IP<2:0> bit Bit is unknown ...

Page 97

... Unimplemented: Read as 0 bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled © 2007-2012 Microchip Technology Inc. R/W-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 ...

Page 98

... T5IP<2:0>: Timer5 Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled DS70293G-page 98 R/W-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 U2RXIP<2:0> bit 8 R/W-0 R/W-0 T5IP<2:0> bit Bit is unknown ...

Page 99

... SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled Note 1: Interrupts disabled on devices without ECAN modules. © 2007-2012 Microchip Technology Inc. R/W-0 U-0 R/W-1 (1) R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 ...

Page 100

... Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled DS70293G-page 100 U-0 U-0 U-0 U-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 R/W-0 R/W-0 DMA3IP<2:0> bit Bit is unknown ...

Page 101

... Unimplemented: Read as 0 bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 © 2007-2012 Microchip Technology Inc. U-0 U-0 R/W-1 R/W-0 U-0 U-0 ...

Page 102

... Interrupt is priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 DS70293G-page 102 U-0 U-0 R/W-1 R/W-0 U-0 U-0 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 RTCIP<2:0> bit 8 U-0 U-0 bit Bit is unknown ...

Page 103

... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 Interrupt is priority 7 (highest priority interrupt) 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 © 2007-2012 Microchip Technology Inc. R/W-0 U-0 R/W-1 R/W-0 U-0 U-0 — Unimplemented bit, read as 0 ...

Page 104

... Interrupt is priority 1 000 Interrupt source is disabled Note 1: Interrupts disabled on devices without ECAN modules. DS70293G-page 104 U-0 U-0 R/W-1 R/W-0 U-0 R/W-1 — Unimplemented bit, read as 0 0 Bit is cleared (1) © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 (1) C1TXIP<2:0> bit 8 R/W-0 R/W-0 DMA6IP<2:0> bit Bit is unknown ...

Page 105

... Unimplemented: Read as 0 bit 6-0 VECNUM: Vector Number of Pending Interrupt bits 0111111 Interrupt Vector pending is number 135 0000001 Interrupt Vector pending is number 9 0000000 Interrupt Vector pending is number 8 © 2007-2012 Microchip Technology Inc. U-0 R-0 R-0 ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as 0 ...

Page 106

... Only user interrupts with a priority level lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. © 2007-2012 Microchip Technology Inc. ...

Page 107

... SPI2 Transfer Done ECAN1 RX Data Ready PMP Master Data Transfer ECAN1 TX Data Request © 2007-2012 Microchip Technology Inc. Direct Memory Access (DMA very efficient mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), ...

Page 108

... Alternatively, an interrupt can be generated when half of the block has been filled. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2007-2012 Microchip Technology Inc. ...

Page 109

... Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools © 2007-2012 Microchip Technology Inc. 8.2 DMAC Registers Each DMAC Channel contains the following registers: A 16-bit DMA Channel Control register (DMAxCON) • ...

Page 110

... Continuous, Ping-Pong modes enabled 01 One-Shot, Ping-Pong modes disabled 00 Continuous, Ping-Pong modes disabled DS70293G-page 110 R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as 0 0 Bit is cleared U-0 U-0 U-0 bit 8 U-0 R/W-0 R/W-0 MODE<1:0> bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 111

... DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources. © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 ...

Page 112

... DMA channel and should be avoided. DS70293G-page 112 R/W-0 R/W-0 R/W-0 STA<15:8> R/W-0 R/W-0 R/W-0 STA<7:0> Unimplemented bit, read as 0 0 Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...

Page 113

... Unimplemented: Read as 0 bit 9-0 CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers CNT<9:0> © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> R/W-0 R/W-0 R/W-0 PAD<7:0> ...

Page 114

... Write collision detected write collision detected DS70293G-page 114 R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 C Clear only bit U Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown ...

Page 115

... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 Write collision detected write collision detected © 2007-2012 Microchip Technology Inc. DS70293G-page 115 ...

Page 116

... PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 DMA0STB register selected 0 DMA0STA register selected DS70293G-page 116 U-0 R-1 R-1 LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown ...

Page 117

... R-0 bit 15 R-0 R-0 R-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2007-2012 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as 0 0 Bit is cleared R-0 R-0 bit 8 ...

Page 118

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293G-page 118 © 2007-2012 Microchip Technology Inc. ...

Page 119

... F P document F and F are used interchangeably, except in the case of Doze mode mode is used in any ratio other than 1:1, which is the default. © 2007-2012 Microchip Technology Inc. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 provides: External and internal oscillator options as clock sources and • ...

Page 120

... PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture. Instruction execution speed or device operating frequency EQUATION 9-1: described in Section 25.1 Configuration Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> Table 9-1. is divided OSC ) and the defines the given by: DEVICE OPERATING FREQUENCY F OSC F ------------- © 2007-2012 Microchip Technology Inc. ...

Page 121

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2007-2012 Microchip Technology Inc. For a primary oscillator or FRC oscillator, output F the PLL output F EQUATION 9-2: For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. • ...

Page 122

... Oscillator Source POSCMD<1:0> Internal xx Internal xx Internal xx ) Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx See FNOSC<2:0> Note 1, 2 111 110 1 1 101 1 100 011 011 1 011 010 010 010 1 1 001 000 1 © 2007-2012 Microchip Technology Inc. ...

Page 123

... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. (1,3) R-0 U-0 R/W-y — ...

Page 124

... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). DS70293G-page 124 (1,3) (CONTINUED) © 2007-2012 Microchip Technology Inc. ...

Page 125

... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as N1, PLL prescaler) 11111 Input/33 00001 Input/3 00000 Input/2 (default) Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. (2) R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> ...

Page 126

... Note 1: This register is reset only on a Power-on Reset (POR). DS70293G-page 126 (1) U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 R/W-0 PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown ...

Page 127

... OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. (2) U-0 U-0 U-0 — ...

Page 128

... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. the CF to Section 39. Oscillator © 2007-2012 Microchip Technology Inc. ...

Page 129

... Configuration. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007-2012 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have two special and power-saving modes that are entered through the ...

Page 130

... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). There are eight possible © 2007-2012 Microchip Technology Inc. ...

Page 131

... Devices.aspx?dDocNameen532315 10.5.1 KEY RESOURCES Section 9. Watchdog Timer and Power-Saving Modes (DS70196) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools © 2007-2012 Microchip Technology Inc. DS70293G-page 131 ...

Page 132

... AD1MD: ADC1 Module Disable bit 1 ADC1 module is disabled 0 ADC1 module is enabled DS70293G-page 132 R/W-0 R/W-0 U-0 T2MD T1MD R/W-0 R/W-0 U-0 SPI2MD SPI1MD — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 R/W-0 R/W-0 C1MD AD1MD bit Bit is unknown ...

Page 133

... Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 Output Compare 2 module is disabled 0 Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 Output Compare 1 module is disabled 0 Output Compare 1 module is enabled © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 U-0 R/W-0 R/W-0 — ...

Page 134

... DAC1 module is disabled 0 DAC1 module is enabled bit 5-0 Unimplemented: Read as 0 DS70293G-page 134 U-0 U-0 R/W-0 CMPMD U-0 U-0 U-0 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 RTCCMD PMPMD bit 8 U-0 U-0 bit Bit is unknown ...

Page 135

... WR Port Data Latch Read LAT Read Port © 2007-2012 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents loop through, in which a ports digital output can drive the input of a peripheral that shares the same pin. ...

Page 136

... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Example 11-1. © 2007-2012 Microchip Technology Inc. ...

Page 137

... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2007-2012 Microchip Technology Inc. 11.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it is mapped to ...

Page 138

... RPINR18 U2RX RPINR19 U2CTS RPINR19 SDI1 RPINR20 SCK1 RPINR20 SS1 RPINR21 SDI2 RPINR22 SCK2 RPINR22 SS2 RPINR23 CIRX RPINR26 © 2007-2012 Microchip Technology Inc. (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> ...

Page 139

... SDO1 SCK1 SS1 SDO2 SCK2 SS2 C1TX OC1 OC2 OC3 OC4 © 2007-2012 Microchip Technology Inc. FIGURE 11-3: U1TX Output enable 11-27). The U1RTS Output enable 4 OC4 Output U1TX Output U1RTS Output 4 OC4 Output RPn tied to default port pin 00000 RPn tied to Comparator1 Output ...

Page 140

... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. built-in C © 2007-2012 Microchip Technology Inc. ...

Page 141

... Those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. This rule applies to all of the functions listed for a given pin. © 2007-2012 Microchip Technology Inc. 11.8 I/O Ports Resources Many useful resources related to I/O Ports are provided ...

Page 142

... U Unimplemented bit, read as 0 0 Bit is cleared SS U-0 U-0 R/W-1 R/W-1 INT2R<4:0> Unimplemented bit, read as 0 0 Bit is cleared SS R/W-1 R/W-1 R/W-1 bit 8 U-0 U-0 U-0 bit Bit is unknown U-0 U-0 U-0 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 143

... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 © 2007-2012 Microchip Technology Inc. R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as 0 ...

Page 144

... Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 DS70293G-page 144 R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as 0 0 Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 145

... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 © 2007-2012 Microchip Technology Inc. R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as 0 0 Bit is cleared ...

Page 146

... Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 DS70293G-page 146 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as 0 0 Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 147

... OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin 11111 Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 © 2007-2012 Microchip Technology Inc. U-0 U-0 R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as 0 ...

Page 148

... Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 DS70293G-page 148 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as 0 0 Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 149

... U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin 11111 Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 © 2007-2012 Microchip Technology Inc. R/W-1 R/W-1 U2CTSR<4:0> R/W-1 R/W-1 U2RXR<4:0> Unimplemented bit, read as 0 0 Bit is cleared ...

Page 150

... Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 DS70293G-page 150 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as 0 0 Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 151

... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin 11111 Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 © 2007-2012 Microchip Technology Inc. U-0 U-0 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as 0 ...

Page 152

... Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 DS70293G-page 152 R/W-1 R/W-1 SCK2R<4:0> R/W-1 R/W-1 SDI2R<4:0> Unimplemented bit, read as 0 0 Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 153

... Input tied to V 11001 Input tied to RP25 00001 Input tied to RP1 00000 Input tied to RP0 Note 1: This register is disabled on devices without ECAN modules. © 2007-2012 Microchip Technology Inc. U-0 U-0 R/W-1 R/W-1 SS2R<4:0> Unimplemented bit, read as 0 ...

Page 154

... R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R<4:0> Unimplemented bit, read as 0 0 Bit is cleared R/W-0 R/W-0 R/W-0 RP3R<4:0> R/W-0 R/W-0 R/W-0 RP2R<4:0> Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...

Page 155

... Unimplemented: Read as 0 bit 12-8 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as 0 bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see peripheral function numbers) © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R<4:0> ...

Page 156

... R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R<4:0> Unimplemented bit, read as 0 0 Bit is cleared R/W-0 R/W-0 R/W-0 RP11R<4:0> R/W-0 R/W-0 R/W-0 RP10R<4:0> Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...

Page 157

... Unimplemented: Read as 0 bit 12-8 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as 0 bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see peripheral function numbers) © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R<4:0> ...

Page 158

... R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R<4:0> Unimplemented bit, read as 0 0 Bit is cleared R/W-0 R/W-0 R/W-0 RP19R<4:0> R/W-0 R/W-0 R/W-0 RP18R<4:0> Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...

Page 159

... RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as 0 bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP21R<4:0> R/W-0 R/W-0 R/W-0 RP20R<4:0> ...

Page 160

... RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. DS70293G-page 160 R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R<4:0> Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for ...

Page 161

... TCKPS<1:0> SOSCI (1) LPOSCEN Note 1: Refer to Section 9.0 Oscillator Configuration © 2007-2012 Microchip Technology Inc. The unique features of Timer1 allow used for Real Time Clock (RTC) applications. A block diagram of Timer1 is shown in The Timer1 module can operate in one of the following and modes: ...

Page 162

... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocNameen532315 12.1.1 KEY RESOURCES Section 11. Timers (DS70205) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools DS70293G-page 162 © 2007-2012 Microchip Technology Inc. ...

Page 163

... When TCS 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 External clock from pin T1CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as 0 © 2007-2012 Microchip Technology Inc. U-0 U-0 R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as 0 ...

Page 164

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293G-page 164 © 2007-2012 Microchip Technology Inc. ...

Page 165

... CY TCKPS<1:0> Prescaler Sync TxCK TCKPS<1:0> © 2007-2012 Microchip Technology Inc. A Type B timer can be concatenated with a Type C timer to form a 32-bit timer The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler ...

Page 166

... The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. Table 13-2. 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 13-3. The 32-timer module can © 2007-2012 Microchip Technology Inc. ...

Page 167

... Section 11. Timers (DS70205) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools © 2007-2012 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw TMRx TMRy ...

Page 168

... External clock from TxCK pin 0 Internal clock (F OSC bit 0 Unimplemented: Read as 0 DS70293G-page 168 U-0 U-0 R/W-0 R/W-0 TCKPS<1:0> T32 U Unimplemented bit, read as 0 0 Bit is cleared /2) U-0 U-0 U-0 bit 8 U-0 R/W-0 U-0 TCS bit Bit is unknown © 2007-2012 Microchip Technology Inc. ...

Page 169

... When 32-bit timer operation is enabled (T32 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 1) in the Timer Control register (TxCON<3>), these bits have no effect. © 2007-2012 Microchip Technology Inc. U-0 U-0 (1) ...

Page 170

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293G-page 170 © 2007-2012 Microchip Technology Inc. ...

Page 171

... Mode Sleep/Idle Wake-up Mode Note: An x’ signal, register or bit name denotes the number of the capture channel. © 2007-2012 Microchip Technology Inc. Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of ...

Page 172

... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocNameen532315 14.1.1 KEY RESOURCES Section 12. Input Capture (DS70198) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools DS70293G-page 172 © 2007-2012 Microchip Technology Inc. ...

Page 173

... Capture mode, every rising edge 010 Capture mode, every falling edge 001 Capture mode, every edge (rising and falling) (ICI<1:0> bits do not control interrupt generation for this mode) 000 Input capture module turned off © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 ...

Page 174

... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293G-page 174 © 2007-2012 Microchip Technology Inc. ...

Page 175

... TMR3 TMR2 © 2007-2012 Microchip Technology Inc. The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. and ...

Page 176

... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match © 2007-2012 Microchip Technology Inc. ...

Page 177

... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocNameen532315 15.2.1 KEY RESOURCES Section 13. Output Compare (DS70209) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools © 2007-2012 Microchip Technology Inc. DS70293G-page 177 ...

Page 178

... Initialize OCx pin low, compare event forces OCx pin high 000 Output compare channel is disabled DS70293G-page 178 U-0 U-0 U-0 R-0 HC R/W-0 R/W-0 OCFLT OCTSEL HS Set in Hardware U Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown ...

Page 179

... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2007-2012 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, analog-to-digital converters, etc ...

Page 180

... Devices.aspx?dDocNameen532315 16.2.1 KEY RESOURCES Section 18. Serial Peripheral Interface (SPI) (DS70206) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools MSTEN bit © 2007-2012 Microchip Technology Inc. ...

Page 181

... SPIRBF: SPIx Receive Buffer Full Status bit 1 Receive complete, SPIxRXB is full 0 Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2007-2012 Microchip Technology Inc. U-0 U-0 U-0 ...

Page 182

... Do not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN 1. DS70293G-page 182 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 (2) SPRE<2:0> Unimplemented bit, read as 0 0 Bit is cleared (1) (3) © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 (2) PPRE<1:0> bit Bit is unknown ...

Page 183

... The CKE bit is not used in the Framed SPI modes. Program this bit to 0 for the Framed SPI modes (FRMEN 1 not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN 1. © 2007-2012 Microchip Technology Inc. (2) (2) DS70293G-page 183 ...

Page 184

... Unimplemented: This bit must not be set to 1 by the user application DS70293G-page 184 U-0 U-0 U-0 U-0 U-0 U-0 — Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. U-0 U-0 bit 8 R/W-0 U-0 FRMDLY bit Bit is unknown ...

Page 185

... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2007-2012 Microchip Technology Inc. 17.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing. ...

Page 186

... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007-2012 Microchip Technology Inc. ...

Page 187

... Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools © 2007-2012 Microchip Technology Inc Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable ...

Page 188

... IPMIEN A10M R/W-0 HC R/W-0 HC R/W-0 HC ACKEN RCEN PEN HS Set in hardware 0 Bit is cleared 2 C pins are controlled by port functions 2 C slave slave slave) © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0 HC R/W-0 HC RSEN SEN bit Cleared in hardware x Bit is unknown ...

Page 189

... SEN: Start Condition Enable bit (when operating Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 Start condition not in progress © 2007-2012 Microchip Technology Inc master, applicable during master receive) C master, applicable during master receive) ...

Page 190

... C master, applicable to master transmit operation master, applicable to master transmit operation slave) R/C-0 HS R-0 HSC R-0 HSC BCL GCSTAT ADD10 R-0 HSC R-0 HSC R-0 HSC R_W RBF TBF C Clear only bit HSC Hardware set/cleared x Bit is unknown 2 C module is busy © 2007-2012 Microchip Technology Inc. bit 8 bit 0 ...

Page 191

... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 Transmit in progress, I2CxTRN is full 0 Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2007-2012 Microchip Technology Inc slave device address byte. DS70293G-page 191 ...

Page 192

... Enable masking for bit x of incoming message address; bit match not required in this position 0 Disable masking for bit x; bit match required in this position DS70293G-page 192 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U Unimplemented bit, read as 0 0 Bit is cleared © 2007-2012 Microchip Technology Inc. R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown ...

Page 193

... Note 1: Both UART1 and UART2 can trigger a DMA data transfer DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> and URXISEL<1:0> 00). © 2007-2012 Microchip Technology Inc. The primary features of the UART module are: Full-Duplex 9-bit Data Transmission through the UxTX and UxRX pins • ...

Page 194

... URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocNameen532315 18.2.1 KEY RESOURCES Section 17. UART (DS70188) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections Development Tools © 2007-2012 Microchip Technology Inc. ...

Page 195

... Baud rate measurement disabled or completed Note 1: Refer to Section 17. UART (DS70232) in the dsPIC33F/PIC24H Family Reference Manual for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH 0). © 2007-2012 Microchip Technology Inc. MODE REGISTER x R/W-0 R/W-0 U-0 ...

Page 196

... Refer to Section 17. UART (DS70232) in the dsPIC33F/PIC24H Family Reference Manual for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH 0). DS70293G-page 196 MODE REGISTER (CONTINUED) x © 2007-2012 Microchip Technology Inc. ...

Page 197

... Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer. Receive buffer has one or more characters Note 1: Refer to Section 17. UART (DS70232) in the dsPIC33F/PIC24H Family Reference Manual for information on enabling the UART module for transmit operation. © 2007-2012 Microchip Technology Inc. STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — ...

Page 198

... Receive buffer has data, at least one more character can be read 0 Receive buffer is empty Note 1: Refer to Section 17. UART (DS70232) in the dsPIC33F/PIC24H Family Reference Manual for information on enabling the UART module for transmit operation. DS70293G-page 198 STATUS AND CONTROL REGISTER (CONTINUED) x © 2007-2012 Microchip Technology Inc. ...

Page 199

... CAN system. The CAN specifi- cation is not covered within this data sheet. The reader can refer to the BOSCH CAN specification for further details. © 2007-2012 Microchip Technology Inc. The module features are as follows: Implementation of the CAN protocol, CAN 1.2, CAN 2.0A and CAN 2.0B • ...

Page 200

... A node can generate a maxi- mum of 2 sequential overload frames to delay the start of the next message. Interframe Space: Interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. DS70293G-page 200 © 2007-2012 Microchip Technology Inc. ...

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