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PIC12F617 Datasheet

Download or read online Microchip Technology PIC12F617 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers pdf datasheet.



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PIC12F609/615/617
PIC12HV609/615
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
 2010 Microchip Technology Inc.
DS41302D

Summary of Contents

Page 1

... Devices Protected by Microchips Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. 2010 Microchip Technology Inc. PIC12F609/615/617 PIC12HV609/615 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41302D ...

Page 2

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U ...

Page 3

... Multiplexed Master Clear with Pull-up/Input Pin Programmable Code Protection High Endurance Flash: - 100,000 write Flash endurance - Flash retention: > 40 years Self Read/ Write Program Memory (PIC12F617 only) Low-Power Features: Standby Current 2.0V, typical Operating Current  ...

Page 4

... Data Memory Memory Device Flash SRAM (bytes) (words) PIC12F609 1024 64 PIC12HV609 1024 64 PIC12F615 1024 64 PIC12HV615 1024 64 PIC12F617 2048 128 8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN) GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/V TABLE 1: PIC12F609/HV609 PIN SUMMARY ( I/O Pin Comparators GP0 7 CIN GP1 6 CIN0- GP2 ...

Page 5

... CIN1- GP5 2 1 8 Alternate pin function. Note 1: Input only. 2: Only when pin is configured for external MCLR. 2010 Microchip Technology Inc GP0/AN0/CIN/P1B/ICSPDAT 2 7 PIC12F615/ 617/HV615 GP1/AN1/CIN0-/ GP2/AN2/T0CKI/INT/COUT/CCP1/P1A PDIP, SOIC, MSOP, DFN ...

Page 6

... PIC12F609/615/617/12HV609/615 Table of Contents 1.0 Device Overview ... 7 2.0 Memory Organization ... 11 3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only)... 27 4.0 Oscillator Module ... 37 5.0 I/O Port ... 43 6.0 Timer0 Module ... 53 7.0 Timer1 Module with Gate Control ... 57 8.0 Timer2 Module (PIC12F615/617/HV615 only) ... 65 9.0 Comparator Module ... 67 10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) ... 79 11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ... 89 12 ...

Page 7

... OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator Block T1G T1CKI Timer0 T0CKI 2010 Microchip Technology Inc. Block Diagrams and pinout descriptions of the devices are as follows: PIC12F609/HV609 (Figure 1-1, Table 1-1) PIC12F615/617/HV615 (Figure 1-2, Table 1-2) INT 13 Data Bus Program Counter RAM 8-Level Stack ...

Page 8

... Timing Generation OSC2/CLKOUT Internal Oscillator T1G Block T1G T1CKI Timer0 T0CKI Analog-To-Digital Converter Alternate pin function. For the PIC12F617 only. DS41302D-page 8 INT 13 Data Bus Program Counter RAM 64 Bytes and 8-Level Stack 128 Bytes (13-Bit) File Registers RAM Addr 9 Addr MUX ...

Page 9

... T1CKI OSC1 CLKIN Legend: ANAnalog input or output STSchmitt Trigger input with CMOS levels 2010 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change AN Comparator non-inverting input ST CMOS ...

Page 10

... PWM output, alternate pin OSC1 XTAL Crystal/Resonator CLKIN ST External clock input/RC oscillator connection V Power Positive supply DD V Power Ground reference SS CMOSCMOS compatible input or output TTL TTL compatible input Description HV High Voltage XTALCrystal 2010 Microchip Technology Inc. ...

Page 11

... Accessing a location above these boundaries will cause a wrap-around within the first space for PIC12F609/615/12HV609/615 devices, and within the first space for the PIC12F617 device. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: ...

Page 12

... GENERAL PURPOSE REGISTER FILE The register file is organized the PIC12F609/615/12HV609/615, and as 128 the PIC12F617. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 Indirect Addressing, INDF and FSR Registers). 2.2.2 SPECIAL FUNCTION REGISTERS ...

Page 13

... Bytes 6Fh 70h Accesses 70h-7Fh Accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as 0. Note 1: Not a physical register. 2: Used for the PIC12F617 only. 2010 Microchip Technology Inc. File Address (1) 80h 81h 82h 83h 84h 85h 86h 87h ...

Page 14

... VR1 VR0 0-00 0000 76, 116 CMCH 0000 -0-0 72, 116 T1GSS CMSYNC ---0 0-10 73, 116 2010 Microchip Technology Inc. ...

Page 15

... Unimplemented locations read as 0’ unchanged unknown value depends on condition, shaded unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: Read only register. 3: PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO PD ...

Page 16

... WPU1 WPU0 --11 -111 46, 116 IOC1 IOC0 --00 0000 46, 116 ANS1 ANS0 ---- 1-11 45, 117 2010 Microchip Technology Inc. ...

Page 17

... MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. 4: TRISIO3 always reads as 1 since input only pin. 5: Read only register. 6: PIC12F615/617/HV615 only. 7: PIC12F617 only. 2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE PSA ...

Page 18

... The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R-1 R Unimplemented bit, read as 0 0 Bit is cleared (ADDWF, ADDLW, SUBLW, SUBWF instructions) R/W-x R/W-x R/W bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 19

... TIMER0 RATE WDT RATE 000 001 010 011 100 101 110 111 2010 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to 1 of the OPTION register. See Section 6.1.3 Software Programmable Prescaler. R/W-1 R/W-1 ...

Page 20

... Enable bit, GIE of the INTCON register. User software appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 INTE GPIE T0IF U Unimplemented bit, read as 0 0 Bit is cleared (1) (2) should ensure the R/W-0 R/W-0 INTF GPIF bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 21

... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as 0. 2010 Microchip Technology Inc. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...

Page 22

... Enable bit, GIE of the INTCON register. User appropriate interrupt flag bits are clear prior to enabling an interrupt. U-0 R/W-0 (1) CMIF U Unimplemented bit, read as 0 0 Bit is cleared (1) (1) (1) software should ensure the U-0 R/W-0 R/W-0 (1) TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 23

... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as 0 if Brown-out Reset is disabled. 2010 Microchip Technology Inc. U-0 U-0 U-0 ...

Page 24

... P1A function is on GP5/T1CKI/P1A 0 P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A Note 1: PIC12F615/617/HV615 only. 2: Alternate pin function. DS41302D-page 24 (1) R/W-0 U-0 U-0 T1GSEL — Unimplemented bit, read as 0 0 Bit is cleared (2) /MCLR/V PP (2) /OSC2/CLKOUT (2) /OSC2/CLKOUT (2) /OSC1/CLKIN R/W-0 R/W-0 P1BSEL P1ASEL bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 25

... For more information refer to Application Note AN556, Implementing a Table Read (DS00556). 2010 Microchip Technology Inc. 2.3.2 STACK The PIC12F609/615/617/12HV609/615 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). ...

Page 26

... Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in this area are mirrored back into Bank 0 and Bank 1. DS41302D-page 26 0 IRP Bank Select 180h (2) NOT USED Bank 1 Bank 2 Bank 3 Indirect Addressing ( File Select Register Location Select 1FFh 2010 Microchip Technology Inc. ...

Page 27

... PIC12F609/615/617/12HV609/615 3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY) The Flash program memory is readable and writable during normal operation (full V range). This memory DD is not directly mapped in the register file space. Instead indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5). There are six SFRs used to read and write this memory: • ...

Page 28

... PMADRH2 U Unimplemented bit, read as 0 0 Bit is cleared R/W-0 R/W-0 PMDATL1 PMDATL0 bit Bit is unknown R/W-0 R/W-0 PMADRL1 PMADRL0 bit Bit is unknown R/W-0 R/W-0 PMDATH1 PMDATH0 bit Bit is unknown R/W-0 R/W-0 PMADRH1 PMADRH0 bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 29

... Initiates a program memory read (The read takes one cycle. The RD is cleared in hardware; the RD bit can only be set (not cleared) in software Does not initiate a Flash memory read Legend Readable bit W Writable bit -n Value at POR 1 bit is set 2010 Microchip Technology Inc. U-0 U-0 R/W-0 WREN U Unimplemented bit, read as 0 ...

Page 30

... First instruction after BSF PMCON1,RD executes normally NOP ; Any instructions here are ignored as program ; memory is read in second cycle after BSF PMCON1,RD ; BANKSEL PMDATL ; Bank to containing PMADRL MOVF PMDATL Byte of Program PMDATL MOVF PMDATH Byte of Program PMDATL DS41302D-page 30 BSF 2010 Microchip Technology Inc. ...

Page 31

... Flash ADDR Flash DATA INSTR (PC) BSF PMCON1,RD INSTR ( Executed here Executed here RD bit PMDATH PMDATL Register PMRHLT 2010 Microchip Technology Inc. PMADRH,PMADRL PC3 INSTR ( PMDATH,PMDATL INSTR ( INSTR ( NOP Executed here Executed here INSTR ( ...

Page 32

... CPU can read and execute from the program memory. The portions of program memory that are write pro- tected can be modified by the CPU using the PMCON registers, but the protected program memory cannot be modified using ICSP mode. 2010 Microchip Technology Inc. ...

Page 33

... Flash read ( (PC) DATA BSF PMCON1,WR INSTR ( Executed here Executed here Flash Memory Location WR bit PMWHLT 2010 Microchip Technology Inc PMDATH PMDATL 6 14 PMADRL<1:0> Buffer Register Buffer Register Program Memory PMADRH,PMADRL ...

Page 34

... Increment address ANDLW 0x03 ; Indicates when sixteen words have been programmed SUBLW 0x03 ; ; ; ; BTFSS STATUS,Z ; Exit on a match, GOTO LOOP ; Continue if more data needs to be written DS41302D-page 34 Required Sequence 0x0F 16 words 0x0B 12 words 0x07 8 words 0x03 4 words 2010 Microchip Technology Inc. ...

Page 35

... PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATH PMDATH5 Legend unknown unchanged, unimplemented read as 0’ value depends upon condition. Shaded cells are not used by Program Memory module. 2010 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 WREN WR PMADRL4 ...

Page 36

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 36 2010 Microchip Technology Inc. ...

Page 37

... MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator OSC2 Sleep OSC1 Internal Oscillator INTOSC 8 MHz 2010 Microchip Technology Inc. The Oscillator module can be configured in one of eight clock modes External clock with I/O on OSC2/CLKOUT 32 kHz Low-Power Crystal mode Medium Gain Crystal or Ceramic Resonator Oscillator mode ...

Page 38

... These oscillator delays are shown in Table 4-1. Frequency Oscillator Delay 125 kHz to 8 MHz Oscillator Warm-Up Delay (T DC 20 MHz 2 instruction cycles 32 kHz to 20 MHz 1024 Clock Cycles (OST) (1) ) WARM 2010 Microchip Technology Inc. ...

Page 39

... The value of R varies with the Oscillator mode F selected (typically between 2 M M. 2010 Microchip Technology Inc. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...

Page 40

... The CLKOUT Internal signal may be used to provide a clock for external Clock circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. ) values EXT See Section 12.0 Special 2010 Microchip Technology Inc. ...

Page 41

... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 12-1) for operation of all register bits. 2010 Microchip Technology Inc. The default value of the OSCTUNE register is 0. The value is a 5-bit twos complement number. ...

Page 42

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 42 2010 Microchip Technology Inc. ...

Page 43

... GPIO pin is > GPIO pin is < 2010 Microchip Technology Inc. Reading the GPIO register (Register 5-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘ ...

Page 44

... Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. Note change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. R/W-1 R/W-1 TRISIO1 TRISIO0 bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 45

... Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on- change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2010 Microchip Technology Inc. U-0 R/W-1 U-0 ...

Page 46

... WPU4 WPU2 U Unimplemented bit, read as 0 0 Bit is cleared (3) R/W-0 R/W-0 R/W-0 IOC4 IOC3 IOC2 U Unimplemented bit, read as 0 0 Bit is cleared R/W-1 R/W-1 WPU1 WPU0 bit Bit is unknown R/W-0 R/W-0 IOC1 IOC0 bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 47

... Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. 5.2.4.2 Figure 5-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: a general purpose I/O an analog input for the ADC • ...

Page 48

... DS41302D-page 48 Note 1: PIC12F615/617/HV615 only. (1) Analog Input Mode C1OE Enable C1OE (1) Analog Input Mode GPIO To Timer0 To INT (3) To A/D Converter ( Weak GPPU V DD I/O Pin 2010 Microchip Technology Inc. ...

Page 49

... BLOCK DIAGRAM OF GP3 Data Bus RD TRISIO RD GPIO WR IOC RD IOC ( Interrupt-on- Change R Write 0 to GBIF Note 1: Set has priority over Reset 2010 Microchip Technology Inc. PP (1, 2) MCLRE Reset From other GP<5:4, 2:0> pins V DD Weak MCLRE Input Pin ...

Page 50

... OSC1 CLKOUT Enable F /4 OSC CLKOUT Enable D Q INTOSC/ (2) RC/ CLKOUT Enable Analog Input Mode From other GP<5, 3:0> pins RD GPIO To T1G (5) To A/D Converter ( Weak V DD I/O Pin 2010 Microchip Technology Inc. ...

Page 51

... FIGURE 5-5: BLOCK DIAGRAM OF GP5 ( Interrupt-on- Change R Write 0 to GBIF Note 1: Timer1 LP Oscillator enabled. 2: Set has priority over Reset. 2010 Microchip Technology Inc. Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only. INTOSC Mode Data Bus WPU ...

Page 52

... CMCH 0000 -0-0 0000 -0-0 GPIF 0000 0000 0000 0000 IOC0 --00 0000 --00 0000 PS0 1111 1111 1111 1111 GP0 --xx xxxx --u0 u000 TRISIO0 --11 1111 --11 1111 WPU0 --11 1111 --11 -111 TMR1ON 0000 0000 uuuu uuuu CCP1M0 0-00 0000 0-00 0000 P1ASEL ---0 --00 ---0 --00 2010 Microchip Technology Inc. ...

Page 53

... Watchdog WDTE Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. 2010 Microchip Technology Inc. 6.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...

Page 54

... T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 16.0 Electrical Specifications. 2010 Microchip Technology Inc. ...

Page 55

... TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 Legend: Unimplemented locations, read as 0’ unchanged unknown. Shaded cells are not used by the Timer0 module. 2010 Microchip Technology Inc. R/W-1 R/W-1 T0SE PSA U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 56

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 56 2010 Microchip Technology Inc. ...

Page 57

... When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. 2010 Microchip Technology Inc. 7.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS 0, the clock source ...

Page 58

... PIC12F615/617/HV615 only. DS41302D-page 58 TMR1ON To Comparator Module Timer1 Clock ( TMR1L 1 (1) T1SYNC 1 Prescaler T1CKPS<1:0> TMR1CS F OSC OSC 0 Internal T1GSEL Clock T1ACS TMR1GE T1GINV Synchronized clock input (3) Synchronize det COUT 0 (2) T1GSS 2010 Microchip Technology Inc. ...

Page 59

... Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. 2010 Microchip Technology Inc. 7.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks ...

Page 60

... In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only). 2010 Microchip Technology Inc. ...

Page 61

... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010 Microchip Technology Inc. For more information, see Section 11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only). ...

Page 62

... TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register Timer1 gate source. 3: See T1ACS bit in CMCON1 register. DS41302D-page 62 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U Unimplemented bit, read as 0 0 Bit is cleared (1) (2) (3) /4) or system clock (F ) OSC R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 63

... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged unimplemented, read as 0. Shaded cells are not used by the Timer1 module. Note 1: PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 T1GSEL P1BSEL CMPOL — ...

Page 64

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 64 2010 Microchip Technology Inc. ...

Page 65

... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> 2010 Microchip Technology Inc. The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a 1. Timer2 is turned off by clearing the TMR2ON bit to a ‘ ...

Page 66

... T2CKPS1 T2CKPS0 bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets GPIF 0000 0000 0000 0000 (1) TMR1IE -00- 0-00 -00- 0-00 (1) TMR1IF -00- 0-00 -00- 0-00 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 2010 Microchip Technology Inc. ...

Page 67

... REF MUX CV REF 1 CMV REN Note 2010 Microchip Technology Inc. than the analog voltage at V comparator is a digital low level. When the analog voltage the output of the comparator is a digital high level. IN FIGURE 9-1:SINGLE COMPARATOR ...

Page 68

... V . The SS and Analog levels on any pin defined digital input, may cause the input buffer to consume more current than is specified. inaccuracies V DD 0. LEAKAGE 0. ±500 Comparator 2010 Microchip Technology Inc. ...

Page 69

... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2010 Microchip Technology Inc. 9.3.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register ...

Page 70

... Allow about 1 s for bias settling then clear the mismatch condition and interrupt comparator interrupts. COMPARATOR INTERRUPT TIMING W/O CMCON0 READ T RT reset by software COMPARATOR INTERRUPT TIMING WITH CMCON0 READ T RT reset by software an invalid output from the flags before enabling 2010 Microchip Technology Inc. ...

Page 71

... INTCON register is also set, the device will then execute the Interrupt Service Routine. 9.7 Effects of a Reset A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state. 2010 Microchip Technology Inc. Electrical DS41302D-page 71 ...

Page 72

... Comparator output requires the following three conditions: CMOE 1, CMON 1 and corresponding port TRIS bit 0. DS41302D-page 72 R/W-0 U-0 CMPOL — Unimplemented bit, read as 0 0 Bit is cleared > CMV - < CMV - > CMV - < CMV - IN IN (1) output REF R/W-0 U-0 R/W-0 CMR CMCH bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 73

... Output is synchronized with falling edge of Timer1 clock 0 Output is asynchronous Note 1: Refer to Section 7.6 Timer1 Gate. 2: Refer to Figure 9-2. 2010 Microchip Technology Inc. 9.9 Synchronizing Comparator Output to Timer1 The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source ...

Page 74

... When the CMVREN bit is cleared, current flow in the CV voltage divider is disabled minimizing the power REF drain of the voltage reference peripheral. SS module current. REF derived and DD output changes with fluctuations in REF , with DD or fixed REF voltage divider REF voltage for use by the Compar- REF 2010 Microchip Technology Inc. ...

Page 75

... COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CMVREN (1) CV REF To Comparators and ADC Module FixedRef To Comparators and ADC Module Note 1: Care should be taken to ensure CV Section 16.0 Electrical Specifications for more detail. 2010 Microchip Technology Inc. 16 Stages Analog MUX 15 0 (1) VR<3:0> 0.6V Fixed Voltage Reference remains within the comparator common mode input range ...

Page 76

... Bit is cleared (1, 2) input of the Comparator REF input of the Comparator REF (2) Value Selection bits (0 VR<3:0> 15) REF (VR<3:0>/24 (VR<3:0>/32 circuit is powered down and does not contribute to I REF R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown current. DD 2010 Microchip Technology Inc. ...

Page 77

... Hysteresis) Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time. 2010 Microchip Technology Inc. Figure 9-7 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis. The output of the comparator ...

Page 78

... POR, BOR Resets ANS0 -000 1111 -000 1111 CMCH 0000 -000 0000 -000 CMSYNC 0000 0000 0000 0000 GPIF 0000 000x 0000 000x TMR1IE -00- 0-00 -00- 0-00 TMR1IF -00- 0-00 -00- 0-00 GP0 --xx xxxx --uu uuuu TRISIO0 --11 1111 --11 1111 VR0 0-00 0000 0-00 0000 2010 Microchip Technology Inc. ...

Page 79

... Figure 10-1 shows the block diagram of the ADC. FIGURE 10-1: ADC BLOCK DIAGRAM GP0/AN0 GP1/AN1/V REF GP2/AN2 GP4/AN3 CV REF 0.6V Reference 1.2V Reference 2010 Microchip Technology Inc. Note: The ADRESL and ADRESH registers are Read Only. (ADC) allows V DD VCFG 0 V REF VCFG 1 000 ...

Page 80

... Section 16.0 Electrical Specifications for more information. Table 10-1 gives examples of appropriate ADC clock selections. Note: Unless using the F , any changes in the RC system clock frequency will change the ADC clock frequency, adversely affect the ADC result. 2010 Microchip Technology Inc. periods AD specification AD which may ...

Page 81

... Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 10.1.5 Interrupts for more information. 2010 Microchip Technology Inc DEVICE OPERATING FREQUENCIES (VDD > 3.0V Device Frequency (F ...

Page 82

... ADC timing requirements are met. See Section 11.0 Enhanced Capture/Compare/ PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) for more information. ADRESL bit 0 Unimplemented: Read as 0 LSB bit 0 RC clock source is selected, the RC 2010 Microchip Technology Inc. ...

Page 83

... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 10.3 A/D Acquisition Requirements. 2010 Microchip Technology Inc. EXAMPLE 10-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ...

Page 84

... If the Comparator module uses this 0.6V reference voltage, the comparator output may momentarily change state due to the transient. DS41302D-page 84 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U Unimplemented bit, read as 0 0 Bit is cleared R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 85

... ADRES5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result 2010 Microchip Technology Inc. R-x R-x R-x ADRES6 ADRES5 ADRES4 U Unimplemented bit, read as 0 0 Bit is cleared U-0 ...

Page 86

... HOLD 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED 2010 Microchip Technology Inc. ...

Page 87

... SS Sampling Switch C Sample/Hold Capacitance HOLD FIGURE 10-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h 003h 002h 001h 000h REF 2010 Microchip Technology Inc Sampling Switch V 0.6V T  Rss LEAKAGE V 0.6V T ± 500 ...

Page 88

... POR, BOR Resets ADON 00-0 0000 00-0 0000 ANS0 -000 1111 -000 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GP0 --x0 x000 --x0 x000 GPIF 0000 0000 0000 0000 (1) TMR1IE -00- 0-00 -00- 0-00 (1) TMR1IF -00- 0-00 -00- 0-00 TRISIO0 --11 1111 --11 1111 2010 Microchip Technology Inc. ...

Page 89

... P1A active-high; P1B active-low 1110 PWM mode; P1A active-low; P1B active-high 1111 PWM mode; P1A active-low; P1B active-low 2010 Microchip Technology Inc. event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. ...

Page 90

... NEW_CAPT_PS ;Load the W reg with CCPR1L MOVWF CCP1CON TMR1L of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value 2010 Microchip Technology Inc. ...

Page 91

... Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISIO TRISIO5 Legend Unimplemented locations, read as 0’ unchanged unknown. Shaded cells are not used by the Capture. Note 1: For PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000 ...

Page 92

... CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. the match condition by 2010 Microchip Technology Inc. ...

Page 93

... TMR2 Timer2 Module Register TRISIO TRISIO5 Legend Unimplemented locations, read as 0’ unchanged unknown. Shaded cells are not used by the Compare. Note 1: For PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 INTE ...

Page 94

... In PWM mode, CCPR1H is a read-only register. DS41302D-page 94 The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 11-4: Period Pulse Width TMR2 0 CCP1 TRIS ), or OSC CCP PWM OUTPUT TMR2 PR2 TMR2 CCPRxL:CCPxCON<5:4> 2010 Microchip Technology Inc. ...

Page 95

... PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 2010 Microchip Technology Inc. EQUATION 11-2: Pulse Width EQUATION 11-3: OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation ...

Page 96

... Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). Enable the CCP1 pin output driver by clearing the associated TRIS bit. 2010 Microchip Technology Inc. ...

Page 97

... EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode Single Half-Bridge 2010 Microchip Technology Inc. The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately ...

Page 98

... Delay (PWM1CON<6:0>) P1C Inactive OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 Programmable Dead-Band Delay mode). P1D Modulated DS41302D-page 98 Pulse 0 Width Period (1) (1) Delay Delay Pulse 0 Width Period (1) (1) Delay Delay 2010 Microchip Technology Inc. PR21 PR21 ...

Page 99

... Standard Half-Bridge Circuit (Push-Pull) Half-Bridge Output Driving a Full-Bridge Circuit P1A P1B 2010 Microchip Technology Inc. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. ...

Page 100

... When the device is placed in sleep, the allocated timer will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. DS41302D-page 100 2010 Microchip Technology Inc. ...

Page 101

... From Comparator 001 000 2010 Microchip Technology Inc. A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a 0, the PWM pins are operating normally. If the bit is a 1, the PWM outputs are in the shutdown state ...

Page 102

... PWM signal will always restart at the beginning of the next PWM period. DS41302D-page 102 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U Unimplemented bit, read as 0 0 Bit is cleared (1) condition R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown 2010 Microchip Technology Inc. ...

Page 103

... ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 11-12: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period 2010 Microchip Technology Inc. PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Period Shutdown Shutdown Event Occurs Event Clears ...

Page 104

... Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high OSC V FET Driver P1A FET Driver P1B V- EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period Period td (1) ( Load V - 2010 Microchip Technology Inc. ...

Page 105

... Timer2 Module Register TRISIO TRISIO5 Legend Unimplemented locations, read as 0’ unchanged unknown. Shaded cells are not used by the PWM. Note 1: For PIC12F615/617/HV615 only. 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC4 PDC3 PDC2 U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 106

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 106 2010 Microchip Technology Inc. ...

Page 107

... The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1). 2010 Microchip Technology Inc. 12.1 Configuration Bits The Configuration bits can be programmed (read as ‘ ...

Page 108

... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41302D-page 108 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 (1) (2) (3) IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 P Programmable 0 Bit is cleared (1) (3) DD R/P-1 R/P-1 R/P-1 R/P-1 bit Unimplemented bit, read as 0’ Bit is unknown 2010 Microchip Technology Inc. ...

Page 109

... PIC12F609/615/617/12HV609/615 REGISTER 12-2: CONFIG CONFIGURATION WORD (ADDRESS: 2007h) FOR PIC12F617 ONLY U-1 U-1 R/P-1 R/P-1 R/P-1 WRT1 WRT0 BOREN1 BOREN0 IOSCFS bit 13 bit 13-12 Unimplemented: Read as 1 bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bits 11 Write protection off 10 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON1 control 01 000h to 3FFh write protected, 400h to 7FFh may be modified by PMCON1 control 00 000h to 7FFh write protected, entire program memory is write protected ...

Page 110

... A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 16.0 Electrical Specifications for pulse-width specifications. Enable PWRT Enable OST S Chip_Reset R Q 2010 Microchip Technology Inc. ...

Page 111

... MCLRE bit in the Configuration Word register. When MCLRE 0, the Reset signal to the chip is generated internally. When the MCLRE 1, the GP3/MCLR pin becomes an external Reset input. In this mode, the GP3/MCLR pin has a weak pull- 2010 Microchip Technology Inc. FIGURE 12- This DD ...

Page 112

... Brown-out Reset BOR and the Power-up Timer will be re-initialized. Once V rises above V BOR Reset. falls & rises DD while the Power-up Timer is BOR DD , the Power-up Timer will execute a V BOR V BOR V BOR 2010 Microchip Technology Inc. ...

Page 113

... Legend unchanged unknown, unimplemented bit, reads as 0’ value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2010 Microchip Technology Inc. 12.3.6 POWER CONTROL (PCON) REGISTER ...

Page 114

... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS41302D-page 114 T PWRT T OST T PWRT T OST ) DD T PWRT T OST 2010 Microchip Technology Inc. ...

Page 115

... See Table 12-6 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit 2010 Microchip Technology Inc. Wake-up from Sleep through MCLR Reset WDT Reset Wake-up from Sleep through ...

Page 116

... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-6 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit For PIC12F617 only. DS41302D-page 116 Wake-up from Sleep through MCLR Reset WDT Reset Wake-up from Sleep through ...

Page 117

... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-6 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit For PIC12F617 only. TABLE 12-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation ...

Page 118

... Timer2 Match Interrupt (PIC12F615/617/HV615 only) Enhanced CCP Interrupt (PIC12F615/617/HV615 only) Flash Memory Self Write (PIC12F617 only) The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. ...

Page 119

... ADIF (615/617 only) ADIE CCP1IF (615/617 only) CCP1IE 2010 Microchip Technology Inc. 12.4.3 GPIO INTERRUPT-ON-CHANGE An input change on GPIO sets the GPIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the GPIE bit of the INTCON register. Plus, individual pins can be configured through the IOC register ...

Page 120

... TMR2IE 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) instruction cycle time. Latency CY . Value on Value on Bit 0 all other POR, BOR Resets GPIF 0000 0000 0000 0000 IOC0 --00 0000 --00 0000 TMR1IF -00- 0-00 -000 0-00 TMR1IE -00- 0-00 -000 0-00 2010 Microchip Technology Inc. ...

Page 121

... The WDT can be permanently disabled by program- ming the Configuration bit, WDTE, (Section 12.1 Configuration Bits). 2010 Microchip Technology Inc. and 12.6.1 WDT PERIOD The WDT has a nominal time-out period (with no prescaler). The time-out periods vary with temperature, V and process variations from part to DD part (see DC specs) ...

Page 122

... FOSC1 Data Bus 8 SYNC 2 TMR0 Cycles Set Flag bit T0IF on Overflow WDT Time-Out WDT Cleared Cleared until the end of OST Value on Value on Bit 0 all other POR, BOR Resets PS0 1111 1111 1111 1111 FOSC0 2010 Microchip Technology Inc. ...

Page 123

... External Interrupt from INT pin. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. 2010 Microchip Technology Inc. When the SLEEP instruction is being executed, the next instruction ( prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...

Page 124

... Only the Least Significant 7 bits of the ID locations are used. DS41302D-page 124 OST (2) T (3) Interrupt Latency Processor in Sleep Inst( Dummy Cycle Inst( not been for more 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) 2010 Microchip Technology Inc. ...

Page 125

... GP0 becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 12-10. FIGURE 12-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External PIC12F617/ Connector PIC12F615/12HV615 Signals PIC12F609/12HV609 ...

Page 126

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 126 2010 Microchip Technology Inc. ...

Page 127

... See Figure 13-1 for voltage regulator schematic. FIGURE 13-1: VOLTAGE REGULATOR V UNREG R SER I SUPPLY I SHUNT C Feedback BYPASS Device 2010 Microchip Technology Inc. An external current limiting resistor, R between the unregulated supply, V pin, drops the difference in voltage between V and SER defined by Equation 13- EQUATION 13-1: supply current R MAX ...

Page 128

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 128 2010 Microchip Technology Inc. ...

Page 129

... For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended consequence of clearing the condition that set the GPIF flag. 2010 Microchip Technology Inc. TABLE 14-1: OPCODE FIELD DESCRIPTIONS Field ...

Page 130

... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk 2010 Microchip Technology Inc. ...

Page 131

... Status Affected: Z Description: AND the W register with register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 2010 Microchip Technology Inc. BCF Syntax: k Operands: Operation: Status Affected: ...

Page 132

... Operands: d [0,1] ( (destination) Operation: Status Affected: Z Description: Decrement register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 2010 Microchip Technology Inc. ...

Page 133

... Description: The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. 2010 Microchip Technology Inc. INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0 f 127 Operands: d  ...

Page 134

... MOVWF f 0 f 127 (W) (f) None Move data from W register to register f’ MOVW OPTION F Before Instruction OPTION 0xFF W 0x4F After Instruction OPTION 0x4F W 0x4F No Operation [ label ] NOP None No operation None No operation NOP 2010 Microchip Technology Inc. ...

Page 135

... Interrupt Enable bit, GIE (INT- CON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC TOS GIE 1 2010 Microchip Technology Inc. RETLW Return with literal in W Syntax: [ label ] RETLW k 0 k 255 Operands: k (W); Operation: TOS PC Status Affected: None Description: The W register is loaded with the eight-bit literal ‘ ...

Page 136

... The W register is subtracted (2s complement method) from the eight-bit literal k. The result is placed in the W register. Result Condition W   W<3:0> k<3:0> W<3:0> k<3:0> 2010 Microchip Technology Inc. ...

Page 137

... Operation: Status Affected: Z Description: The contents of the W register are XORed with the eight-bit literal k. The result is placed in the W register. 2010 Microchip Technology Inc. XORWF Exclusive OR W with f Syntax: [ label ] XORWF 0 f 127 Operands: d [0,1] (W) .XOR. (f) destination) ...

Page 138

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 138 2010 Microchip Technology Inc. ...

Page 139

... PICkit 3 Debug Express Device Programmers - PICkit 2 Programmer - MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 2010 Microchip Technology Inc. 15.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

Page 140

... Support for the entire device instruction set ® standard HEX Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 2010 Microchip Technology Inc. ...

Page 141

... Microchip Technology Inc. 15.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...

Page 142

... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® 2010 Microchip Technology Inc. ...

Page 143

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2010 Microchip Technology Inc. ... -0. ) ...

Page 144

... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 16-2: PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH, -40° 125° 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41302D-page 144 8 10 Frequency (MHz Frequency (MHz 2010 Microchip Technology Inc. ...

Page 145

... Note 1: This is the limit to which User defined. Voltage across the shunt regulator should not exceed 5V. 2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40° C T -40° C T Min Typ Max Units 2.0 — ...

Page 146

... XT Oscillator mode MHz OSC XT Oscillator mode MHz OSC EC Oscillator mode MHz OSC EC Oscillator mode MHz OSC INTOSC mode MHz OSC INTOSC mode MHz OSC (3) EXTRC mode MHz OSC HS Oscillator mode 2010 Microchip Technology Inc. ...

Page 147

... For RC oscillator configurations, current through R be extended by the formula I 2010 Microchip Technology Inc. -40° C T 85° C for industrial A -40° C T  ...

Page 148

... T1OSC disabled 40° C T 25° C for industrial - A (1) WDT Current (1) BOR Current (1) Comparator Current , single comparator enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress 2010 Microchip Technology Inc. ...

Page 149

... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V 2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40° C T 125° C for extended ...

Page 150

... Note WDT, BOR, Comparator, V and REF T1OSC disabled (1) WDT Current (1) BOR Current (1) Comparator Current , single comparator enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress 2010 Microchip Technology Inc. ...

Page 151

... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied Shunt regulator is always on and always draws operating current. 2010 Microchip Technology Inc. -E (Extended) -40° C T 125° C for extended ...

Page 152

... This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled. 5: This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. 6: Applies to PIC12F617 only. DS41302D-page 152 PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) Standard Operating Conditions (unless otherwise stated) -40° ...

Page 153

... This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. 6: Applies to PIC12F617 only. 2010 Microchip Technology Inc. PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) -40° ...

Page 154

... DFN 3x3mm package 3.0 C/W 8-pin DFN 4x4mm package 150 C — INTERNAL — INTERNAL DD (NOTE 1) (I — — DER MAX DIE (NOTE 2) 2010 Microchip Technology Inc  )/ ...

Page 155

... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 16-3: LOAD CONDITIONS Load Condition Pin Legend: C 50 pF for all pins for OSC2 output 2010 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period ...

Page 156

... LP Oscillator mode ns XT Oscillator mode ns HS Oscillator mode ns EC Oscillator mode s LP Oscillator mode ns XT Oscillator mode ns HS Oscillator mode ns RC Oscillator mode 4/F CY OSC s LP oscillator ns XT oscillator ns HS oscillator ns LP oscillator ns XT oscillator ns HS oscillator 2010 Microchip Technology Inc. ...

Page 157

... When an external clock input is used, the max cycle time limit is DC (no clock) for all devices ensure these oscillator frequency tolerances, V possible. 0.1 F and 0.01 F values in parallel are recommended design. 2010 Microchip Technology Inc. Freq. Min Typ Max Units Tolerance — ...

Page 158

... T CY OSC Execute Q3 OS12 OS18 New Value Max Units Conditions 5. 5. — 5.0V DD — 5.0V DD — 5.0V DD ns — 2010 Microchip Technology Inc. ...

Page 159

... Asserted low. FIGURE 16-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to 0. 2010 Microchip Technology Inc BOR 37 33 HYST (Device not in Brown-out Reset) ...

Page 160

... Conditions  5V, -40° 85°  5V, -40° 125° 5V, -40° 85° 5V, -40° 125° (NOTE 3) OSC ms s V (NOTE 4) mV s  BOR 2010 Microchip Technology Inc. ...

Page 161

... Delay from External Clock Edge to Timer TMR Increment These parameters are characterized but not tested. Data in Typ column is at 5V, 25° C unless otherwise stated. These parameters are for design guidance only and are not tested. 2010 Microchip Technology Inc Min Typ† ...

Page 162

... DD DD Typ Max Units Conditions ns ns ns ns — prescale value ( 16) Max Units Comments  1 dB 600 ns 1000 ns  1.5)/ mV 1.5V)/2. 2010 Microchip Technology Inc. ...

Page 163

... SHUNT SR03 T Settling Time SETTLE SR04 C Load Capacitance LOAD I SR05 Regulator operating current SNT These parameters are characterized but not tested. 2010 Microchip Technology Inc. ) SPECIFICATIONS REF 125° C Min Typ Max V /24 DD V /32 — ...

Page 164

... V pin, whichever is selected as reference input. REF DD Conditions (5) 5.12V REF ( 5.12V REF (5) 5.12V REF (5) 5.12V REF Absolute minimum to ensure 1 LSb accuracy During V acquisition. AIN Based on differential HOLD AIN During A/D conversion cycle. 2010 Microchip Technology Inc. ...

Page 165

... BSF ADCON0, GO AD134 (T OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. 2010 Microchip Technology Inc. 125° C Min Typ Max Units s 1.6 9.0 s 3.0 9.0 s 3 ...

Page 166

... Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. DS41302D-page 166 ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the NEW_DATA DONE 2010 Microchip Technology Inc. ...

Page 167

... This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2010 Microchip Technology Inc. . (4) ...

Page 168

... Condition Note I LP OSC (32 kHz OSC (1 MHz OSC (4 MHz OSC (1 MHz OSC (4 MHz INTOSC (4 MHz INTOSC (8 MHz EXTRC (4 MHz OSC (20 MHz) DD 2010 Microchip Technology Inc. ...

Page 169

... GP3/RA3/MCLR pin is higher than for the standard I/O port pins. 2: This specification applies when GP3/RA3/MCLR is configured as the MCLR reset pin function with the weak pull-up enabled. 2010 Microchip Technology Inc. SPECIFICATIONS FOR PIC12F615-H (High Temp.) PD Min Typ ...

Page 170

... CM01 V Input Offset Voltage OS DS41302D-page 170 Frequency Units Min Typ Tolerance ±10% MHz 7.2 8.0 Units Min Typ Max mV ±5 ±20 2010 Microchip Technology Inc. Max Conditions 2.0V V 5.5V 8.8 DD -40° C T 150° Conditions (V - 1.5)/2 DD ...

Page 171

... FIGURE 17-2: PIC12F609/615/617 I 600 Typical: Statistical Mean @25° C 500 Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 400 300 200 100 2010 Microchip Technology Inc. LP (32 kHz MHz) vs (V) DD Maximum ...

Page 172

... C to 125° C) 800 600 400 200 0 1 DS41302D-page 172 EC (4 MHz MHz MHz) vs (V) DD Maximum Typical 5 6 Maximum Typical 6 5 Maximum Typical 5 6 2010 Microchip Technology Inc. ...

Page 173

... PIC12F609/615/617 I 1800 Typical: Statistical Mean @25° C 1600 Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 1400 1200 1000 800 600 400 200 0 1 2010 Microchip Technology Inc. INTOSC (4 MHz) vs (V) DD INTOSC (8 MHz) vs (V) ...

Page 174

... PIC12F609/615/617 I Typical: Statistical Mean @25° C Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) DS41302D-page 174 EXTRC (4 MHz (20 MHz) vs Maximum Typical 6 5 Maximum Typical 6 5 (V) 2010 Microchip Technology Inc. ...

Page 175

... FIGURE 17-11: PIC12F609/615/617 2010 Microchip Technology Inc. BASE vs (V) DD COMPARATOR (SINGLE ON) vs Typical: Statistical Mean @25° C Industrial: Mean (Worst-Case Temp) 3 (-40° 85° C) Extended: Mean (Worst-Case Temp) 3 (-40° 125° C) ...

Page 176

... Extended: Mean (Worst-Case Temp (-40° 125° DS41302D-page 176 WDT vs (V) DD BOR vs  (V) DD Extended Industrial Typical 6 5 Extended Industrial Typical 5 6 2010 Microchip Technology Inc. ...

Page 177

... Typical: Statistical Mean @25° C Industrial: Mean (Worst-Case Temp 100 (-40° 85° C) Extended: Mean (Worst-Case Temp (-40° 125° 2010 Microchip Technology Inc. CV (LOW RANGE) vs REF DD  ( (HI RANGE) vs. V ...

Page 178

... C to 85° C) Extended: Mean (Worst-Case Temp) 3 10 (-40° 125° DS41302D-page 178 T1OSC vs (V) DD A/D vs (V) DD Extended Industrial Typical 6 5 Extended Industrial Typical 5 6 2010 Microchip Technology Inc. ...

Page 179

... FIGURE 17-20: PIC12HV609/615 I 1400 Typical: Statistical Mean @25° C 1200 Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 1000 800 600 400 200 0 1 2010 Microchip Technology Inc. LP (32 kHz MHz MHz) vs ...

Page 180

... C to 125° C) 800 600 400 200 0 1 DS41302D-page 180 XT (1 MHz MHz) vs (V) DD INTOSC (4 MHz) vs (V) DD Maximum Typical 5 4 Maximum Typical 5 4 Maximum Typical 5 4 2010 Microchip Technology Inc. ...

Page 181

... FIGURE 17-26: PIC12HV609/615 I 400 Typical: Statistical Mean @25° C 350 Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 300 250 200 150 100 2010 Microchip Technology Inc. INTOSC (8 MHz) vs (V) DD EXTRC (4 MHz) vs (V) DD BASE vs ...

Page 182

... C to 125° C) 300 250 200 150 100 2 DS41302D-page 182 COMPARATOR (SINGLE ON) vs (V) DD WDT vs (V) DD BOR vs ( Maximum Typical 5 4 Maximum Typical 5 4 Maximum Typical 4 5 2010 Microchip Technology Inc. ...

Page 183

... FIGURE 17-32: PIC12HV609/615 I Typical: Statistical Mean @25° C 400 Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 350 300 250 200 150 100 2010 Microchip Technology Inc. CV (LOW RANGE) vs REF ( (HI RANGE) vs REF ...

Page 184

... OVER TEMPERATURE ( 0.8 Typical: Statistical Mean @25° C 0.7 Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5.0 5.5 6.0 DS41302D-page 184 A 3.0V) DD 6.5 7.0 7.5 8.0 I (mA) OL Maximum Typical 4 5 Max. 125° C Max. 85° C Typical 25° C Min. -40° C 8.5 9.0 9.5 10.0 2010 Microchip Technology Inc. ...

Page 185

... FIGURE 17-36: V vs. I OVER TEMPERATURE ( 3.5 3.0 2.5 2.0 1.5 Typical: Statistical Mean @25° C Maximum: Mean (Worst-Case Temp) 3 1.0 (-40° 125° C) 0.5 0.0 0.0 -0.5 -1.0 2010 Microchip Technology Inc. 5.0V) DD Max. 125° C Max. 85° C Typ. 25° C Min. -40°C 6.5 7.0 7.5 8.0 8.5 I (mA 3.0V) DD -1.5 -2.0 -2.5 I (mA) OH 9.0 9.5 10.0 Max. -40° C Typ. 25° C Min. 125° ...

Page 186

... Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 1.3 1.1 0.9 0.7 0.5 2.0 2.5 DS41302D-page 186 5.0V) DD -1.5 -2.0 -2.5 -3.0 -3.5 I (mA) OH vs. V OVER TEMPERATURE IN DD Max. -40° C Typ. 25° C Min. 125° C 3.0 3.5 4.0 4.5 V (V) DD Max. -40° C Typ. 25° C Min. 125° C -4.0 -4.5 -5.0 5.0 5.5 2010 Microchip Technology Inc. ...

Page 187

... FIGURE 17-40: TYPICAL HFINTOSC START-UP TIMES vs 85°C 12 25°C 10 -40° 2.0 2.5 3.0 2010 Microchip Technology Inc. vs 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25° C Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 3.5 4.0 V (V) DD OVER TEMPERATURE ...

Page 188

... DS41302D-page 188 OVER TEMPERATURE DD Typical: Statistical Mean @25° C Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25° C Maximum: Mean (Worst-Case Temp) 3 (-40° 125° C) 3.5 4.0 4.5 V (V) DD 2010 Microchip Technology Inc. 5.0 5.5 5.0 5.5 ...

Page 189

... PIC12F609/615/617/12HV609/615 FIGURE 17-43: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 17-44: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 2010 Microchip Technology Inc. 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 V (V) DD (25° 5.0 5.5 (85° 4.5 5.0 5.5 DS41302D-page 189 ...

Page 190

... PIC12F609/615/617/12HV609/615 FIGURE 17-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 17-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41302D-page 190 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (125° 5.0 5.5 (-40° 5.0 5.5 2010 Microchip Technology Inc. ...

Page 191

... FIGURE 17-48: 1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 1.26 1.25 1.24 1.23 1.22 1.21 1.2 -60 -40 -20 FIGURE 17-49: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.16 5.14 5.12 5.1 5.08 5.06 5.04 5.02 5 4.98 4. 2010 Microchip Technology Inc Temp ( Temp ( Input Current (mA) 2. 5.5V 100 120 140 2. 5.5V 100 120 140 -40° ...

Page 192

... V- input Transition from V 500 400 300 200 100 0 2.0 DS41302D-page 192 Temp (C) 100mV 20mV CM CM 2.5 4 100 120 140 Max. 125° C Max. 85° C Typ. 25° C Min. -40° C 5.5 2010 Microchip Technology Inc. ...

Page 193

... V- input Transition from V 400 300 200 100 0 2.0 FIGURE 17-53: WDT TIME-OUT PERIOD vs 1.5 2 2010 Microchip Technology Inc. - 100mV 2.5 4.0 V (V) DD OVER TEMPERATURE DD 2 (V) DD Max. 125° C Max. 85° C Typ. 25° C Min. -40° ...

Page 194

... PIC12F609/615/617/12HV609/615 NOTES: DS41302D-page 194 2010 Microchip Technology Inc. ...

Page 195

... Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2010 Microchip Technology Inc. Example XXFXXX/P ...

Page 196

... PIC12F609/615/617/12HV609/615 18.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 'XDO ,Q/LQH 3 ± PLO %RG >3',3@ 1RWH 1RWHV DS41302D-page 196 2010 Microchip Technology Inc. ...

Page 197

... PIC12F609/615/617/12HV609/615 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 ± 1DUURZ PP %RG >62,&@ 1RWH 1RWHV 2010 Microchip Technology Inc. α φ β DS41302D-page 197 ...

Page 198

... PIC12F609/615/617/12HV609/615 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 ± 1DUURZ PP %RG >62,&@ 1RWH DS41302D-page 198 2010 Microchip Technology Inc. ...

Page 199

... PIC12F609/615/617/12HV609/615 /HDG 3ODVWLF 0LFUR 6PDOO 2XWOLQH 3DFNDJH 06 >0623@ 1RWH 1RWHV 2010 Microchip Technology Inc. I φ DS41302D-page 199 ...

Page 200

... PIC12F609/615/617/12HV609/615 /HDG 3ODVWLF 'XDO )ODW 1R /HDG 3DFNDJH 0) ± [[ PP %RG >')1@ 1RWH 1RWHV DS41302D-page 200 2010 Microchip Technology Inc. ...

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