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PIC24FV32KA304 Datasheet

Download or read online Microchip Technology PIC24FV32KA304 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers With XLP Technology pdf datasheet.



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20/28/44/48-Pin, General Purpose, 16-Bit Flash
Microcontrollers with XLP Technology
Power Management Modes:
• Run – CPU, Flash, SRAM and Peripherals On
• Doze – CPU Clock Runs Slower than Peripherals
• Idle – CPU Off, Flash, SRAM and Peripherals On
• Sleep – CPU, Flash and Peripherals Off and SRAM on
• Deep Sleep – CPU, Flash, SRAM and Most Peripherals
Off; Multiple Autonomous Wake-up Sources
• Low-Power Consumption:
- Run mode currents down to 8 A, typical
- Idle mode currents down to 2.2 A, typical
- Deep Sleep mode currents down to 20 nA, typical
- Real-Time Clock/Calendar currents down to
700 nA, 32 kHz, 1.8V
- Watchdog Timer 500 nA, 1.8V typical
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider, 16-Bit x 16-Bit
Working Register Array
• C Compiler Optimized Instruction Set Architecture
Peripheral Features:
• Hardware Real-Time Clock and Calendar (RTCC):
- Provides clock, calendar and alarm functions
- Can run in Deep Sleep mode
- Can use 50/60 Hz power line input as clock source
• Programmable 32-bit Cyclic Redundancy Check
(CRC)
• Multiple Serial Communication modules:
- Two 3-/4-wire SPI modules
2
- Two I
C™ modules with multi-master/slave support
- Two UART modules supporting RS-485, RS-232,
®
LIN/J2602, IrDA
• Five 16-Bit Timers/Counters with Programmable
Prescaler:
- Can be paired as 32-bit timers/counters
• Three 16-Bit Capture Inputs with Dedicated Timers
• Three 16-Bit Compare/PWM Output with Dedicated
Timers
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
 2011-2012 Microchip Technology Inc.
PIC24FV32KA304 FAMILY
Analog Features:
• 12-Bit, Up to 16-Channel Analog-to-Digital Converter:
- 100 ksps conversion rate
- Conversion available during Sleep and Idle
- Auto-sampling timer-based option for Sleep and
Idle modes
- Wake on auto-compare option
• Dual Rail-to-Rail Analog Comparators with
Programmable Input/Output Configuration
• On-Chip Voltage Reference
• Internal Temperature Sensor
• Charge Time Measurement Unit (CTMU):
- Used for capacitance sensing, 16 channels
- Time measurement, down to 200 ps resolution
- Delay/pulse generation, down to 1 ns resolution
Special Microcontroller Features:
• Wide Operating Voltage Range:
- 1.8V to 3.6V (PIC24F devices)
- 2.0V to 5.5V (PIC24FV devices)
• Low Power Wake-up Sources and Supervisors:
- Ultra-Low Power Wake-up (ULPWU) for
Sleep/Deep Sleep
- Low-Power Watchdog Timer (DSWDT) for
Deep Sleep
- Extreme Low-Power Brown-out Reset (DSBOR)
for Deep Sleep, LPBOR for all other modes
• System Frequency Range Declaration bits:
- Declaring the frequency range optimizes the
current consumption.
• Standard Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation
• Programmable High/Low-Voltage Detect (HLVD)
• Standard Brown-out Reset (BOR) with 3 Programmable
Trip Points that can be Disabled in Sleep
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Flash Program Memory:
- Erase/write cycles: 10,000 minimum
- 40 years’ data retention minimum
• Data EEPROM:
- Erase/write cycles: 100,000 minimum
- 40 years’ data retention minimum
• Fail-Safe Clock Monitor (FSCM)
• Programmable Reference Clock Output
• Self-Programmable under Software Control
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins
DS39995C-page 1

Summary of Contents

Page 1

... Three 16-Bit Compare/PWM Output with Dedicated Timers Configurable Open-Drain Outputs on Digital I/O Pins • Three External Interrupt Sources 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Analog Features: 12-Bit 16-Channel Analog-to-Digital Converter: - 100 ksps conversion rate - Conversion available during Sleep and Idle ...

Page 2

... PIC24FV32KA304 FAMILY Memory PIC24F Device PIC24FV16KA301/ 20 16K PIC24F16KA301 PIC24FV32KA301/ 20 32K PIC24F32KA301 PIC24FV16KA302/ 28 16K PIC24F16KA302 PIC24FV32KA302/ 28 32K PIC24F32KA302 PIC24FV16KA304/ 44 16K PIC24F16KA304 PIC24FV32KA304/ 44 32K PIC24F32KA304 DS39995C-page 2 2K 512 512 512 512 512 512 ...

Page 3

... / Legend: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. Note 1: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY MCLR/RA5 RA0 SS RA1 3 ...

Page 4

... PIC24FV32KA304 FAMILY Pin Diagrams (1,2) 28-Pin SPDIP/SSOP/SOIC Pin PIC24FVXXKA302 1 MCLR/V /RA5 /CV /AN0/C3INC/CTED1/CN2/RA0 REF REF 3 CV -/V -/AN1/CN3/RA1 REF REF 4 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 5 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 6 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 7 AN5/C1INA/C2INC/SCL2/CN7/RB3 OSCI/AN13/CLKI/CN30/RA2 10 OSCO/AN14/CLKO/CN29/RA3 11 SOSCI/AN15/U2RTS/CN1/RB4 12 SOSCO/SCLKI/U2CTS/CN0/RA4 (1) 14 PGED3/ASDA /SCK2/CN27/RB5 (1) 15 PGEC3/ASCL /SDO2/CN24/RB6 16 U1TX/C2OUT/OC1/INT0/CN23/RB7 17 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 18 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 19 SDI2/IC1/CTED3/CN9/RA7 20 V CAP ...

Page 5

... Exposed pad on underside of device is connected Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. 3: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1,2,3) 28-Pin QFN ...

Page 6

... PIC24FV32KA304 FAMILY Pin Diagrams (1,2,3) 44-Pin TQFP/QFN RB9 1 RC6 2 RC7 3 RC8 4 RC9 PIC24FVXXKA304 5 RA7 6 PIC24FXXKA304 RA6 or V CAP 7 RB10 8 RB11 9 RB12 10 RB13 11 Legend: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. Note 1: Exposed pad on underside of device is connected ...

Page 7

... Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. 3: PIC24F32KA3XX device pins have a maximum voltage of 3.6V and are not 5V tolerant. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Pin PIC24FVXXKA304 1 SDA1/T1CK/U1RTS/CTED4/CN21/RB9 2 U1RX/CN18/RC6 3 U1TX/CN17/RC7 4 OC2/CN20/RC8 5 IC2/CTED7/CN19/RC9 ...

Page 8

... PIC24FV32KA304 FAMILY Table of Contents 1.0 Device Overview ... 11 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ... 23 3.0 CPU ... 29 4.0 Memory Organization ... 35 5.0 Flash Program Memory ... 57 6.0 Data EEPROM Memory ... 63 7.0 Resets ... 69 8.0 Interrupt Controller ... 75 9.0 Oscillator Configuration ... 113 10.0 Power-Saving Features ... 123 11.0 I/O Ports ... 135 12.0 Timer1 ... 139 13.0 Timer2/3 and Timer4/5 ... 141 14.0 Input Capture with Dedicated Timers ... 147 15 ...

Page 9

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System www.microchip.com Register on our web site at 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY to receive the most current information on all of our products. DS39995C-page 9 ...

Page 10

... PIC24FV32KA304 FAMILY NOTES: DS39995C-page 10 2011-2012 Microchip Technology Inc. ...

Page 11

... Operational performance MIPS 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FV32KA304 family incorporate a range of features that can significantly reduce power consumption during operation. Key features include: On-the-Fly Clock Switching: The device clock ...

Page 12

... DS39995C-page 12 1.3 Details on Individual Family Members Devices in the PIC24FV32KA304 family are available in 20-pin, 28-pin, 44-pin and 48-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are different from each other in four ways: 1 ...

Page 13

... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FV32KA304 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Data EEPROM Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...

Page 14

... PIC24FV32KA304 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24F32KA304 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Data EEPROM Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...

Page 15

... FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV and Table Data Access Control Block 23 23 Address Latch Program Memory Data EEPROM Data Latch Address Bus Instruction Decode and Control Power-up Timing OSCO/CLKO Timer Generation OSCI/CLKI Oscillator FRC/LPRC Start-up Timer Oscillators ...

Page 16

... TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS F Pin Number Function 20-Pin 28-Pin 44-Pin PDIP/ SPDIP/ 28-Pin QFN/ SSOP/ SSOP/ QFN TQFP SOIC SOIC AN0 AN1 AN2 AN3 AN4 AN5 — AN6 ...

Page 17

... TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 44-Pin PDIP/ SPDIP/ 28-Pin QFN/ SSOP/ SSOP/ QFN TQFP SOIC SOIC C3INA C3INB C3INC C3IND C3OUT CLK CLKO ...

Page 18

... TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 44-Pin PDIP/ SPDIP/ 28-Pin QFN/ SSOP/ SSOP/ QFN TQFP SOIC SOIC CN23 CN24 – CN25 - 37 CN26 - 38 CN27 – CN28 - — ...

Page 19

... TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 44-Pin PDIP/ SPDIP/ 28-Pin QFN/ SSOP/ SSOP/ QFN TQFP SOIC SOIC CTPLS HLVDIN IC1 IC2 IC3 INT0 INT1 ...

Page 20

... TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 44-Pin PDIP/ SPDIP/ 28-Pin QFN/ SSOP/ SSOP/ QFN TQFP SOIC SOIC RA0 RA1 RA2 RA3 RA4 RA5 RA6 ...

Page 21

... TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 44-Pin PDIP/ SPDIP/ 28-Pin QFN/ SSOP/ SSOP/ QFN TQFP SOIC SOIC RC0 25 RC1 26 RC2 27 RC3 36 RC4 ...

Page 22

... TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 44-Pin PDIP/ SPDIP/ 28-Pin QFN/ SSOP/ SSOP/ QFN TQFP SOIC SOIC T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS 13 18 ...

Page 23

... GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC24FV32KA304 family family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: All V and V pins ...

Page 24

... PIC24FV32KA304 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...

Page 25

... TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Make Part # TDK C3216X7R1C106K TDK C3216X5R1C106K Panasonic ECJ-3YX1C106K Panasonic ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY ) Section 29.0 Electrical Characteristics Refer to CAP information on V FIGURE 2- 0.1 Table 2-1. 0.01 0.001 . CAP 0.01 0.1 Note: Typical data measurement at 25° ...

Page 26

... PIC24FV32KA304 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the inter- nal voltage regulator of this microcontroller ...

Page 27

... Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect resistor unused pins and drive the SS output to logic low. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 2-5: for Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator ...

Page 28

... PIC24FV32KA304 FAMILY NOTES: DS39995C-page 28 2011-2012 Microchip Technology Inc. ...

Page 29

... Instructions are associated with predefined addressing modes depending upon their functional requirements. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a pro- gram (instruction) memory read per instruction cycle ...

Page 30

... PIC24FV32KA304 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data EEPROM Address Bus Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...

Page 31

... PROGRAMMERS MODEL W0 (WREG) Divider Working Registers Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits are shadowed for PUSH.S and POP.S instructions. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Frame Pointer Stack Pointer SPLIM ...

Page 32

... PIC24FV32KA304 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 bit 15 (1) (1) R/W-0, HSC R/W-0, HSC R/W-0, HSC (2) (2) IPL2 IPL1 IPL0 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-9 Unimplemented: Read as 0 ...

Page 33

... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 ...

Page 34

... PIC24FV32KA304 FAMILY 3.3.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...

Page 35

... Program Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section 4.3 Interfacing Program and Data Memory Spaces. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES PIC24FV16KA304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table ...

Page 36

... Byte (read as 0) 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 4.1.3 DATA EEPROM In the PIC24FV32KA304 family, the data EEPROM is mapped to the top of the user program memory space, organized in starting at address, 7FFE00, and expanding up to address, 7FFFFF. The data EEPROM is organized as 16-bit wide memory and 256 words deep ...

Page 37

... Program Space Visibility (PSV) area Section 4.3.3 Reading Data From Program (see Memory Using Program Space Visibility). FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES MSB Address 0001h 07FFh 0801h Implemented ...

Page 38

... The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing (MDA) with a 16-bit address field. For PIC24FV32KA304 family devices, the entire implemented data memory lies in Near Data Space. 4.2.4 SFR SPACE ...

Page 39

TABLE 4-3: CPU CORE REGISTERS MAP Start File Name Bit 15 Bit 14 Bit 13 Bit 12 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 ...

Page 40

TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (1) CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE (1,2) (1,2) CNPD2 0058 CN31PDE CN30PDE CN29PDE CN28PDE CNPD3 005A (1) CNEN1 0062 ...

Page 41

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI IFS0 0084 NVMIF AD1IF U1TXIF U1RXIF IFS1 0086 U2TXIF U2RXIF ...

Page 42

TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON TSIDL TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

Page 43

TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 ...

Page 44

TABLE 4-9: I2Cx REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 I2C1TRN 0202 I2C1BRG 0204 I2C1CON 0206 I2CEN I2CSIDL SCLREL ...

Page 45

TABLE 4-11: SPIx REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name SPI1STAT 0240 SPIEN SPISIDL SPI1CON1 0242 DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL SPI1BUF 0248 SPI2STAT 0260 SPIEN ...

Page 46

TABLE 4-14: PORTC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISC 02D0 PORTC 02D2 LATC 02D4 ODCC 02D6 ...

Page 47

TABLE 4-16: A/D REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUF10 0314 ADC1BUF11 0316 ...

Page 48

TABLE 4-17: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CTMUCON1 035A CTMUEN CTMUSIDL TGEN CTMUCON2 035C EDG1EDGE EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 CTMUICON 035E ITRIM5 ITRIM4 ITRIM3 ITRIM2 AD1CTMUENH 0360 ...

Page 49

TABLE 4-21: CRC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CRCCON1 0640 CRCEN CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN CRCCON2 0642 DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 ...

Page 50

TABLE 4-24: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR PGMONLY NVMKEY 0766 Legend: unimplemented, read as 0. Reset values are shown in ...

Page 51

... PIC24FV32KA304 FAMILY 4.2.5 SOFTWARE STACK In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and ...

Page 52

... Data EA<15> is always 1 in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. 2: PSVPAG can have only two values (00 to access program memory and FF to access data EEPROM) in the PIC24FV32KA304 family. FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) ...

Page 53

... PIC24FV32KA304 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. It also offers a direct method of ...

Page 54

... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY TBLPAG<7> the table page is located in the user memory space. When TBLPAG<7> the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas, such as the Device ID ...

Page 55

... PSVPAG is mapped into the upper half of the data memory space... 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘ ...

Page 56

... PIC24FV32KA304 FAMILY NOTES: DS39995C-page 56 2011-2012 Microchip Technology Inc. ...

Page 57

... Run-Time Self Programming (RTSP) Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FV32KA304 device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx and ...

Page 58

... PIC24FV32KA304 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions time, and to program one row at a time also possible to program single words ...

Page 59

... These values are available in ICSP mode only. Refer to the device programming specification. 3: The address in the Table Pointer decides which rows will be erased. 4: This bit is used only while accessing data EEPROM. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 U-0 (4) PGMONLY ...

Page 60

... PIC24FV32KA304 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is as follows: 1. Read a row of program memory (32 instructions) and store in data RAM. 2. Update the program data in RAM with the desired new data ...

Page 61

... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0] 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts for next 5 // instructions ...

Page 62

... PIC24FV32KA304 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS C LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr 0x1234; // Global variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2NUM_INSTRUCTION_PER_ROW]; //Set up NVMCON for row programming NVMCON 0x4001 ...

Page 63

... Perform Write/Erase operations asm volatile ("bset NVMCON, #WR n" "nop "nop 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.1 NVMCON Register The NVMCON register control register for data EEPROM program/erase operations. The upper byte contains the control bits used to start the program or erase cycle, and the flag bit to indicate if the operation was successfully performed ...

Page 64

... PIC24FV32KA304 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 WR WREN WRERR bit 15 U-0 R/W-0 R/W-0 ERASE NVMOP5 bit 7 Legend Hardware Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 WR: Write Control bit (program or erase Initiates a data EEPROM erase or write cycle (can be set, but not cleared in software) ...

Page 65

... TBLPAG W Register EA NVMADRU NVMADR 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.4 Data EEPROM Operations The EEPROM block is accessed using table read and write operations similar to those used for program memory. The TBLWTH and TBLRDH instructions are not required for data EEPROM operations since the memory is only 16 bits wide (data on the lower address is valid only) ...

Page 66

... PIC24FV32KA304 FAMILY 6.4.1 ERASE DATA EEPROM The data EEPROM can be fully erased, or can be partially erased, at three different sizes: one word, four words or eight words. The bits, NVMOP<1:0> (NVMCON<1:0>), decide the number of words to be erased. To erase partially from the data EEPROM, the following sequence must be followed: 1 ...

Page 67

... TBLPAG __builtin_tblpage(&eeData); offset __builtin_tbloffset(&eeData); __builtin_tblwtl(offset, newData); asm volatile ("disi #5"); __builtin_write_NVM(); while(NVMCONbits.WR1); 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.4.2 SINGLE-WORD WRITE To write a single word in the data EEPROM, the following sequence must be followed: 1. Erase one data EEPROM word (as mentioned in the previous section) if the PGMONLY bit (NVMCON< ...

Page 68

... PIC24FV32KA304 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the table read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location, followed by a TBLRDL instruction ...

Page 69

... Configuration Mismatch Uninitialized W Register 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets ...

Page 70

... PIC24FV32KA304 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER R/W-0, HS R/W-0, HS R/W-0 TRAPR IOPUWR SBOREN bit 15 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR SWDTEN bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...

Page 71

... BOR (RCON<1>) POR, BOR POR (RCON<0>) POR DPSLP (RCON<10>) PWRSAV #SLEEP instruction with DSCON set Note: All Reset flag bits may be set or cleared by the user software. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) (CONTINUED) (2) Setting Event Clearing Event POR POR POR ...

Page 72

... PIC24FV32KA304 FAMILY 7.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table switching is disabled, the system clock source is always selected according to the Oscillator Configuration bits. Section 9.0 Oscillator For more information, see Configuration. TABLE 7-2: OSCILLATOR SELECTION vs. ...

Page 73

... DD 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 7.5 Brown-out Reset (BOR) The PIC24FV32KA304 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> Configuration bits (FPOR<6:5,1:0>). There are a total of four BOR configurations, which are provided in Table 7-3 ...

Page 74

... PIC24FV32KA304 FAMILY 7.5.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to 1 on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘ ...

Page 75

... Table 8-1 and Table 8-2. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in AIVT is provided (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors ...

Page 76

... PIC24FV32KA304 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ...

Page 77

... Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter Ultra Low-Power Wake-up 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error ...

Page 78

... PIC24FV32KA304 FAMILY 8.3 Interrupt Control and Status Registers The PIC24FV32KA304 family of devices implements a total of 22 registers for the interrupt controller: INTCON1 INTCON2 IFS0, IFS1, IFS3 and IFS4 IEC0, IEC1, IEC3 and IEC4 IPC0 through IPC5, IPC7 and IPC15 through IPC19 • ...

Page 79

... The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 1. 3: The IPLx Status bits are read-only when NSTDIS (INTCON1<15> Note: Bit 8 and bits 4 through 0 are described in 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 ...

Page 80

... PIC24FV32KA304 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-4 Unimplemented: Read as 0 bit 3 IPL3: CPU Interrupt Priority Level Status bit ...

Page 81

... Stack error trap has occurred 0 Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 Oscillator failure trap has occurred 0 Oscillator failure trap has not occurred bit 0 Unimplemented: Read as 0 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 R/W-0, HS R/W-0, HS ...

Page 82

... PIC24FV32KA304 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 ALTIVT DISI bit 15 U-0 U-0 U-0 bit 7 Legend: HSC Hardware Settable/Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set ALTIVT: Enable Alternate Interrupt Vector Table bit bit Uses Alternate Interrupt Vector Table (AIVT) ...

Page 83

... Interrupt request has occurred 0 Interrupt request has not occurred bit 4 Unimplemented: Read as 0 bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF SPI1IF U-0 R/W-0, HS R/W-0, HS — ...

Page 84

... PIC24FV32KA304 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit bit Interrupt request has occurred ...

Page 85

... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit bit Interrupt request has occurred 0 Interrupt request has not occurred 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0, HS R/W-0, HS U-0 T5IF T4IF R/W-0, HS ...

Page 86

... PIC24FV32KA304 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 bit 15 U-0 U-0 R/W-0, HS IC3IF bit 7 Legend Hardware Settable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit ...

Page 87

... Interrupt request has occurred 0 Interrupt request has not occurred SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit bit Interrupt request has occurred 0 Interrupt request has not occurred bit 0 Unimplemented: Read as 0 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-0, HS — ...

Page 88

... PIC24FV32KA304 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS CTMUIF bit 15 U-0 U-0 U-0 bit 7 Legend Hardware Settable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-14 bit 13 CTMUIF: CTMU Interrupt Flag Status bit ...

Page 89

... W Writable bit -n Value at POR 1 Bit is set bit 15-1 Unimplemented: Read as 0 bit 0 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 U-0 U-0 U-0 — ...

Page 90

... PIC24FV32KA304 FAMILY REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 U-0 R/W-0 NVMIE AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set NVMIE: NVM Interrupt Enable bit bit Interrupt request is enabled 0 Interrupt request is not enabled Unimplemented: Read as ‘ ...

Page 91

... Interrupt request is not enabled CNIE: Input Change Notification Interrupt Enable bit bit Interrupt request is enabled 0 Interrupt request is not enabled bit 2 CMIE: Comparator Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 U-0 T5IE T4IE R/W-0 R/W-0 R/W-0 ...

Page 92

... PIC24FV32KA304 FAMILY REGISTER 8-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 ...

Page 93

... MI2C2IE: Master I2C2 Event Interrupt Enable bit bit Interrupt request is enabled 0 Interrupt request is not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 Interrupt request is enabled 0 Interrupt request is not enabled bit 0 Unimplemented: Read as 0 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-0 ...

Page 94

... PIC24FV32KA304 FAMILY REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 CTMUIE bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-14 Unimplemented: Read as 0 bit 13 CTMUIE: CTMU Interrupt Enable bit 1 Interrupt request is enabled ...

Page 95

... R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-1 Unimplemented: Read as 0 bit 0 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Bit 1 Interrupt request is enabled 0 Interrupt request is not enabled 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 U-0 U-0 U-0 ...

Page 96

... PIC24FV32KA304 FAMILY REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 T1IP2 T1IP1 bit 15 U-0 R/W-1 R/W-0 IC1IP2 IC1IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15 bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 97

... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled Unimplemented: Read as 0 bit 3-0 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-1 T2IP0 OC2IP2 R/W-0 U-0 U-0 IC2IP0 ...

Page 98

... PIC24FV32KA304 FAMILY REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 U1RXIP2 U1RXIP1 bit 15 U-0 R/W-1 R/W-0 SPF1IP2 SPF1IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 99

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 U-0 NVMIP0 R/W-0 U-0 R/W-1 AD1IP0 ...

Page 100

... PIC24FV32KA304 FAMILY REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 CNIP2 CNIP1 bit 15 U-0 R/W-1 R/W-0 MI2C1P2 MI2C1P1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 101

... Bit is set Unimplemented: Read as 0 bit 15-3 bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-1 ...

Page 102

... PIC24FV32KA304 FAMILY REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 T4IP2 T4IP1 bit 15 U-0 R/W-1 R/W-0 OC3IP2 OC3IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 103

... Interrupt source is disabled bit 3 Unimplemented: Read as 0 bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 ...

Page 104

... PIC24FV32KA304 FAMILY REGISTER 8-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 SPI2IP2 SPI2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-7 Unimplemented: Read as 0 bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 105

... IC3IP<2:0>: Input Capture Channel 3 Event Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 R/W-0 U-0 U-0 IC3IP0 — ...

Page 106

... PIC24FV32KA304 FAMILY REGISTER 8-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 bit 15 U-0 R/W-1 R/W-0 SI2C2IP2 SI2C2IP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-11 Unimplemented: Read as 0 bit 10-8 MI2C2IP <2:0>: Master I2C2 Event Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 107

... RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 7-0 Unimplemented: Read as 0 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 R/W-1 RTCIP2 U-0 U-0 U-0 ...

Page 108

... PIC24FV32KA304 FAMILY REGISTER 8-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 109

... CTMUIP<2:0>: CTMU Interrupt Priority bits bit 6-4 111 Interrupt is Priority 7 (highest priority interrupt) 001 Interrupt is Priority 1 000 Interrupt source is disabled bit 3-0 Unimplemented: Read as 0 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 U-0 U-0 R/W-1 HLVDIP2 U Unimplemented bit, read as ‘ ...

Page 110

... PIC24FV32KA304 FAMILY REGISTER 8-32: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-3 bit 6-4 ULPWUIP<2:0>: Ultra Low-Power Wake-up Interrupt Priority bits 111 Interrupt is Priority 7 (highest priority interrupt) • ...

Page 111

... Unimplemented: Read as 0 bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 Interrupt vector pending is Number 135 0000001 Interrupt vector pending is Number 9 0000000 Interrupt vector pending is Number 8 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 R-0 R-0 ILR3 ILR2 R-0 R-0 R-0 VECNUM4 ...

Page 112

... PIC24FV32KA304 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. Set the NSTDIS control bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...

Page 113

... Family Reference Section 38. Oscillator with 500 kHz Low-Power FRC (DS39726). The oscillator system for the PIC24FV32KA304 family of devices has the following features: A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. On-chip 4x Phase Locked Loop (PLL) to boost internal operating frequency on select internal and external oscillator sources ...

Page 114

... Primary Oscillator (POSC) on the OSCI and OSCO pins Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24FV32KA304 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC< ...

Page 115

... When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC 0), this bit has no effect. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY The Clock Divider register features associated with Doze mode, as well as the postscaler for the FRC oscillator. The FRC Oscillator Tune register the user to fine tune the FRC oscillator over a range of approximately ± ...

Page 116

... PIC24FV32KA304 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) CLKLOCK: Clock Selection Lock Enabled bit bit 7 If FSCM is enabled (FCKSM1 1 Clock and PLL selections are locked 0 Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...

Page 117

... Unimplemented: Read as 0 Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...

Page 118

... PIC24FV32KA304 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 R/W-0 TUN5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 0 TUN<5:0>: FRC Oscillator Tuning bits bit 5-0 011111 Maximum frequency deviation 011110 • ...

Page 119

... OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically, as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...

Page 120

... PIC24FV32KA304 FAMILY The following code sequence for a clock switch is recommended: 1. Disable interrupts during the OSCCON register unlock and write sequence. 2. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8>, in two instructions. 3. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence ...

Page 121

... Base clock value divided by 2 0000 Base clock value bit 7-0 Unimplemented: Read as 0 Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 ...

Page 122

... PIC24FV32KA304 FAMILY NOTES: DS39995C-page 122 2011-2012 Microchip Technology Inc. ...

Page 123

... For more information, refer to the PIC24F Family Reference Manual, Section 39. Power-Saving Features with Deep Sleep (DS39727). The PIC24FV32KA304 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...

Page 124

... Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 10.2.4 DEEP SLEEP MODE In PIC24FV32KA304 family devices, Deep Sleep mode is intended to provide the lowest levels of power consumption available without requiring the use of external switches to completely remove all power from the device ...

Page 125

... Deep Sleep mode, information in data RAM may be lost when exiting this mode. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0 and DSGPR1 or data EEPROM (if available) ...

Page 126

... PIC24FV32KA304 FAMILY 10.2.4.5 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (FDS< ...

Page 127

... All register bits are only reset in the case of a POR event outside of Deep Sleep mode. 2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms POR. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) U-0 U-0 U-0 ...

Page 128

... PIC24FV32KA304 FAMILY REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER U-0 U-0 U-0 bit 15 R/W-0, HS U-0 U-0 DSFLT bit 7 Legend Hardware Settable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-9 bit 8 DSINT0: Interrupt-on-Change bit ...

Page 129

... When the ULPWU module wakes the device from Sleep mode, the ULPWUIF bit (IFS5<0>) is set. Soft- ware can check this bit upon wake-up to determine the wake-up source. See Example 10-3 for initializing the ULPWU module 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY EXAMPLE 10-3: / / // 1. Charge the capacitor on RB0 // TRISBbits.TRISB0 0; LATBbits.LATB0 1; ...

Page 130

... PIC24FV32KA304 FAMILY REGISTER 10-3: ULPWCON: ULPWU CONTROL REGISTER R/W-0 U-0 R/W-0 ULPEN ULPSIDL bit 15 U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 ULPEN: ULPWU Module Enable bit 1 Module is enabled 0 Module is disabled bit 14 Unimplemented: Read as 0 ...

Page 131

... Voltage Regulator-Based Power-Saving Features The PIC24FV32KA304 series devices have a voltage regulator that has the ability to alter functionality to provide power savings. The on-board regulator is made up of two basic modules: the High-Voltage Regulator (HVREG) and the Low-Voltage Regulator (LVREG). With the combination of HVREG and LVREG, the following power modes are available: 10 ...

Page 132

... PIC24FV32KA304 FAMILY TABLE 10-1: VOLTAGE REGULATION CONFIGURATION SETTINGS FOR PIC24FV32KA304 DEVICES LVRCFG Bit LVREN Bit PMSLP Bit (FPOR<2>) (RCON<12> (RCON<8> DS39995C-page 132 Power Mode During Sleep Fast Wake-up HVREG mode (normal) is unchanged during Sleep. 1 Sleep LVREG is unused. ...

Page 133

... Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 10.6 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock ...

Page 134

... PIC24FV32KA304 FAMILY NOTES: DS39995C-page 134 2011-2012 Microchip Technology Inc. ...

Page 135

... Reference Manual, Section 12. I/O Ports with Peripheral (PPS) (DS39711). Note PIC24FV32KA304 family devices do not support Peripheral Pin Select features. All of the device pins (except V and V DD between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity ...

Page 136

... PIC24FV32KA304 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output ...

Page 137

... Unimplemented: Read as 0 bit 2-0 ANSC<2:0>: Analog Select Control bits 1 Digital input buffer is not active (use for analog input Digital input buffer is active Note 1: These bits are not available on 20-pin or 28-pin devices. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-1 U-0 U-0 ANSB12 R/W-1 ...

Page 138

... NOP. 11.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FV32KA304 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input change of states, even in Sleep mode, when the clocks are disabled ...

Page 139

... SOSCO SOSCI SOSCEN T1CK TGATE Set T1IF Reset Equal 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. Set the TON bit ( 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...

Page 140

... PIC24FV32KA304 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON TSIDL bit 15 U-0 R/W-0 R/W-0 TGATE TCKPS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 TON: Timer1 On bit 1 Starts 16-bit Timer1 0 Stops 16-bit Timer1 bit 14 Unimplemented: Read as 0 ...

Page 141

... Timer2 inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> 1). 2. Select the prescaler ratio for Timer2 or Timer4 using the TCKPS< ...

Page 142

... PIC24FV32KA304 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (2) A/D Event Trigger Equal Reset Read TMR2 (TMR4) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...

Page 143

... Set T2IF (T4IF) 0 Reset Equal FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) TGATE 1 Set T3IF (T5IF) 0 Reset A/D Event Trigger Equal 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Gate Sync Sync TMR2 (TMR4) Comparator PR2 (PR4) Sync T CY ...

Page 144

... PIC24FV32KA304 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON TSIDL bit 15 U-0 R/W-0 R/W-0 TGATE TCKPS1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set TON: Timer2 On bit bit 15 When TxCON<3> Starts 32-bit Timerx Stops 32-bit Timerx/y When TxCON< ...

Page 145

... External clock is from the T3CK pin (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as 0 Note 1: When 32-bit operation is enabled (TxCON<3> 1), these bits have no effect on Timery operation. All timer functions are set through the TxCON register. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 (1) R/W-0 U-0 (1) ...

Page 146

... PIC24FV32KA304 FAMILY NOTES: DS39995C-page 146 2011-2012 Microchip Technology Inc. ...

Page 147

... Family Reference Manual, Section 34. Input Capture with Dedicated Timer (DS39722). All devices in the PIC24FV32KA304 family feature three independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events, and generating interrupts ...

Page 148

... PIC24FV32KA304 FAMILY 14.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The ...

Page 149

... Simple Capture mode: Capture on every falling edge 001 Edge Detect Capture mode: Capture on every edge (rising and falling); ICI<1:0 bits do not control interrupt generation for this mode 000 Input capture module is turned off 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 ICTSEL2 ICTSEL1 ...

Page 150

... PIC24FV32KA304 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 bit 15 R/W-0 R/W-0, HS U-0 ICTRIG TRIGSTAT bit 7 Legend Hardware Settable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-9 Unimplemented: Read as 0 bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation) ...

Page 151

... Family Reference Section 35. Output Compare with Dedicated Timer (DS39723). All devices in the PIC24FV32KA304 family feature 3 independent output compare modules. Each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events. Also, the modules can produce Pulse-Width Modulated (PWM) waveforms for driving power applications ...

Page 152

... PIC24FV32KA304 FAMILY FIGURE 15-1: OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE) OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Increment Clock OC Clock Select Sources Match Event Trigger and Trigger and Sync Sources Sync Logic Reset DS39995C-page 152 OCxCON1 OCxCON2 OCxR Match Event Comparator OCxTMR Reset Match Event ...

Page 153

... Trigger mode operation starts after a trigger source event occurs. 6. Set the OCM<2:0> bits for the appropriate compare operation (0xx). 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. Set the OC32 (OCyCON2< ...

Page 154

... PIC24FV32KA304 FAMILY 15.3 Pulse-Width Modulation (PWM) Mode In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output ...

Page 155

... T ; Doze mode and PLL are disabled. CY OSC 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 15.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a period is complete ...

Page 156

... PIC24FV32KA304 FAMILY 15.4 Subcycle Resolution The DCBx bits (OCxCON2<10:9>) provide for resolu- tion better than one instruction cycle. When used, they delay the falling edge generated from a match event by a portion of an instruction cycle. For example, setting DCB<1:0> causes the falling edge to occur halfway through the instruction cycle in which the match event occurs, instead of at the beginning ...

Page 157

... TRIGSTAT (OCxCON2<6>) is cleared when OCxRS OCxTMR or in software 0 TRIGSTAT is only cleared by software Note 1: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 R/W-0 OCTSEL2 OCTSEL1 ...

Page 158

... PIC24FV32KA304 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) OCM<2:0>: Output Compare x Mode Select bits bit 2-0 111 Center-Aligned PWM mode on OCx 110 Edge-Aligned PWM mode on OCx 101 Double Compare Continuous Pulse mode: Initialize OCx pin low; toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 Double Compare Single-Shot mode: Initialize OCx pin low ...

Page 159

... SYNCSELx setting. 2: Use these inputs as trigger sources only and never as Sync sources. 3: These bits affect the rising edge when OCINV 1. The bits have no effect when the OCMx bits (OCxCON1<2:0>) 001. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-0 (3) OCINV DCB1 ...

Page 160

... PIC24FV32KA304 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits bit 4-0 11111 This OC module 11110 Reserved 11101 Reserved (2) 11100 CTMU (2) 11011 A/D 11010 Comparator 3 11001 Comparator 2 11000 Comparator 1 10111 Input Capture 4 10110 Input Capture 3 10101 Input Capture 2 10100 Input Capture 1 ...

Page 161

... SDO1 and SS1 are not used. Block diagrams of the module, in Standard and Enhanced Buffer modes, are shown in Figure 16-2. The devices of the PIC24FV32KA304 family offer two SPI modules on a device. Note: In this section, the SPI modules are referred to as SPIx. Special Function Registers (SFRs) will follow a similar notation ...

Page 162

... PIC24FV32KA304 FAMILY FIGURE 16-1: SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 SS1/FSYNC1 Sync Control Control Clock SDO1 bit 0 SDI1 SPI1SR Transfer SPI1BUF Read SPI1BUF DS39995C-page 162 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPI1BUF 16 Internal Data Bus 1:1/4/16/64 Primary F CY Prescaler SPI1CON1< ...

Page 163

... SDI1 SPI1SR Transfer 8-Level FIFO Receive Buffer SPI1BUF Read SPI1BUF 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY To set up the SPI1 module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPI1BUF register using interrupts: a) Clear the SPI1IF bit in the IFS0 register. ...

Page 164

... PIC24FV32KA304 FAMILY REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN SPISIDL bit 15 R-0,HSC R/C-0, HS R/W-0, HSC SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 SPIEN: SPIx Enable bit 1 Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins ...

Page 165

... SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY DS39995C-page 165 ...

Page 166

... PIC24FV32KA304 FAMILY REGISTER 16-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-13 Unimplemented: Read as 0 bit 12 DISSCK: Disable SCKx pin bit (SPIx Master modes only) ...

Page 167

... Frame Sync pulse coincides with the first bit clock 0 Frame Sync pulse precedes the first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 Enhanced buffer is enabled 0 Enhanced buffer is disabled (Legacy mode) 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 ...

Page 168

... PIC24FV32KA304 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED F SCK Note 1: Based TABLE 16-1: SAMPLE SCKx FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: Based /2; Doze mode and PLL are disabled. CY OSC 2: SCKx frequencies are indicated in kHz. ...

Page 169

... Thus, I2CxSTAT might refer to the Receive Status register for either I2C1 or I2C2. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 17.2 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communication protocols for the device being communicated with ...

Page 170

... PIC24FV32KA304 FAMILY 2 FIGURE 17-1: I C BLOCK DIAGRAM (I2C1 MODULE IS SHOWN) Shift SCL1 Clock SDA1 Shift Clock BRG Down Counter DS39995C-page 170 I2C1RCV I2C1RSR LSB Address Match Match Detect I2C1ADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect ...

Page 171

... This address will be Acknowledged only if GCEN match on this address can only occur on the upper byte in 10-Bit Addressing mode. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 17.4 Slave Address Masking The I2CxMSK register address bit positions as dont care for both 7-Bit and 10-Bit Addressing modes ...

Page 172

... PIC24FV32KA304 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Hardware Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 I2CEN: I2Cx Enable bit 1 Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 Disables the I2Cx module ...

Page 173

... SEN: Start Condition Enable bit (when operating Initiates Start condition on SDAx and SCLx pins; hardware is clear at the end of the master Start sequence 0 Start condition is not in progress 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 2 C master; applicable during master receive master ...

Page 174

... PIC24FV32KA304 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT bit 15 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC IWCOL I2COV D/A bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set ACKSTAT: Acknowledge Status bit bit NACK was detected last 0 ACK was detected last Hardware is set or clear at the end of Acknowledge ...

Page 175

... TBF: Transmit Buffer Full Status bit 1 Transmit is in progress, I2CxTRN is full 0 Transmit is complete, I2CxTRN is empty Hardware is set when the software writes to I2CxTRN; hardware is clear at the completion of data transmission. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 2 C slave device address byte. DS39995C-page 175 ...

Page 176

... PIC24FV32KA304 FAMILY REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-10 Unimplemented: Read as 0 bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits 1 Enables masking for bit incoming message address ...

Page 177

... Baud Rate Generator IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer 4-Deep FIFO Receive Data Buffer • ...

Page 178

... PIC24FV32KA304 FAMILY 18.1 UARTx Baud Rate Generator (BRG) The UARTx module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. provides the formula for computation of the baud rate with BRGH 0. EQUATION 18-1: UARTx BAUD RATE WITH ...

Page 179

... Write 55h to UxTXREG loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UARTx (as described in Transmitting in 8-Bit Data 2 ...

Page 180

... PIC24FV32KA304 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 UARTEN USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 UARTEN: UARTx Enable bit 1 UARTx is enabled; all UARTx pins are controlled by UARTx, as defined by UEN<1:0> ...

Page 181

... STSEL: Stop Bit Selection bit 1 Two Stop bits 0 One Stop bit Note 1: This feature is is only available for the 16x BRG mode (BRGH 0). 2: The bit availability depends on the pin availability. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY DS39995C-page 181 ...

Page 182

... PIC24FV32KA304 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Hardware Clearable bit HS Hardware Settable bit C Clearable bit R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 Reserved ...

Page 183

... Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the RSR to the empty state) URXDA: Receive Buffer Data Available bit (read-only) bit Receive buffer has data; at least one more characters can be read 0 Receive buffer is empty 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY DS39995C-page 183 ...

Page 184

... PIC24FV32KA304 FAMILY REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER U-x U-x U-x bit 15 W-x W-x W-x UTX7 UTX6 UTX5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set Unimplemented: Read as 0 bit 15-9 bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode) UTX<7:0>: Data of the Transmitted Character bits ...

Page 185

... Event Comparator Alarm Registers with Masks Repeat Counter 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY BCD format for smaller software overhead Optimized for long term battery operation User calibration of the 32.768 kHz clock crystal/32K INTRC frequency with periodic auto-adjust • ...

Page 186

... PIC24FV32KA304 FAMILY 19.2 RTCC Module Registers The RTCC module registers are organized into three categories: RTCC Control Registers RTCC Value Registers Alarm Value Registers 19.2.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed corresponding register pointers ...

Page 187

... The RCFGCAL register is only affected by a POR write to the RTCEN bit is only allowed when RTCWREN 1. 3: This bit is read-only cleared to 0’ write to the lower half of the MINSEC register. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R-0, HSC R-0, HSC R/W-0 (3) RTCSYNC ...

Page 188

... PIC24FV32KA304 FAMILY REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER CAL<7:0>: RTC Drift Calibration bits bit 7-0 01111111 Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 00000001 Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 No adjustment 11111111 Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute ...

Page 189

... Unimplemented: Read as 0 bit 7-0 Note 1: The RTCPWC register is only affected by a POR. 2: When a new value is written to these register bits, the Seconds Value register should also be written to properly reset the clock prescalers in the RTCC. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) R/W-0 R/W-0 R/W-0 (2) PWCSPRE RTCCLK1 ...

Page 190

... PIC24FV32KA304 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 bit 15 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set ALRMEN: Alarm Enable bit bit Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> 00h and ...

Page 191

... DAYTEN<1:0>: Binary Coded Decimal Value of Days Tens Digit bits Contains a value from bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Days Ones Digit bits Contains a value from Note 1: A write to this register is only allowed when RTCWREN 1. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) U-0 U-0 U-0 ...

Page 192

... PIC24FV32KA304 FAMILY REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER U-0 U-0 U-0 bit 15 U-0 U-0 R/W-x HRTEN1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15-11 Unimplemented: Read as 0 bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from ...

Page 193

... HRTEN<1:0>: Binary Coded Decimal Value of Hours Tens Digit bits Contains a value from bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hours Ones Digit bits Contains a value from Note 1: A write to this register is only allowed when RTCWREN 1. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 R/W-x ...

Page 194

... PIC24FV32KA304 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x MINTEN2 MINTEN1 bit 15 U-0 R/W-x R/W-x SECTEN2 SECTEN1 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 15 Unimplemented: Read as 0 bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minutes Tens Digit bits Contains a value from ...

Page 195

... The sample window timer starts counting at the end of the stability window when PWCEN 1. If PWCSTAB<7:0> 00000000, the sample window timer starts counting from every alarm event when PWCEN 1. Note 1: A write to this register is only allowed when RTCWREN 1. 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-x R/W-x R/W-x PWCSTAB4 PWCSTAB3 ...

Page 196

... PIC24FV32KA304 FAMILY 19.3 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register ...

Page 197

... Deep Sleep, etc.). To enable this feature, the RTCC must be enabled (RTCEN 1), the PWCEN register bit must be set and the RTCC pin must be driving the PWC control signal (RTCOE 1 and RTCSECSEL<1:0> 11). 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY Day of the Week Month Day ...

Page 198

... PIC24FV32KA304 FAMILY NOTES: DS39995C-page 198 2011-2012 Microchip Technology Inc. ...

Page 199

... Each XOR stage of the shift engine is programmable; see text for details. 2: Polynomial length n is determined by ([PLEN<4:0> 2011-2012 Microchip Technology Inc. PIC24FV32KA304 FAMILY The programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications. It offers the following features: • ...

Page 200

... PIC24FV32KA304 FAMILY 20.1 User Interface 20.1.1 POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials the 32nd order, using bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN<4:0> bits (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation ...

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