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PIC32MX664F128L Datasheet

Download or read online Microchip Technology PIC32MX664F128L High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers pdf datasheet.



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PIC32MX5XX/6XX/7XX
Family Data Sheet
High-Performance, USB, CAN and Ethernet
32-bit Flash Microcontrollers
© 2009-2011 Microchip Technology Inc.
DS61156G

Summary of Contents

Page 1

... PIC32MX5XX/6XX/7XX High-Performance, USB, CAN and Ethernet © 2009-2011 Microchip Technology Inc. Family Data Sheet 32-bit Flash Microcontrollers DS61156G ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009-2011, Microchip Technology Incorporated, Printed in the U ...

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... CAN module: - 2.0B Active with DeviceNet addressing support - Dedicated DMA channels 3 MHz to 25 MHz crystal oscillator © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Peripheral Features (Continued): Internal 8 MHz and 32 kHz oscillators Six UART modules with: - RS-232, RS-485 and LIN support ® ...

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... PT Yes Yes Yes PF Yes Yes Yes PF Yes Yes Yes PF Yes Yes Yes PF, BG Pin Diagrams section for more Pin Diagrams section for more © 2009-2011 Microchip Technology Inc. ...

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... PIC32MX675F256H 64 256 12 (1) PIC32MX675F512H 64 512 12 (1) PIC32MX695F512H 64 512 12 (1) PIC32MX664F064L 100 (1) PIC32MX664F128L 100 128 12 (1) PIC32MX675F256L 100 256 12 (1) PIC32MX675F512L 100 512 12 (1) 512 12 PIC32MX695F512L 100 Legend: PF TQFP MR QFN Note 1: This device features 12 KB boot Flash memory. 2: CTS and RTS pins may not be available for all UART modules ...

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... Yes Yes Yes PF Yes Yes Yes PF Yes Yes Yes PF Yes Yes Yes PF, BG Diagrams section for more Pin Diagrams section for more © 2009-2011 Microchip Technology Inc. ...

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... REF REF PGED1/AN0/V /CV /PMA6/CN2/RB0 REF REF Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PIC32MX534F064H 6 ...

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... SOSCO/T1CK/CN0/RC14 48 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 44 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 43 PIC32MX664F064H RTCC/AERXD1/ETXD3/IC1/INT1/RD8 42 PIC32MX664F128H 41 Vss PIC32MX675F256H OSC2/CLKO/RC15 40 PIC32MX675F512H OSC1/CLKI/RC12 39 PIC32MX695F512H D/RG2 37 D-/RG3 USB V 34 BUS USBID/RF3 © 2009-2011 Microchip Technology Inc. Pins are tolerant ...

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... REF REF Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pins are tolerant SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 OC1/INT0/RD0 46 45 ...

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... SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 47 46 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 45 44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 43 42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 PIC32MX764F128H Vss 41 40 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D/RG2 37 D-/RG3 USB V 34 BUS 33 USBID/RF3 Pins are tolerant © 2009-2011 Microchip Technology Inc. ...

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... AN5/C1IN/V /CN7/RB5 BUSON AN4/C1IN-/CN6/RB4 AN3/C2IN/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF PGED1/AN0/V /CV /PMA6/CN2/RB0 REF REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PIC32MX534F064H 7 PIC32MX564F064H 8 PIC32MX564F128H 9 PIC32MX575F256H 10 PIC32MX575F512H ...

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... SOSCI/CN1/RC13 OC1/INT0/RD0 46 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 44 43 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 PIC32MX664F064H RTCC/AERXD1/ETXD3/IC1/INT1/RD8 42 PIC32MX664F128H Vss 41 PIC32MX675F256H OSC2/CLKO/RC15 40 PIC32MX675F512H OSC1/CLKI/RC12 39 PIC32MX695F512H D/RG2 37 D-/RG3 USB V 34 BUS USBID/RF3 © 2009-2011 Microchip Technology Inc. Pins are tolerant ...

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... AN5/C1IN/V /CN7/RB5 11 BUSON AN4/C1IN-/CN6/RB4 12 AN3/C2IN/CN5/RB3 13 AN2/C2IN-/CN4/RB2 14 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF 15 PGED1/AN0/V /CV /PMA6/CN2/RB0 16 REF REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 44 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 43 42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss 41 PIC32MX775F256H OSC2/CLKO/RC15 40 PIC32MX775F512H OSC1/CLKI/RC12 ...

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... DS61156G-page SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 OC1/INT0/RD0 46 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 45 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 44 43 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss 41 PIC32MX764F128H OSC2/CLKO/RC15 40 OSC1/CLKI/RC12 D/RG2 37 D-/RG3 USB V 34 BUS USBID/RF3 © 2009-2011 Microchip Technology Inc. Pins are tolerant ...

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... SS2/U6RX/U3CTS/PMA2/CN11/RG9 TMS/RA0 17 INT1/RE8 18 INT2/RE9 19 AN5/C1IN/V /CN7/RB5 20 BUSON AN4/C1IN-/CN6/RB4 21 AN3/C2IN/CN5/RB3 22 AN2/C2IN-/CN4/RB2 23 PGEC1/AN1/CN3/RB1 24 PGED1/AN0/CN2/RB0 25 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pins are tolerant PIC32MX534F064L 65 PIC32MX564F064L 64 PIC32MX564F128L 63 PIC32MX575F512L 62 PIC32MX575F256L ...

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... PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN/V BUSON AN4/C1IN-/CN6/RB4 AN3/C2IN/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 PIC32MX664F064L 4 PIC32MX664F128L 5 PIC32MX675F256L 6 7 PIC32MX675F512L 8 PIC32MX695F512L MCLR TMS/RA0 /CN7/RB5 20 ...

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Pin Diagrams (Continued) 100-Pin TQFP AERXERR/RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN/V BUSON AN4/C1IN-/CN6/RB4 AN3/C2IN/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 PIC32MX775F256L 5 PIC32MX775F512L T2CK/RC1 6 PIC32MX795F512L ...

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Pin Diagrams (Continued) 100-Pin TQFP AERXERR/RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN/V BUSON AN4/C1IN-/CN6/RB4 AN3/C2IN/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 PIC32MX764F128L ...

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... RB3 RB2 RB7 K RB1 RB0 RA10 L RB6 RA9 AV SS Note 1: Refer to Table 4, © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L RE0 RG0 RF1 V DD RE1 RA7 RF0 ...

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... No Connect (NC Connect (NC BUS H9 V USB H10 D/RG2 H11 SCL2/RA2 J1 AN3/C2IN/CN5/RB3 J2 AN2/C2IN-/CN4/RB2 J3 PGED2/AN7/RB7 AN11/PMA12/RB11 J6 TCK/RA1 J7 AN12/PMA11/RB12 J8 No Connect (NC Connect (NC) J10 SCL3/SDO3/U1TX/RF8 J11 D-/RG3 K1 PGEC1/AN1/CN3/RB1 K2 PGED1/AN0/CN2/RB0 K3 V /CV /PMA6/RA10 REF REF © 2009-2011 Microchip Technology Inc. ...

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... AN8/C1OUT/RB8 K5 No Connect (NC) K6 AC1RX/SS4/U5RX/U2CTS/RF12 K7 AN14/PMALH/PMA1/RB14 SCK3/U4TX/U1RTS/CN21/RD15 K10 USBID/RF3 K11 SDA3/SDI3/U1RX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/PMA7/RA9 REF REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Full Pin Name Number AN9/C2OUT/RB9 L5 AN10/CV /PMA13/RB10 REFOUT L6 AC1TX/SCK4/U5TX/U2RTS/RF13 L7 AN13/PMA10/RB13 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 L9 SS3/U4RX/U1CTS/CN20/RD14 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4 ...

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... PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Pin Full Pin Name Number A1 PMD4/RE4 A2 PMD3/RE3 A3 TRD0/RG13 A4 PMD0/RE0 A5 PMD8/RG0 A6 ETXD0/PMD10/RF1 ETXD2/IC5/PMD12/RD12 A10 OC3/RD2 A11 OC2/RD1 B1 No Connect (NC) B2 AERXERR/RG15 B3 PMD2/RE2 B4 PMD1/RE1 B5 TRD3/RA7 B6 ETXD1/PMD11/RF0 CAP CORE ...

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... TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) Pin Full Pin Name Number K4 AN8/C1OUT/RB8 K5 No Connect (NC) K6 SS4/U5RX/U2CTS/RF12 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 K10 USBID/RF3 K11 SDA3/SDI3/U1RX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/AERXD2/PMA7/RA9 REF REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin ...

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... No Connect (NC Connect (NC BUS H9 V USB H10 D/RG2 H11 SCL2/RA2 J1 AN3/C2IN/CN5/RB3 J2 AN2/C2IN-/CN4/RB2 J3 PGED2/AN7/RB7 AN11/ERXERR/AETXERR/PMA12/RB11 J6 TCK/RA1 J7 AN12/ERXD0/AECRS/PMA11/RB12 J8 No Connect (NC Connect (NC) J10 SCL3/SDO3/U1TX/RF8 J11 D-/RG3 K1 PGEC1/AN1/CN3/RB1 K2 PGED1/AN0/CN2/RB0 K3 V /CV /AERXD3/PMA6/RA10 REF REF © 2009-2011 Microchip Technology Inc. ...

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... AN8/C1OUT/RB8 K5 No Connect (NC) K6 AC1RX/SS4/U5RX/U2CTS/RF12 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 K10 USBID/RF3 K11 SDA3/SDI3/U1RX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/AERXD2/PMA7/RA9 REF REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Full Pin Name Number AN9/C2OUT/RB9 L5 AN10/CV /PMA13/RB10 REFOUT L6 AC1TX/SCK4/U5TX/U2RTS/RF13 L7 AN13/ERXD1/AECOL/PMA10/RB13 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4 ...

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... No Connect (NC Connect (NC BUS H9 V USB H10 D/RG2 H11 SCL2/RA2 J1 AN3/C2IN/CN5/RB3 J2 AN2/C2IN-/CN4/RB2 J3 PGED2/AN7/RB7 AN11/ERXERR/AETXERR/PMA12/RB11 J6 TCK/RA1 J7 AN12/ERXD0/AECRS/PMA11/RB12 J8 No Connect (NC Connect (NC) J10 SCL3/SDO3/U1TX/RF8 J11 D-/RG3 K1 PGEC1/AN1/CN3/RB1 K2 PGED1/AN0/CN2/RB0 K3 V /CV /AERXD3/PMA6/RA10 REF REF © 2009-2011 Microchip Technology Inc. ...

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... AN8/C1OUT/RB8 K5 No Connect (NC) K6 AC1RX/SS4/U5RX/U2CTS/RF12 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 K10 USBID/RF3 K11 SDA3/SDI3/U1RX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/AERXD2/PMA7/RA9 REF REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Full Pin Name Number AN9/C2OUT/RB9 L5 AN10/CV /PMA13/RB10 REFOUT L6 AC1TX/SCK4/U5TX/U2RTS/RF13 L7 AN13/ERXD1/AECOL/PMA10/RB13 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4 ...

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... Special Features ... 165 29.0 Instruction Set ... 177 30.0 Development Support... 179 31.0 Electrical Characteristics ... 183 32.0 Packaging Information... 225 The Microchip Web Site ... 253 Customer Change Notification Service ... 253 Customer Support ... 253 Reader Response ... 254 Product Identification System... 255 DS61156G-page 28 )... 161 © 2009-2011 Microchip Technology Inc. ...

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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature num- ber) you are using. Customer Notification System Register on our web site at www.microchip.com © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX or fax the Reader Response Form in the back of this data to receive the most current information on all of our products. DS61156G-page 29 ...

Page 30

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 30 © 2009-2011 Microchip Technology Inc. ...

Page 31

... Program Flash Memory PORTG Note 1: Some features are not available on all device variants. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Figure 1-1 illustrates a general block diagram of the ...

Page 32

... C10 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. B11 O 32.768 kHz low-power oscillator crystal output. Analog Analog input O Output Pin Diagrams section for device pin availability. for more information. Description P Power I Input © 2009-2011 Microchip Technology Inc. ...

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... Legend: CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels TTL TTL input buffer Note 1: Pin numbers are provided for reference only. See the 2: See Section 24.0 Ethernet Controller © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer 121-Pin Type Type XBGA ...

Page 34

... I/O ST PORTC is a bidirectional I/O port I/O ST C10 I/O ST B11 I/O ST F11 I/O ST Analog Analog input O Output Pin Diagrams section for device pin availability. for more information. Description P Power I Input © 2009-2011 Microchip Technology Inc. ...

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... Legend: CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels TTL TTL input buffer Note 1: Pin numbers are provided for reference only. See the 2: See Section 24.0 Ethernet Controller © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer 121-Pin Type Type XBGA ...

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... UART5 transmit D11 I/O ST Synchronous serial clock input/output for SPI1 SPI1 data SPI1 data out Analog Analog input O Output Pin Diagrams section for device pin availability. for more information. Description P Power I Input © 2009-2011 Microchip Technology Inc. ...

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... Legend: CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels TTL TTL input buffer Note 1: Pin numbers are provided for reference only. See the 2: See Section 24.0 Ethernet Controller © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer 121-Pin Type Type XBGA ...

Page 38

... Master mode) or address/data (Multiplexed B4 I/O TTL/ST Master modes) B3 I/O TTL/ST A2 I/O TTL/ST A1 I/O TTL/ST D3 I/O TTL/ST C1 I/O TTL/ST D2 I/O TTL/ST A5 I/O TTL/ST E6 I/O TTL/ST A6 I/O TTL/ST B6 I/O TTL/ST A9 I/O TTL/ST D8 I/O TTL/ST D7 I/O TTL/ST C7 I/O TTL/ST Analog Analog input O Output Pin Diagrams section for device pin availability. for more information. Description P Power I Input © 2009-2011 Microchip Technology Inc. ...

Page 39

... Legend: CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels TTL TTL input buffer Note 1: Pin numbers are provided for reference only. See the 2: See Section 24.0 Ethernet Controller © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer 121-Pin Type Type XBGA ...

Page 40

... Master Clear (Reset) input. This pin is an active-low Reset to the device. Analog Analog input O Output Pin Diagrams section for device pin availability. for more information. Description (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) ( Power I Input © 2009-2011 Microchip Technology Inc. ...

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... Legend: CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels TTL TTL input buffer Note 1: Pin numbers are provided for reference only. See the 2: See Section 24.0 Ethernet Controller © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer 121-Pin Type Type XBGA ...

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... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 42 © 2009-2011 Microchip Technology Inc. ...

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... REF for ADC module is implemented Note: The AV and AV pins must connected, regardless of the ADC use and the ADC voltage reference source. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such See Figure 2-1. ...

Page 44

... Reset period during the POR. pin provides two specific device ) and fast signal transitions must IL Figure 2- Figure 2-2 within EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC32 JP C and V specifications are met. IL and V specifications are met. IL © 2009-2011 Microchip Technology Inc. ...

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... REAL ICE In-Circuit Emulator Users Guide DS51616 ® Using MPLAB REAL ICE Emulator (poster) DS51749 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.6 JTAG The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard ...

Page 46

... Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven Guard Ring to a logic-low state. Alternatively, inputs can be reserved by connecting the Main Oscillator pin to V through 10k resistor and configuring SS the pin as an input. © 2009-2011 Microchip Technology Inc. ...

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... Section 31. Direct Memory Access (DMA) Controller (DS61117) Section 32. Configuration (DS61124) Section 33. Programming and Diagnostics (DS61129) Section 34. Controller Area Network (CAN) (DS61154) Section 35. Ethernet Controller (DS61155) © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX web site ) (DS61109) ...

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... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 48 © 2009-2011 Microchip Technology Inc. ...

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... M4K PROCESSOR CORE BLOCK DIAGRAM CPU MDU Execution Core (RF/ALU/Shift) System Coprocessor © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions ® MIPS16e code compression - 16-bit encoding of 32-bit instructions to ...

Page 50

... PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. © 2009-2011 Microchip Technology Inc. ...

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... HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Operand Size (mul rt) (div rs) 16 bits 32 bits ...

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... Debug control and exception status. (2) 24 DEPC Program counter at last debug exception. 25-29 Reserved Reserved. (1) 30 ErrorEPC Program counter at last error. (2) 31 DESAVE Debug handler scratchpad register. Note 1: Registers used in exception processing. 2: Registers used during debug. DS61156G-page 52 Function © 2009-2011 Microchip Technology Inc. ...

Page 53

... AdEL Load address alignment error. Load reference to protected address. AdES Store address alignment error. Store to protected address. DBE Load or store bus error. DDBL EJTAG data hardware breakpoint matched in load data compare. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Table 3-3 lists Description DS61156G-page 53 ...

Page 54

... Port (TAP), a serial communication port used for trans- ferring test data in and out of the MIPS M4K processor core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. © 2009-2011 Microchip Technology Inc. ...

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... Robust bus exception handling to intercept runaway code Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable (KSEG0) and non-cacheable (KSEG1) address regions © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 4.1 PIC32MX5XX/6XX/7XX Memory Layout PIC32MX5XX/6XX/7XX microcontrollers implement two address schemes: virtual and physical. All ...

Page 56

... DS61156G-page 56 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM (1) 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D010000 0x1D00FFFF (2) 0x1D000000 0x00008000 0x00007FFF (2) 0x00000000 © 2009-2011 Microchip Technology Inc. ...

Page 57

... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. Memory Organization (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Physical Memory Map ...

Page 58

... PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L, PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES Virtual Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 0xBF800000 Reserved 0xBD020000 0xBD01FFFF Program Flash 0xBD000000 Reserved ...

Page 59

... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. Memory Organization (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX (1) Physical ...

Page 60

... DS61156G-page 60 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D080000 0x1D07FFFF (2) 0x1D000000 0x00010000 0x0000FFFF (2) 0x00000000 © 2009-2011 Microchip Technology Inc. ...

Page 61

... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. Memory Organization (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Physical Memory Map ...

Page 62

TABLE 4-1: BUS MATRIX REGISTER MAP 31/15 30/14 29/13 28/12 31:16 (1) 2000 BMXCON 15:0 31:16 (1) 2010 BMXDKPBA 15:0 31:16 (1) 2020 BMXDUDBA ...

Page 63

TABLE 4-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES 31/15 30/14 29/13 28/12 31:16 1000 INTCON 15:0 FRZ MVEC 31:16 (3) 1010 INTSTAT 15:0 31:16 ...

Page 64

TABLE 4-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES 31/15 30/14 29/13 28/12 31:16 10B0 IPC2 15:0 31:16 10C0 IPC3 15:0 31:16 ...

Page 65

TABLE 4-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES 31/15 30/14 29/13 28/12 31:16 1000 INTCON 15:0 FRZ MVEC 31:16 (3) 1010 INTSTAT 15:0 ...

Page 66

TABLE 4-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES 31/15 30/14 29/13 28/12 31:16 10D0 IPC4 15:0 31:16 10E0 IPC5 15:0 31:16 ...

Page 67

TABLE 4-4: INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 31/15 30/14 29/13 28/12 31:16 1000 INTCON 15:0 FRZ MVEC 31:16 (3) 1010 INTSTAT 15:0 31:16 1020 ...

Page 68

TABLE 4-4: INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 31/15 30/14 29/13 28/12 31:16 10D0 IPC4 15:0 31:16 10E0 IPC5 15:0 31:16 ...

Page 69

TABLE 4-5: INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES 31/15 30/14 29/13 28/12 31:16 1000 INTCON 15:0 FRZ MVEC 31:16 (3) 1010 INTSTAT 15:0 31:16 ...

Page 70

TABLE 4-5: INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES 31/15 30/14 29/13 28/12 31:16 10D0 IPC4 15:0 31:16 10E0 IPC5 15:0 31:16 ...

Page 71

... TABLE 4-6: INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES 31/15 30/14 29/13 28/12 31:16 1000 INTCON 15:0 FRZ MVEC 31:16 (3) 1010 INTSTAT 15:0 31:16 1020 IPTMR 15:0 U1TXIF 31:16 I2C1MIF I2C1SIF I2C1BIF SPI3TXIF SPI3RXIF 1030 ...

Page 72

... TABLE 4-6: INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES 31/15 30/14 29/13 28/12 31:16 10D0 IPC4 15:0 31:16 10E0 IPC5 15:0 31:16 10F0 IPC6 15:0 31:16 1100 IPC7 15:0 — ...

Page 73

TABLE 4-7: INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 1000 INTCON 15:0 FRZ MVEC 31:16 (3) 1010 INTSTAT 15:0 31:16 1020 ...

Page 74

TABLE 4-7: INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 10D0 IPC4 15:0 31:16 10E0 IPC5 15:0 31:16 ...

Page 75

TABLE 4-8: TIMER1-TIMER5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 0600 T1CON 15:0 ON FRZ SIDL TWDIS 31:16 0610 TMR1 15:0 31:16 0620 PR1 15:0 31:16 ...

Page 76

TABLE 4-9: INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 (1) 2000 IC1CON 15:0 ON FRZ SIDL 31:16 2010 IC1BUF 15:0 31:16 (1) 2200 IC2CON 15:0 ON FRZ SIDL 31:16 ...

Page 77

TABLE 4-10: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 3000 OC1CON 15:0 ON FRZ SIDL 31:16 3010 OC1R 15:0 31:16 3020 OC1RS 15:0 31:16 3200 OC2CON ...

Page 78

TABLE 4-11: I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 5000 I2C3CON 15:0 ON FRZ SIDL SCLREL 31:16 5010 I2C3STAT 15:0 ACKSTAT TRSTAT 31:16 5020 I2C5DD ...

Page 79

TABLE 4-11: I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 5220 I2C5ADD 15:0 31:16 5230 I2C5MSK 15:0 31:16 5240 I2C5BRG 15:0 ...

Page 80

... TABLE 4-12: I2C2 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 5400 I2C2CON 15:0 ON FRZ SIDL SCLREL 31:16 5410 I2C2STAT 15:0 ACKSTAT TRSTAT 31:16 ...

Page 81

TABLE 4-13: UART1 THROUGH UART6 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 (1) 6000 U1MODE 15:0 ON FRZ SIDL IREN 31:16 (1) 6010 U1STA 15:0 UTXISEL<1:0> UTXINV URXEN 31:16 6020 U1TXREG ...

Page 82

TABLE 4-13: UART1 THROUGH UART6 REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 6630 U6RXREG 15:0 31:16 (1) 6640 U6BRG 15:0 31:16 (1) 6800 U2MODE 15:0 ON FRZ ...

Page 83

TABLE 4-14: SPI2, SPI3 AND SPI4 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 FRMEN FRMSYNC FRMPOL MSSEN 5800 SPI3CON 15:0 ON FRZ SIDL DISSDO 31:16 5810 SPI3STAT 15:0 31:16 SPI3BUF 5820 15:0 31:16 ...

Page 84

... TABLE 4-15: SPI1 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES Register Name 31/15 30/14 29/13 28/12 31:16 FRMEN FRMSYNC FRMPOL MSSEN 5E00 SPI1CON 15:0 ON FRZ SIDL DISSDO 31:16 5E10 SPI1STAT 15:0 31:16 5E20 ...

Page 85

TABLE 4-16: ADC REGISTER MAP Register Name 31/15 30/14 29/13 28/12 31:16 (1) 9000 AD1CON1 15:0 ON FRZ SIDL 31:16 (1) 9010 AD1CON2 15:0 VCFG2 VCFG1 VCFG0 OFFCAL 31:16 (1) 9020 ...

Page 86

TABLE 4-16: ADC REGISTER MAP (CONTINUED) Register Name 31/15 30/14 29/13 28/12 31:16 9130 ADC1BUFC 15:0 31:16 9140 ADC1BUFD 15:0 31:16 9150 ADC1BUFE 15:0 31:16 9160 ADC1BUFF 15:0 Legend unknown value on Reset; unimplemented, read as ...

Page 87

TABLE 4-17: DMA GLOBAL REGISTER MAP 31/15 30/14 29/13 28/12 31:16 (1) 3000 DMACON 15:0 ON FRZ SUSPEND DMABUSY 31:16 3010 DMASTAT 15:0 31:16 3020 DMAADDR 15:0 Legend ...

Page 88

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 3060 DCH0CON 15:0 CHBUSY 31:16 3070 DCH0ECON 15:0 31:16 3080 DCH0INT 15:0 31:16 3090 ...

Page 89

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 3180 DCH1DSIZ 15:0 31:16 3190 DCH1SPTR 15:0 31:16 31A0 DCH1DPTR 15:0 31:16 31B0 DCH1CSIZ 15:0 31:16 ...

Page 90

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 3290 DCH2DAT 15:0 31:16 32A0 DCH3CON 15:0 CHBUSY 31:16 32B0 DCH3ECON 15:0 31:16 ...

Page 91

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 33B0 DCH4SSIZ 15:0 31:16 33C0 DCH4DSIZ 15:0 31:16 33D0 DCH4SPTR 15:0 31:16 33E0 DCH4DPTR 15:0 31:16 ...

Page 92

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 34D0 DCH5DAT 15:0 31:16 34E0 DCH6CON 15:0 CHBUSY 31:16 34F0 DCH6ECON 15:0 31:16 ...

Page 93

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 35F0 DCH7SSIZ 15:0 31:16 3600 DCH7DSIZ 15:0 31:16 3610 DCH7SPTR 15:0 31:16 3620 DCH7DPTR 15:0 31:16 ...

Page 94

TABLE 4-20: COMPARATOR REGISTER MAP 31/15 30/14 29/13 28/12 31:16 A000 CM1CON 15:0 ON COE CPOL 31:16 A010 CM2CON 15:0 ON COE CPOL 31:16 A060 CMSTAT 15:0 FRZ SIDL Legend: ...

Page 95

TABLE 4-22: FLASH CONTROLLER REGISTER MAP 31/15 30/14 29/13 28/12 31:16 (1) F400 NVMCON 15:0 WR WREN WRERR LVDERR 31:16 F410 NVMKEY 15:0 31:16 (1) F420 NVMADDR 15:0 31:16 F430 NVMDATA 15:0 31:16 NVMSRC F440 ADDR 15:0 ...

Page 96

... TABLE 4-24: PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 6000 TRISA 15:0 TRISA15 TRISA14 31:16 6010 PORTA 15:0 RA15 RA14 ...

Page 97

... All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See information. TABLE 4-27: PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 ...

Page 98

... All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See information. TABLE 4-29: PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 ...

Page 99

... All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See information. TABLE 4-31: PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 ...

Page 100

... All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See information. TABLE 4-33: PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 ...

Page 101

... All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See information. TABLE 4-35: PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 ...

Page 102

... TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 61C0 CNCON 15:0 ON FRZ SIDL 31:16 61D0 CNEN 15:0 CNEN15 CNEN14 ...

Page 103

TABLE 4-38: PARALLEL MASTER PORT REGISTER MAP 31/15 30/14 29/13 28/12 31:16 7000 PMCON 15:0 ON FRZ SIDL ADRMUX<1:0> 31:16 7010 PMMODE 15:0 BUSY IRQM<1:0> 31:16 7020 PMADDR ...

Page 104

TABLE 4-40: PREFETCH REGISTER MAP 31/15 30/14 29/13 28/12 31:16 (1,2) 4000 CHECON 15:0 31:16 CHEWEN (1) 4010 CHEACC 15:0 31:16 LTAGBOOT (1) 4020 CHETAG 15:0 31:16 ...

Page 105

TABLE 4-41: RTCC REGISTER MAP 31/15 30/14 29/13 28/12 31:16 0200 RTCCON 15:0 ON FRZ SIDL 31:16 0210 RTCALRM 15:0 ALRMEN CHIME PIV ALRMSYNC 31:16 HR10<3:0> 0220 RTCTIME 15:0 SEC10<3:0> 31:16 YEAR10<3:0> 0230 ...

Page 106

TABLE 4-42: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY 31/15 30/14 29/13 28/12 31:16 FVBUSIO FUSBIDIO 2FF0 DEVCFG3 15:0 31:16 2FF4 DEVCFG2 15:0 UPLLEN 31:16 2FF8 DEVCFG1 15:0 FCKSM<1:0> ...

Page 107

TABLE 4-44: USB REGISTER MAP 31/15 30/14 29/13 28/12 31:16 (2) 5040 U1OTGIR 15:0 31:16 5050 U1OTGIE 15:0 31:16 (3) 5060 U1OTGSTAT 15:0 ...

Page 108

TABLE 4-44: USB REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 (3) 5290 U1FRMH 15:0 31:16 52A0 U1TOK 15:0 31:16 52B0 U1SOF 15:0 ...

Page 109

TABLE 4-44: USB REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 53B0 U1EP11 15:0 31:16 53C0 U1EP12 15:0 31:16 53D0 U1EP13 15:0 ...

Page 110

TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 31:16 B000 C1CON 15:0 ON FRZ SIDLE 31:16 ...

Page 111

TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 31:16 FLTEN19 MSEL19<1:0> B100 C1FLTCON4 15:0 FLTEN17 MSEL17<1:0> 31:16 FLTEN23 MSEL23<1:0> ...

Page 112

TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 C000 C2CON 15:0 ON FRZ SIDLE 31:16 C010 C2CFG 15:0 SEG2PHTS SAM SEG1PH<2:0> 31:16 IVRIE ...

Page 113

TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 FLTEN19 MSEL19<1:0> C100 C2FLTCON4 15:0 FLTEN17 MSEL17<1:0> 31:16 FLTEN23 MSEL23<1:0> C110 C2FLTCON5 15:0 FLTEN21 MSEL21<1:0> 31:16 FLTEN27 MSEL27<1:0> C120 C2FLTCON6 15:0 ...

Page 114

... TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 9000 ETHCON1 15:0 ON FRZ SIDL 31:16 9010 ETHCON2 15:0 31:16 9020 ETHTXST 15:0 31:16 9030 ...

Page 115

... TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 90E0 ETHSTAT 15:0 31:16 ETH 9100 RXOVFLOW 15:0 31:16 ...

Page 116

... TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 EMAC1 9260 SUPP 15:0 31:16 EMAC1 9270 TEST 15:0 — ...

Page 117

... Refer to Section 4.0 Memory Organization this data sheet for device-specific register and bit information. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PIC32MX5XX/6XX/7XX devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory: 1 ...

Page 118

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 118 © 2009-2011 Microchip Technology Inc. ...

Page 119

... DD Detect Configuration Mismatch Reset Software Reset © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: POR: Power-on Reset MCLR: Master Clear Reset pin • ...

Page 120

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 120 © 2009-2011 Microchip Technology Inc. ...

Page 121

... CPU logic and prioritizes the interrupt events before presenting them to the CPU. FIGURE 7-1: INTERRUPT CONTROLLER MODULE Interrupt Controller © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The PIC32MX5XX/6XX/7XX interrupt module includes the following features: • interrupt sources • interrupt vectors • ...

Page 122

... IPC4<17:16> IPC4<28:26> IPC4<25:24> IPC5<4:2> IPC5<1:0> IPC5<12:10> IPC5<9:8> IPC5<20:18> IPC5<17:16> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<12:10> IPC6<9:8> IPC6<12:10> IPC6<9:8> IPC6<12:10> IPC6<9:8> IPC6<20:18> IPC6<17:16> IPC6<28:26> IPC6<25:24> and Table 3 for the list of © 2009-2011 Microchip Technology Inc. ...

Page 123

... IC1E Input Capture 1 Error IC2E Input Capture 2 Error IC3E Input Capture 3 Error IC4E Input Capture 4 Error Note 1: Not all interrupt sources are available on all devices. See available peripherals. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Interrupt Bit Location Vector IRQ Number Flag ...

Page 124

... Lowest Natural Order Priority Table 1, Table 2 Priority Sub-Priority IPC5<12:10> IPC5<9:8> IPC7<4:2> IPC7<1:0> IPC12<12:10> IPC12<9:8> IPC12<12:10> IPC12<9:8> IPC12<12:10> IPC12<9:8> IPC12<20:18> IPC12<17:16> IPC12<20:18> IPC12<17:16> IPC12<20:18> IPC12<17:16> IPC12<28:26> IPC12<25:24> and Table 3 for the list of © 2009-2011 Microchip Technology Inc. ...

Page 125

... Refer to Section 6. Oscillator (DS61112) in the PIC32 Family Reference Manual for help in determining the best oscillator components. 4. The PBCLK out is available on the OSC2 pin in certain clock modes. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The PIC32MX5XX/6XX/7XX oscillator system has the following modules and features: • ...

Page 126

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 126 © 2009-2011 Microchip Technology Inc. ...

Page 127

... Prefetch Ctrl Hit LRU Miss LRU Hit Logic PreFetch Prefetch Pre-Fetch © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. 9.1 Features • ...

Page 128

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 128 © 2009-2011 Microchip Technology Inc. ...

Page 129

... DMA BLOCK DIAGRAM INT Controller System IRQ Peripheral Bus Address Decoder Global Control (DMACON) © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Automatic word-size detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination Fixed priority channel arbitration • ...

Page 130

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 130 © 2009-2011 Microchip Technology Inc. ...

Page 131

... A block diagram of the PIC32 USB OTG module is presented in Figure 11-1. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communi- cation. The voltage comparators monitor the voltage on the V pin to determine the state of the bus ...

Page 132

... To Clock Generator for Core and Peripherals USB Suspend Sleep or Idle USB Voltage Comparators SIE Transceiver FRC Oscillator 8 MHz Typical (4) TUN<5:0> Div 2 (3) UFRCEN (6) UPLLEN USB Module (7) 48 MHz USB Clock Registers and Control Interface DMA System RAM © 2009-2011 Microchip Technology Inc. ...

Page 133

... This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX General purpose I/O pins are the simplest of peripher- als ...

Page 134

... Each CNx pin also has a weak pull-up, which acts as a current source connected to the pin. The pull-ups are enabled by setting the corresponding bit in the CNPUE register. © 2009-2011 Microchip Technology Inc. specification. Refer to IH for V IH ...

Page 135

... SOSCO/T1CK SOSCEN SOSCI Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX This family synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applica- tions and counting external events ...

Page 136

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 136 © 2009-2011 Microchip Technology Inc. ...

Page 137

... TxCK Note 1: ADC event trigger is available on Timer3 only. 2: TxCK pins are not available on 64-pin devices. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: • ...

Page 138

... TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on the Timer2/3 pair. DS61156G-page 138 (1) TMRx Sync LS Half Word PRx Gate 1 0 Sync PBCLK 0 0 © 2009-2011 Microchip Technology Inc. TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) Prescaler 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) ...

Page 139

... INPUT CAPTURE BLOCK DIAGRAM ICx Input Prescaler Edge Detect ICM<2:0> ICM<2:0> FEDGE ICxCON © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 1. Simple capture event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin 2. ...

Page 140

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 140 © 2009-2011 Microchip Technology Inc. ...

Page 141

... The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events ...

Page 142

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 142 © 2009-2011 Microchip Technology Inc. ...

Page 143

... Sync Control SSx/F SYNC SCKx Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, dis- play drivers, Analog-to-Digital Converters, etc ...

Page 144

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 144 © 2009-2011 Microchip Technology Inc. ...

Page 145

... Refer to Section 4.0 Memory Organization this data sheet for device-specific register and bit information. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2 The I C module provides complete hardware support for both Slave and Multi-Master modes of the I communication standard ...

Page 146

... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control PBCLK Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009-2011 Microchip Technology Inc. ...

Page 147

... UARTx Receiver UARTx Transmitter Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The primary features of the UART module are: Full-duplex, 8-bit or 9-bit data transmission • ...

Page 148

... UxTXREG TSR BCLK/16 (Shift Clock) UxTX Start UxTXIF UTXISEL 00 UxTXIF UTXISEL 01 UxTXIF UTXISEL 10 DS61156G-page 148 Char 5-10 Char 11-13 Stop 4 Start 5 Stop 10 Start 11 Pull from Buffer Bit 0 Bit 1 Stop 13 Cleared by Software Cleared by Software Cleared by Software Stop Start Bit 1 © 2009-2011 Microchip Technology Inc. ...

Page 149

... PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES PIC32MX5XX/6XX/7XX Parallel Master Port Note 1: On 64-pin devices, data pins, PMD<15:8>, are not available in 16-bit Master modes. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Key features of the PMP module include: 8-bit, 16-bit interface • programmable address lines • ...

Page 150

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 150 © 2009-2011 Microchip Technology Inc. ...

Page 151

... Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Following are some of the key features of this module: Time: hours, minutes and seconds 24-hour format (military time) Visibility of one-half second period Provides calendar: Weekday, date, month and year • ...

Page 152

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 152 © 2009-2011 Microchip Technology Inc. ...

Page 153

... V and V - inputs can be multiplexed with other analog inputs. REF REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX One unipolar, differential Sample and Hold Amplifier (SHA) Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer • ...

Page 154

... PIC32MX5XX/6XX/7XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM FRC Div DS61156G-page 154 ADCS<7:0> 8 ADC Conversion Clock Multiplier 2, 4,..., 512 © 2009-2011 Microchip Technology Inc. ADRC ...

Page 155

... Masks CxRX CAN Module Message Buffer 31 Message Buffer 1 Message Buffer 0 FIFO0 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Message Reception and Transmission message FIFOs - Each FIFO can have messages for a total of 1024 messages - FIFO can be a transmit message FIFO or a receive message FIFO ...

Page 156

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 156 © 2009-2011 Microchip Technology Inc. ...

Page 157

... RX Bus Master DMA Control Registers Ethernet Controller © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Following are some of the key features of this module: Supports 10/100 Mbps data transfer rates Supports full-duplex and half-duplex operation Supports RMII and MII PHY interface • ...

Page 158

... Receive Error Carrier Sense Collision Indication RMII MODE ALTERNATE INTERFACE SIGNALS (FMIIEN 0, FETHIO 0) Description Management Clock Management I/O Transmit Enable Transmit Data Transmit Data Reference Clock Carrier Sense Receive Data Valid Receive Data Receive Data Receive Error © 2009-2011 Microchip Technology Inc. ...

Page 159

... Note 1: On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module, and therefore, is not available as a comparator input. 2: Internally connected. See © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The Analog Comparator module contains two compar- ators that can be configured in a variety of ways. ...

Page 160

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 160 © 2009-2011 Microchip Technology Inc. ...

Page 161

... SS CVRSS 0 Note 1: This bit is not available on PIC32MX575/675/695/775 devices. On these devices CV network and IV is connected to 0.6V. REF © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The CV module is a 16-tap, resistor ladder network REF that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them ...

Page 162

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 162 © 2009-2011 Microchip Technology Inc. ...

Page 163

... OSC the S . Peripherals continue to operate, but OSC can optionally be individually disabled. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. • ...

Page 164

... PBCLK divider, peripheral clock require- ments, such as baud rate accuracy, should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. PLL and/or © 2009-2011 Microchip Technology Inc. ...

Page 165

... DEVCFG0: Device Configuration Word 0 DEVCFG1: Device Configuration Word 1 DEVCFG2: Device Configuration Word 2 DEVCFG3: Device Configuration Word 3 DEVID: Device and Revision ID Register © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX several device DS61156G-page 165 ...

Page 166

... CP r-1 r-1 R/P R/P R/P r-1 r-1 r-1 R/P ICESEL W Writable bit P Programmable bit 1 Bit is set 0 Bit is cleared Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 R/P BWP R/P R/P R/P PWP<7:4> r-1 r-1 r-1 r-1 R/P R/P DEBUG<1:0> Reserved bit x Bit is unknown © 2009-2011 Microchip Technology Inc. ...

Page 167

... PGEC1/PGED1 pair is used bit 2 Reserved: Write 1 bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to 11 if code-protect is enabled Debugger is disabled 10 Debugger is enabled 01 Reserved (same as 11 setting Reserved (same as 11 setting) © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX DS61156G-page 167 ...

Page 168

... Bit 29/21/13/5 28/20/12/4 27/19/11/3 r-1 r-1 r-1 r-1 R/P R/P R/P R/P r-1 FPBDIV<1:0> R/P r-1 r-1 FSOSCEN — Writable bit P Programmable bit 1 Bit is set 0 Bit is cleared Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 R/P R/P R/P WDTPS<4:0> R/P R/P R/P OSCIOFNC POSCMOD<1:0> R/P R/P R/P FNOSC<2:0> Reserved bit x Bit is unknown © 2009-2011 Microchip Technology Inc. ...

Page 169

... Primary Oscillator (XT, HS, EC) 001 Fast RC Oscillator with divide-by-N with PLL module (FRCDIVPLL) 000 Fast RC Oscillator (FRC) Note 1: Do not disable the P (POSCMOD 11 ) when using this oscillator source. OSC © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX ) OSC ) with PLL module (XTPLL, HSPLL, ECPLL) OSC (1) ...

Page 170

... Bit 29/21/13/5 28/20/12/4 27/19/11/3 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 R/P R/P-1 r-1 — Writable bit P Programmable bit 1 Bit is set 0 Bit is cleared Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 R/P R/P R/P FPLLODIV<2:0> R/P R/P R/P UPLLIDIV<2:0> R/P R/P R/P FPLLIDIV<2:0> Reserved bit x Bit is unknown © 2009-2011 Microchip Technology Inc. ...

Page 171

... USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP and JTAG Note 1: This bit is Reserved and reads 1 on PIC32MX664/675/695 devices. 2: This bit is Reserved and reads 1 on PIC32MX534/564/575 devices. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Bit Bit Bit ...

Page 172

... R (1) DEVID<23:16> (1) DEVID<15:8> (1) DEVID<7:0> Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared (1) Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8 (1) DEVID<27:24> Bit is unknown © 2009-2011 Microchip Technology Inc. ...

Page 173

... Oscillator WDTCLR 1 WDT Enable Wake WDT Enable Reset Event © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The following are some of the key features of the WDT module: Configuration or software controlled User-configurable time-out period Can wake the device from Sleep or Idle ...

Page 174

... V V CORE important that the low-ESR capacitor is placed as close as possible to the V CAP . must never CORE CONNECTIONS FOR THE ON-CHIP REGULATOR (1) 3.3V PIC32 CAP CORE V SS for and pin. CORE © 2009-2011 Microchip Technology Inc. ...

Page 175

... PGED2 TDI TDO TCK TMS TRCLK TRD0 TRD1 TRD2 TRD3 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PIC32 devices incorporate two programming and diag- nostic modules, and a trace controller, that provide a range of functions to the application developer. ICSP Controller ICESEL JTAG Controller JTAGEN DEBUG< ...

Page 176

... U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 JTAGEN U Unimplemented bit, read as 0 0 Bit is cleared Bit Bit Bit 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 TROEN TDOEN x Bit is unknown © 2009-2011 Microchip Technology Inc. ...

Page 177

... The PIC32 device family does not support the following features: Core extend instructions Coprocessor 1 instructions Coprocessor 2 instructions ® Note: Refer to MIPS32 Architecture for Programmers Volume II: The MIPS32 Instruction Set at www.mips.com more information. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX ® for DS61156G-page 177 ...

Page 178

... PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 178 © 2009-2011 Microchip Technology Inc. ...

Page 179

... MPLAB ICD 3 - PICkit 3 Debug Express Device Programmers - PICkit 2 Programmer - MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 30.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

Page 180

... Support for the entire device instruction set ® standard HEX Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility © 2009-2011 Microchip Technology Inc. ...

Page 181

... Microchip Technology Inc. PIC32MX5XX/6XX/7XX 30.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...

Page 182

... This usually includes a single application and debug capability, all on one board. for DDMAX Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2009-2011 Microchip Technology Inc. ...

Page 183

... Maximum allowable current is a function of device maximum power dissipation (see 3: See the Pin Diagrams section for the 5V tolerant pins. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX (Note 3) ... -0. 2.3V (Note 3) ... -0.3V to 5.5V ...

Page 184

... T 85°C for Industrial A -40°C T 105°C for V-Temp A Units Conditions V V V V/ µ s © 2009-2011 Microchip Technology Inc. ...

Page 185

... Data in Typical column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 4: This parameter is characterized, but not tested in manufacturing. 5: This information is preliminary. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX -40°C T 85°C for Industrial A -40°C T ≤ ...

Page 186

... Industrial A 105°C for V-Temp A Conditions 4 MHz 25 MHz (Note 3) 60 MHz (Note 3) 80 MHz 2.3V LPRC (31 kHz) 3.3V (Note 3) 3.6V 4 MHz 25 MHz (Note 3) 60 MHz (Note 3) 80 MHz 2.3V LPRC (31 kHz) 3.3V (Note 3) 3.6V © 2009-2011 Microchip Technology Inc. ...

Page 187

... Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: Data is characterized at 70°C and not tested. Parameter is for design guidance only. 6: This parameter is characterized, but not tested in manufacturing. 7: This information is preliminary. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PD -40°C T 85°C for Industrial A -40°C T ≤ ...

Page 188

... RTCC Timer1 w/32 kHz Crystal: I 3.3V RTCC Timer1 w/32 kHz Crystal: I 3.6V ADC: I 2.5V (Notes 3,4,6) ADC ADC: I 3.3V (Notes 3,4) ADC ADC: I 3.6V (Notes 3,4) ADC © 2009-2011 Microchip Technology Inc. (Notes 3,6) WDT (Note 3) WDT (Note 3) WDT (Notes 3,6) RTCC (Note 3) RTCC (Note 3) RTCC ...

Page 189

... Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C T Operating temperature -40° ...

Page 190

... 2 - - - - -40°C T 85°C for Industrial A -40°C T 105°C for V-Temp A Units Conditions 2.3 V © 2009-2011 Microchip Technology Inc. ...

Page 191

... Arbitration mode is mode 1 (CPU has lowest priority). 3: Refer to PIC32 Flash Programming Specification (DS61145) for operating conditions during programming and erase cycles. 4: This parameter applies to PIC32MX534/564/664/764 devices only. This information is preliminary. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX (3) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C T Operating temperature -40° ...

Page 192

... VDD VSS SS (Note 2) dB Max 1)V ICM DD (Note (Notes 1, 2) µ s Comparator module is configured before setting the comparator ON bit (Note 2) V For devices without BGSEL<1:0> V BGSEL<1:0> BGSEL<1:0> © 2009-2011 Microchip Technology Inc. ...

Page 193

... Regulator Output Voltage CORE D321 C External Filter Capacitor Value EFC D322 T Power-up Timer Period PWRT © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C T 85°C for Industrial Operating temperature A -40°C T 105°C for V-Temp A Min ...

Page 194

... Operating temperature -40°C T (1) Min. Typical Max. Units — 400 pF OS30 OS30 85°C for Industrial A 105°C for V-Temp A Conditions EC mode C mode OS31 OS31 © 2009-2011 Microchip Technology Inc. ...

Page 195

... All devices are tested to operate at min. values with an external clock applied to the OSC1/CLKI pin. 3: PLL input requirements characterized, but tested at 10 MHz only at manufacturing. 4: This parameter is characterized, but not tested in manufacturing. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) Min. ...

Page 196

... Industrial 105°C for V-Temp Units Conditions MHz ECPLL, HSPLL, XTPLL, FRCPLL modes MHz ms % Measured over 100 ms period 85°C for Industrial 105°C for V-Temp Conditions © 2009-2011 Microchip Technology Inc. ...

Page 197

... CNx High or Low Time (input) RBP Note 1: Data in Typical column is at 3.3V, 25°C unless otherwise stated. 2: This parameter is characterized, but not tested in manufacturing. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX -40°C T 85°C for Industrial A -40°C T 105°C for V-Temp A Min ...

Page 198

... Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR (V < DDMIN 2: Includes interval voltage regulator stabilization delay. DS61156G-page 198 SYSDLY SY02 CPU Starts Fetching Code SY00 ( (Note 1) ) OSC SYSDLY SY02 CPU Starts Fetching Code SY00 SY10 ( OST PU (Note 1) DD © 2009-2011 Microchip Technology Inc. ...

Page 199

... MCLR Pulse Width (low) MCLR SY30 T BOR Pulse Width (low) BOR Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in Typ column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested. © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX T MCLR (SY20) T BOR (T ) SYSDLY ...

Page 200

... Conditions ns Must also meet parameter TA15 ns ns Must also meet parameter TA15 ns — > 2.7V DD — < 2.7V DD — > 2.7V DD (Note 3) — < 2.7V DD (Note 3) 100 kHz — PB © 2009-2011 Microchip Technology Inc. ...

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