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PIC16F707 Datasheet

Download or read online Microchip Technology PIC16F707 40/44-Pin, Flash Microcontrollers With NanoWatt XLP And mTouch™ Technology pdf datasheet.



Summary of Contents

Page 1

... Flash Microcontrollers 2010-2011 Microchip Technology Inc. PIC16(L)F707 Data Sheet with nanoWatt XLP and mTouch Technology DS41418B ...

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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010-2011, Microchip Technology Incorporated, Printed in the U ...

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... A/D Converter: - 8-bit resolution and channels - Conversion available during Sleep - Selectable 1.024V/2.048V/4.096V voltage reference On-chip 3.2V Regulator (PIC16F707 device only) Peripheral Highlights: • I/O Pins and 1 Input-only Pin: - High current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups • ...

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... V SS CLKIN/OSC1/CPSB0/RA7 CAP (3) V CLKOUT/OSC2/CPSB1/RA6 / T1CKI/T1OSO/CPSB2/RC0 (1) CCP2 /T1OSI/CPSB3/RC1 TBCKI/CCP1/CPSB4/RC2 SCL/SCK/RC3 T3G/CPSB5/RD0 CPSB6/RD1 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F707 only. DS41418B-page 4 Capacitive Touch 8-bit A/D I/Os Channels (ch RB7/CPSB15/ICSPDAT 40 1 RB6/CPSB14/ICSPCLK 2 39 RB5/AN13/CPSB13/T1G/T3CKI ...

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... DT/RX/CPSA11/RC7 CPSA12/RD4 CPSA13/RD5 CPSA14/RD6 CPSA15/RD7 INT/CPSB8/AN12/RB0 CPSB9/AN10/RB1 CPSB10/AN8/RB2 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F707 only. 2010-2011 Microchip Technology Inc. 1 RA6/OSC2/CLKOUT/CPSB1 RA7/OSC1/CLKIN/CPSB0 PIC16F707 NC ...

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... TQFP DT/RX/CPSA11/RC7 CPSA12/RD4 CPSA13/RD5 CPSA14/RD6 CPSA15/RD7 INT/CPSB8/AN12/RB0 CPSB9/AN10/RB1 CPSB10/AN8/RB2 (1) CCP2 /CPSB11/AN9/RB3 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F707 only. DS41418B-page RC0/T1OSO/T1CKI/CPSB2 31 RA6/OSC2/CLKOUT/CPSB1 RA7/OSC1/CLKIN/CPSB0 PIC16F707 ...

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... DT/RX/CPSA11/RC7 CPSA12/RD4 CPSA13/RD5 CPSA14/RD6 CPSA15/RD7 INT/CPSB8/AN12/RB0 CPSB9/AN10/RB1 CPSB10/AN8/RB2 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F707 only. 2010-2011 Microchip Technology Inc RC0/CPSB2/T1OSO/T1CKI 2 29 RA6/OSC2/CLKOUT/CPSB1 RA7/OSC1/CLKIN/CPSB0 4 PIC16F707 ...

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... PIC16(L)F707 TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 ...

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... TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707 V 11 Vss 12 30 Note 1: Pull-up activated only with external MCLR configuration. 2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register. ...

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... History... 279 Appendix B: Migrating From Other PIC® Devices The Microchip Web Site ... 287 Customer Change Notification Service ... 287 Customer Support ... 287 Reader Response ... 288 Product Identification System... 289 DS41418B-page 10 ... 81 ... 93 ... 129 (AUSART)... 139 ... 187 ... 233 ... 279 2010-2011 Microchip Technology Inc. ...

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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2010-2011 Microchip Technology Inc. PIC16(L)F707 to receive the most current information on all of our products. DS41418B-page 11 ...

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... PIC16(L)F707 NOTES: DS41418B-page 12 2010-2011 Microchip Technology Inc. ...

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... DEVICE OVERVIEW The PIC16(L)F707 devices are covered by this data sheet. They are available in 40/44-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F707 devices. Table 1-1 shows the pinout descriptions. 2010-2011 Microchip Technology Inc. PIC16(L)F707 DS41418B-page 13 ...

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... RD6 RD7 PORTE PORTE PORTE RE0 RE1 RE2 RE3 SDI/ SCK/ SDI/ SCK/ SDI/ SCK/ SDO SDO SDO SDA SCL SDA SCL SDA SCL Synchronous Synchronous Synchronous Serial Port Serial Port Serial Port Converter DACOUT 2010-2011 Microchip Technology Inc. ...

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... RB0/AN12/CPSB8/INT RB0 AN12 CPSB8 INT RB1/AN10/CPSB9 RB1 AN10 CPSB9 Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input HV High Voltage 2010-2011 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. AN A/D Channel 0 input. ST ...

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... Capacitive sensing B input 4. ST TimerB clock input. ST CMOS General purpose I/O. ST CMOS SPI clock C™ C clock Schmitt Trigger input with CMOS levels I XTAL Crystal Description OD Open Drain 2 2 C Schmitt Trigger input with I C levels 2010-2011 Microchip Technology Inc. ...

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... CPSA7 RE3/MCLR/V RE3 PP MCLR Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input HV High Voltage 2010-2011 Microchip Technology Inc. Input Output Type Type ST CMOS General purpose I/O. ST SPI data input C ...

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... Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input HV High Voltage Note: The PIC16F707 devices have an internal low dropout voltage regulator. An external capacitor must be connected to one of the available V Section 5.0 Low Dropout (LDO) Voltage regulator and therefore no external capacitor is required. ...

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... Page 1 On-chip Program Memory Page 2 Page 3 2010-2011 Microchip Technology Inc. 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. ...

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... Reserved 18Fh 190h 191h 192h 193h 194h 195h 196h General 197h Purpose Register 198h 16 Bytes 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes 1EFh Accesses 1F0h 70h 7Fh 1FFh BANK 3 2010-2011 Microchip Technology Inc. ...

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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> 1001. 2010-2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Timer0 Module Register ...

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... SSSEL CCP2SEL ---- --00 ADFVR1 ADFVR0 x000 0000 T3GSS1 T3GSS0 0000 0x00 ADREF1 ADREF0 -000 --00 2010-2011 Microchip Technology Inc. Value on all other resets xxxx xxxx 1111 1111 0000 0000 000q quuu uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111 ...

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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> 1001. 2010-2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Timer0 Module Register Program Counter’ ...

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... ANSC1 ANSC0 111- -111 111- -111 ANSD1 ANSD0 1111 1111 1111 1111 ANSE1 ANSE0 ---- -111 ---- -111 ---0 0000 ---0 0000 INTF RBIF 0000 000x 0000 000u RD 1--- ---0 1--- ---0 2010-2011 Microchip Technology Inc. other ...

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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010-2011 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 2-1, contains: as ‘ ...

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... U Unimplemented bit, read as 0 0 Bit is cleared /4) OSC WDT Rate 128 256 1 : 128 Section 13.3 Timer1/3 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2010-2011 Microchip Technology Inc. ...

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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010-2011 Microchip Technology Inc. PIC16(L)F707 2-3. U-0 U-0 U-0 — ...

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... ORG SUB1_P1 : : RETURN RETLW and RETFIE RETURN, shows the calling of a subroutine in CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;(800h-FFFh) SUB1_P1 ;Call subroutine in ;page 1 (800h-FFFh) 900h ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh) 2010-2011 Microchip Technology Inc. ...

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... DIRECT/INDIRECT ADDRESSING Direct Addressing From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, refer to 2010-2011 Microchip Technology Inc. EXAMPLE 2-2: MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE 2-3. 2-2. 0 IRP Bank Select ...

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... PIC16(L)F707 NOTES: DS41418B-page 30 2010-2011 Microchip Technology Inc. ...

Page 31

... PWRT 11-bit Ripple Counter WDTOSC Note 1: Refer to the Configuration Word Register 1 2010-2011 Microchip Technology Inc. Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in These bits are used in software to determine the nature of the Reset ...

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... If a Status bit is not implemented, that bit will be read as 0. DS41418B-page 32 Condition (2) Program STATUS Counter Register 0000h 0001 1xxx ---- --0x 0000h 000u uuuu ---- --uu 0000h 0001 0uuu ---- --uu 0000h 0000 1uuu ---- -- uuu0 0uuu ---- --uu 0000h 0001 1uuu ---- --u0 ( uuu1 0uuu ---- --uu 2010-2011 Microchip Technology Inc. PCON Register ...

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... Reset until the operating conditions are met. For additional information, refer to Application Note AN607, Power-up Trouble Shooting (DS00607). 2010-2011 Microchip Technology Inc. 3.3 Power-up Timer (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset ...

Page 34

... Exit Sleep System Clock EXTRC, INTOSC, EXTCLK Exit Sleep System Clock XT, HS, LP DS41418B-page 34 From TMR0 Clock Source 0 Postscaler Divide by 1 512 PSA 0 To TxG WDTE Cleared until the end of OST 2010-2011 Microchip Technology Inc. 8 PS<2:0> TO TMR0 1 WDT Reset WDT Cleared ...

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... Internal Reset V DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to 0. 2010-2011 Microchip Technology Inc. PIC16(L)F707 If V falls below V for greater than parameter DD BOR (T ) (see Section 25.0 Electrical Specifica- BOR tions), the brown-out situation will reset the device. ...

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... Reset (BOR). Power-up Brown-out Reset PWRTE 1 PWRTE 0 1024 • 1024 OSC PWRT T OSC T PWRT T PWRT may have DD Section 3.5 Brown-Out Wake-up from Sleep PWRTE 1 1024 T 1024 T OSC OSC T OST 2010-2011 Microchip Technology Inc. ...

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... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset 2010-2011 Microchip Technology Inc. PIC16(L)F707 T PWRT T OST DD T PWRT T OST ): CASE 3 DS41418B-page 37 ...

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... Microchip Technology Inc. ...

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... See Table 3-2 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit 2010-2011 Microchip Technology Inc. MCLR Reset/ (1) WDT Reset --00 0000 1111 1111 1111 1111 1111 1111 ...

Page 40

... Shaded cells are - Wake-up from Sleep through Interrupt/Time-out u-uu uuuu uuuu uuuu uuu- uu-- ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu u--- ---u Value on Value on Bit 0 all other POR, BOR (1) Resets C 0001 1xxx 000q quuu BOR ---- --qq ---- --uu 2010-2011 Microchip Technology Inc. ...

Page 41

... An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. The PIC16F707 family has 16 interrupt sources, differentiated by corresponding interrupt enable and flag bits: Timer0 Overflow Interrupt • ...

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... Interrupt Latency Inst ( Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency where Section 25.0 Electrical Figure 4 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) instruction cycle time. Latency CY Specifications. 2010-2011 Microchip Technology Inc. ...

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... SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W 2010-2011 Microchip Technology Inc. following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and PCLATH registers. Note: The microcontroller does not normally require saving the PCLATH register. ...

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... GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1) (2) INTE RBIE TMR0IF U Unimplemented bit, read as 0 0 Bit is cleared (1) (2) 2010-2011 Microchip Technology Inc. R/W-0 R/W-x INTF RBIF bit Bit is unknown ...

Page 45

... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt 2010-2011 Microchip Technology Inc. PIC16(L)F707 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...

Page 46

... Enables the CCP2 interrupt 0 Disables the CCP2 interrupt DS41418B-page 46 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 U-0 U-0 TMRAIE — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets 2010-2011 Microchip Technology Inc. U-0 R/W-0 CCP2IE bit 0 ...

Page 47

... No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 The Timer1 register overflowed (must be cleared in software The Timer1 register did not overflow 2010-2011 Microchip Technology Inc. PIC16(L)F707 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...

Page 48

... GIE of the INTCON register. User software appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 U-0 U-0 TMRAIF — Unimplemented bit, read as 0 0 Bit is cleared 2010-2011 Microchip Technology Inc. should ensure the U-0 R/W-0 CCP2IF bit Bit is unknown ...

Page 49

... PIE2 TMR3GIE TMR3IE TMRBIE PIR1 TMR1GIF ADIF PIR2 TMR3GIF TMR3IF TMRBIF Legend Unimplemented locations, read as 0’ unchanged unknown. Shaded cells are not used by interrupts. 2010-2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 INTE RBIE TMR0IF PSA PS2 TXIE SSPIE ...

Page 50

... PIC16(L)F707 NOTES: DS41418B-page 50 2010-2011 Microchip Technology Inc. ...

Page 51

... LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F707 device has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the V and I/O pins to operate higher voltage. There is no user enable/disable control available for the LDO always active. The PIC16LF707 operates at a maximum V does not incorporate an LDO ...

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... PIC16(L)F707 NOTES: DS41418B-page 52 2010-2011 Microchip Technology Inc. ...

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... SSSEL: SS Input Pin Selection bit function is on RA5/AN4/CPS7/SS function is on RA0/AN0/SS/V bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 CCP2 function is on RC1/T1OSI/CCP2 1 CCP2 function is on RB3/CCP2 2010-2011 Microchip Technology Inc. PIC16(L)F707 FIGURE 6-1: GENERIC I/O PORT OPERATION D Q Write PORTx ...

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... Bit is cleared R/W-1 R/W-1 TRISA4 TRISA3 U Unimplemented bit, read as 0 0 Bit is cleared INITIALIZING PORTA ; ;Init PORTA ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<7:4,1:0> ;as outputs R/W-x R/W-x R/W-x RA2 RA1 RA0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISA2 TRISA1 TRISA0 bit Bit is unknown 2010-2011 Microchip Technology Inc. ...

Page 55

... The RA0 pin is configurable to function as one of the following: General purpose I/O Analog input for the A/D (1) Slave Select input for the SSP Voltage Regulator Capacitor pin (PIC16F707 only) Note 1: SS pin location may be selected as RA5 or RA0. 2010-2011 Microchip Technology Inc. PIC16(L)F707 ...

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... General purpose I/O Capacitive sensing input Analog input for the A/D (1) Slave Select input for the SSP Voltage Regulator Capacitor pin (PIC16F707 only) Note 1: SS pin location may be selected as RA5 or RA0. TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA ...

Page 57

... TRISB ; Note: The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read 0. 2010-2011 Microchip Technology Inc. 6.3.1 ANSELB REGISTER The ANSELB register configure the Input mode of an I/O pin to analog. is TRISB Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as ‘ ...

Page 58

... TRISB4 TRISB3 TRISB2 U Unimplemented bit, read as 0 0 Bit is cleared R/W-1 R/W-1 R/W-1 WPUB4 WPUB3 WPUB2 U Unimplemented bit, read as 0 0 Bit is cleared 2010-2011 Microchip Technology Inc. R/W-x R/W-x RB1 RB0 bit Bit is unknown R/W-1 R/W-1 TRISB1 TRISB0 bit Bit is unknown ...

Page 59

... RB0/AN12/CPSB8/INT These pins are configurable to function as one of the following: General purpose I/O Analog input for the ADC Capacitive sensing input External edge triggered interrupt 2010-2011 Microchip Technology Inc. PIC16(L)F707 R/W-0 R/W-0 R/W-0 IOCB4 IOCB3 IOCB2 U Unimplemented bit, read as 0 ...

Page 60

... T3CKPS0 T3SYNC T1GSPM T1GGO/ T1GVAL T1GSS1 DONE TRISB4 TRISB3 TRISB2 TRISB1 WPUB4 WPUB3 WPUB2 WPUB1 2010-2011 Microchip Technology Inc. Value on all Value on Bit 0 other POR, BOR Resets ADON --00 0000 --00 0000 ANSB0 1111 1111 1111 1111 CCP2SEL ---- --00 ---- --00 CCP2M0 ...

Page 61

... R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 PORTC pin configured as an input (tri-stated PORTC pin configured as an output 2010-2011 Microchip Technology Inc. EXAMPLE 6-3: BANKSEL PORTC CLRF PORTC is TRISC BANKSEL TRISC MOVLW B‘ ...

Page 62

... These pins are configurable to function as one of the following: General purpose I/O Timer1 oscillator input Capture 2 input, Compare 2 output, and PWM2 output Capacitive sensing input Note: CCP2 pin location may be selected as RB3 or RC1. 2010-2011 Microchip Technology Inc. R/W-1 R/W-1 ANSC1 ANSC0 bit Bit is unknown ...

Page 63

... TRISC TRISC7 TRISC6 TRISC5 Legend unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTC. 2010-2011 Microchip Technology Inc. 6.4.2.6 These pins are configurable to function as one of the following: General purpose I/O SPI data output Capacitive sensing input 6 ...

Page 64

... R/W-x R/W-x RD4 RD3 U Unimplemented bit, read as 0 0 Bit is cleared INITIALIZING PORTD ; ;Init PORTD ;Make PORTD digital ; ;Set RD<3:2> as inputs ;and set RD<7:4,1:0> ;as outputs (Register 6-15) is used to R/W-x R/W-x R/W-x RD2 RD1 RD0 bit Bit is unknown 2010-2011 Microchip Technology Inc. ...

Page 65

... General purpose I/O Capacitive sensing input Timer3 Gate input 6.5.2.2 RD1/CPSB6 These pins are configurable to function as one of the following: General purpose I/O Capacitive sensing input 2010-2011 Microchip Technology Inc. PIC16(L)F707 R/W-1 R/W-1 R/W-1 TRISD4 TRISD3 TRISD2 U Unimplemented bit, read as 0 ...

Page 66

... POR, BOR Resets ANSD0 1111 1111 1111 1111 TAXCS 00-- 0000 00-- 0000 CPSACH0 ---- 0000 ---- 0000 TBXCS 00-- 0000 00-- 0000 CPSBCH0 ---- 0000 ---- 0000 T3GSS0 0000 0x00 uuuu uxuu RD0 xxxx xxxx xxxx xxxx TRISD0 1111 1111 1111 1111 2010-2011 Microchip Technology Inc. ...

Page 67

... Value at POR 1 Bit is set Unimplemented: Read as 0 bit 7-4 bit 3-0 RE<3:0>: PORTE I/O Pin bits 1 Port pin is > Port pin is < 2010-2011 Microchip Technology Inc. EXAMPLE 6-5: BANKSEL PORTE CLRF PORTE BANKSEL ANSELE CLRF ANSELE BANKSEL TRISE MOVLW B00001100 ...

Page 68

... Analog input for the ADC Capacitive sensing input 6.6.2.3 RE2/AN7/CPSA7 These pins are configurable to function as one of the following: General purpose I/O Analog input for the ADC Capacitive sensing input 2010-2011 Microchip Technology Inc. R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown R/W-1 R/W-1 ...

Page 69

... TRISE Legend unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by PORTE. Note 1: This bit is always 1 as RE3 is input only. 2010-2011 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE — ...

Page 70

... PIC16(L)F707 NOTES: DS41418B-page 70 2010-2011 Microchip Technology Inc. ...

Page 71

... Internal Oscillator 500 kHz 0 32x 1 PLL PLLEN (Configuration Word 1) 2010-2011 Microchip Technology Inc. Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation External Resistor-Capacitor (RC) with F /4 output on OSC2/CLKOUT. ...

Page 72

... IRCF bits takes effect. This is because the old and new frequencies are derived from INTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the Table 25-4 in Specifications. for more Figure 7-1). The Section 25.0 Electrical 2010-2011 Microchip Technology Inc. ...

Page 73

... ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy bit 1-0 Unimplemented: Read as 0 2010-2011 Microchip Technology Inc. (Figure 7-1) clock. The ...

Page 74

... Code execution continues during this shift. There is no indication that the shift has occurred. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U Unimplemented bit, read as 0 0 Bit is cleared 2010-2011 Microchip Technology Inc. R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown ...

Page 75

... This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. 2010-2011 Microchip Technology Inc. XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. ...

Page 76

... Alternate pin functions are described in Section 6.1 Alternate Pin Function. Output depends upon RC or RCIO clock mode. ) and capacitor (C ) values EXT EXT Value on Value on Bit 0 all other POR, BOR (1) Resets FOSC0 --10 qq-- --10 qq-- TUN0 --00 0000 --uu uuuu 2010-2011 Microchip Technology Inc. ...

Page 77

... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. ® 4: MPLAB IDE masks unimplemented Configuration bits to 0. 2010-2011 Microchip Technology Inc. PIC16(L)F707 8.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. ...

Page 78

... Value at POR 1 Bit is set bit 15-6 Unimplemented: Read as 1 bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits For the PIC16LF707: These bits are ignored. All V For the PIC16F707 functionality is enabled on RA0 CAP functionality is enabled on RA5 CAP functionality is enabled on RA6 ...

Page 79

... ICSP for verification purposes. Note: The entire Flash program memory will be erased when the code protection is turned off. See the PIC16F707/PIC16LF707 Memory Programming (DS41332) for more information. 8.3 User ID Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers ...

Page 80

... PIC16(L)F707 NOTES: DS41418B-page 80 2010-2011 Microchip Technology Inc. ...

Page 81

... REF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 Reserved FV REF CHS<3:0> 2010-2011 Microchip Technology Inc. (ADC) allows shows the AV DD ADREF 0x ADREF 11 ADREF 10 0000 0001 0010 0011 0100 0101 0110 0111 ADC 1000 ...

Page 82

... Section 25.0 Electrical for more information. Table 9-1 gives , any changes in the RC clock frequency, which may ) OSC 4 MHz 1 MHz 2.0 s (2) (2) 500 ns 1.0 s 4.0 s (2) 2.0 s 8.0 s (3) 4.0 s 16.0 s (3) 8.0 s (3) 32.0 s (3) (3) 16.0 s (3) 64.0 s (3) (1,4) 1.0-6.0 s (1,4) 1.0-6.0 s (1,4) 2010-2011 Microchip Technology Inc. ...

Page 83

... GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 9.1.5 Interrupts information. 2010-2011 Microchip Technology Inc. CYCLES ...

Page 84

... Read ADC Result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 9.3 A/D Acquisition Requirements. 2010-2011 Microchip Technology Inc. Capture/Compare/PWM (1) (2) . ...

Page 85

... MOVLW B00000001;AN0, On MOVWF ADCON0 ; CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO -1 ;No, test again BANKSEL ADRES ; MOVF ADRES,W ;Read result MOVWF RESULT ;store in GPR space 2010-2011 Microchip Technology Inc. PIC16(L)F707 DS41418B-page 85 ...

Page 86

... A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 ADC is enabled 0 ADC is disabled and consumes no operating current DS41418B-page 86 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U Unimplemented bit, read as 0 0 Bit is cleared ) REF 2010-2011 Microchip Technology Inc. R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown ...

Page 87

... ADRES5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits 8-bit conversion result. 2010-2011 Microchip Technology Inc. PIC16(L)F707 R/W-0 U-0 U-0 ADCS0 — Unimplemented bit, read as 0 0 Bit is cleared ...

Page 88

... HOLD Equation 9-1 may be 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED 2010-2011 Microchip Technology Inc. ...

Page 89

... Threshold Voltage T Note 1: Refer to Section 25.0 Electrical Specifications FIGURE 9-4: ADC TRANSFER FUNCTION FFh FEh FDh FCh FBh 04h 03h 02h 01h 00h V SS 2010-2011 Microchip Technology Inc Sampling Switch 0.  Rss R IC LEAKAGE (1) I 0. ...

Page 90

... RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111 TRISB0 1111 1111 1111 1111 TRISE0 ---- 1111 ---- 1111 . Shaded cells are not used for ADC 2010-2011 Microchip Technology Inc. ...

Page 91

... FVRCON register. VOLTAGE REFERENCE BLOCK DIAGRAM FIGURE 10-1: ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010-2011 Microchip Technology Inc. 10.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC and CSM/DAC modules is routed through the two with 1.024V, independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x ...

Page 92

... A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V) Note 1: FVRRDY is always 1 on PIC16F707 devices. 2: Fixed Voltage Reference output cannot exceed V TABLE 10-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE ...

Page 93

... Reading the DACOUT pin when it has been configured for reference voltage output will always return a 0. 2010-2011 Microchip Technology Inc. 11.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR< ...

Page 94

... PIC16(L)F707 FIGURE 11-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM DACEN DACLPS DACPSS[1: DACPSS[1: REF DACPSS[1: FVR BUFFER 2 DACEN DACLPS EXAMPLE 11-1: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC16F707/ PIC16LF707 DAC R Module Voltage Reference Output Impedance DS41418B-page 94 DACR<4:0> Steps ...

Page 95

... W Writable bit u bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-5 Unimplemented: Read as 0 bit 4-0 DACR<4:0>: DAC Voltage Output Select bits 2010-2011 Microchip Technology Inc. PIC16(L)F707 U-0 R/W-0/0 R/W-0/0 DACPSS1 DACPSS0 U Unimplemented bit, read as 0 ...

Page 96

... DS41418B-page 96 Bit 4 Bit 3 Bit 2 Bit 1 Reserved CDAFVR1 CDAFVR0 ADFVR1 DACPSS1 DACPSS0 DACR4 DACR3 DACR2 DACR1 Value on Value on Bit 0 all other POR, BOR Resets ADFVR0 q000 0000 q000 0000 000- 00-- 000- 00-- DACR0 ---0 0000 ---0 0000 2010-2011 Microchip Technology Inc. ...

Page 97

... T0CKI pin 1 TMR0SE TMR0CS T1GSS 11 TMR1GE WDTE Note 1: TMR0SE, TMR0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in Configuration Word 1. 3: T1GSS and TMR1GE are in the T1GCON register. 2010-2011 Microchip Technology Inc 8-bit Prescaler PSA 1 PSA 8 PS<2:0> 1 Divide by ...

Page 98

... Operation of Timer0 is always enabled and the module will operate according to the settings of the OPTION register. 12.1.7 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. 2010-2011 Microchip Technology Inc. ...

Page 99

... RBPU INTEDG TMR0CS TMR0 TRISA TRISA7 TRISA6 TRISA5 Legend: Unimplemented locations, read as 0. Shaded cells are not used by the Timer0 module. 2010-2011 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 TMR0SE PSA U Unimplemented bit, read as 0 0 Bit is cleared /4) OSC WDT RATE ...

Page 100

... PIC16(L)F707 NOTES: DS41418B-page 100 2010-2011 Microchip Technology Inc. ...

Page 101

... Special Event Trigger with CCP (Timer1 only) Selectable Gate Source Polarity Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 13 block diagram of the Timer1/3 modules. 2010-2011 Microchip Technology Inc. PIC16(L)F707 DS41418B-page 101 ...

Page 102

... TxCKPS<1:0> F OSC 00 Internal Clock F /4 OSC 00 Internal Clock Table TimerA TimerB 0 Data Bus TxGVAL TXGCON Q1 EN Interrupt Set TMRxGIF det TMRxGE Synchronized clock input (3) Synchronize det OSC Sleep input Internal Clock 13-1. Table 13-1. 2010-2011 Microchip Technology Inc. ...

Page 103

... Microchip Technology Inc. 13.2 Clock Source Selection The TMRxCS<1:0> bits of the TxCON register and the T1OSCEN bit of the T1CON register are used to select the clock source for Timer1/3. clock source selections. 13.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the ...

Page 104

... The Timer1/3 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits of the TxGCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the TxGPOL bit of the TxGCON register. 2010-2011 Microchip Technology Inc. Counts Counts ...

Page 105

... TMRxGE 1 and WDTE TxGSS 2010-2011 Microchip Technology Inc. Timer3 Gate Pin Overflow of TimerB (TMRB increments from FFh to 00h) Timer2 match PR2 (TMR2 increments to match PR2) Count Enabled by WDT Overflow (Watchdog Time-out interval expired) 13.6.6 WATCHDOG OVERFLOW GATE OPERATION ...

Page 106

... TMR3IE bit in PIE2 register TMR3GIF bit in PIR2 register TMR3GIE bit in PIE2 register Note: The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before enabling interrupts. for interrupt bit Figure 13-5 for Figure 13-6 for timing Table 13-7 for Timer3 2010-2011 Microchip Technology Inc. ...

Page 107

... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010-2011 Microchip Technology Inc. PIC16(L)F707 In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event ...

Page 108

... TIMER1/TIMER3 GATE COUNT ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3 N FIGURE 13-4: TIMER1/TIMER3 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxG_IN TxCKI TxGVAL TIMER1 DS41418B-page 108 2010-2011 Microchip Technology Inc ...

Page 109

... TxGPOL TxGSPM TxGGO/ Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3 N Cleared by software TMRxGIF 2010-2011 Microchip Technology Inc. PIC16(L)F707 Cleared by hardware on falling edge of TxGVAL Set by hardware on falling edge of TxGVAL Cleared by software DS41418B-page 109 ...

Page 110

... TxGSPM TxGTM TxGGO/ Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3 N Cleared by software TMRxGIF DS41418B-page 110 Cleared by hardware on falling edge of TxGVAL Set by hardware on falling edge of TxGVAL 2010-2011 Microchip Technology Inc. Cleared by software ...

Page 111

... If TMRxCS<1:0> This bit is ignored. Timerx uses the internal clock when TMR1CS<1:0> 0X. bit 1 Unimplemented: Read as 0 bit 0 TMRxON: Timerx on bit 1 Enables Timerx 0 Stops Timerx Clears Timerx gate flip-flop 2010-2011 Microchip Technology Inc. PIC16(L)F707 R/W-0/0 R/W-0/0 R/W-0/0 (1) TxCKPS0 T1OSCEN TxSYNC U Unimplemented bit, read as 0 ...

Page 112

... Watchdog Timer scaler overflow Watchdog Timer oscillator is turned on if TMRxGE 1, regardless of the state of TMR1ON. DS41418B-page 112 R/W-0/0 R/W-0/0 R-0/0 TxGSPM TxGGO/ TxGVAL DONE U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets HC Bit is cleared by hardware 2010-2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 TxGSS1 TxGSS0 bit 0 ...

Page 113

... BLOCK DIAGRAM OF THE TIMERA/TIMERB PRESCALER F /4 OSC TxCKI 0 pin 0 1 From 1 CPSxOSC TMRxCS TMRxSE TxXCS Note 1: TxXCS is in the CPSxCON0 register. 2010-2011 Microchip Technology Inc. PIC16(L)F707 1 Sync 2 Tcy 0 8-bit Prescaler TMRxPSA 8 TMRxPS<2:0> Data Bus 8 TMRx Set Flag bit TMRxIF on Overflow ...

Page 114

... TimerA and TimerB cannot operate while the processor is in Sleep mode. The contents of the TMRx registers will remain unchanged while the processor is in Sleep mode Counter mode, the source must meet the timing Section 25.0 Electrical 2010-2011 Microchip Technology Inc. ...

Page 115

... TRISA TRISA7 TRISA6 TRISA5 TRISC TRISC7 TRISC6 TRISC5 Legend: Unimplemented locations, read as 0. Shaded cells are not used by the TimerA/B modules. 2010-2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 R/W-0/0 TMRxSE TMRxPSA TMRxPS2 U Unimplemented bit, read as 0 0 Bit is cleared /4) OSC ...

Page 116

... PIC16(L)F707 NOTES: DS41418B-page 116 2010-2011 Microchip Technology Inc. ...

Page 117

... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> 2010-2011 Microchip Technology Inc. PIC16(L)F707 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...

Page 118

... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 TMR1IF 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 2010-2011 Microchip Technology Inc. ...

Page 119

... Operation during sleep Acquire two samples simultaneously (when using both CSM modules) Two identical implemented on the PIC16F707/PIC16LF707. The modules are named CPSA and CPSB. The timer module integration for both capacitive sensing modules is shown in capacitive sensing module is shown in Figure 16-2 ...

Page 120

... CPSxON TMRxCS<1:0> F OSC F OSC CPSxCLK Int. Ref. T1OSC/ TxCKI CPSxOUT 0 TxGSS<1:0> 1 FVR TxG WDT Event TMR2 TimerA/B Module Set TMRxCS TMRxIF 0 Overflow TMRx 1 Timer1/3 Module /4 TMRxH:TMRxL EN Timer1/3 Gate Control Logic Timer2 Module Overflow Set Postscaler TMR2IF 2010-2011 Microchip Technology Inc. ...

Page 121

... FIGURE 16-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM CPSx Analog Pin Note 1: Module Enable and Power mode selections are not shown. 2: Comparators remain active in Noise Detection mode. 2010-2011 Microchip Technology Inc. Oscillator Module V DD (1) ( (1) ( Internal References 0 0 Ref- Ref ...

Page 122

... Please see Section 10.0 Fixed Voltage Reference and Section 11.0 Digital-to-Analog (DAC) Module for more information on configuring the variable voltage levels. 2010-2011 Microchip Technology Inc. SS Converter ...

Page 123

... Microchip Technology Inc. The remaining mode is a Noise Detection mode that resides within the high range. The Noise Detection mode is unique in that it disables the sinking and sourc- ing of current on the analog pin but leaves the rest of the oscillator circuitry active ...

Page 124

... The frequency of the capacitive sensing oscillator is equal to the number of counts on the timer divided by the period of the fixed time base. This frequency should be less than the value obtained measurement. during the nominal frequency 2010-2011 Microchip Technology Inc. ...

Page 125

... AN1101, Introduction to Capacitive Sensing (DS01101) AN1102, Layout and Physical Design Guidelines for Capacitive Sensing (DS01102). 2010-2011 Microchip Technology Inc. 16.8 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep ...

Page 126

... TimerA/B clock source is the TxCKI pin If TMRxCS 0: TimerA/B clock source is controlled by the core/TimerA/B module and is F DS41418B-page 126 U-0 R/W-0/0 R/W-0/0 CPSxRNG1 CPSxRNG0 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets 2010-2011 Microchip Technology Inc. R-0/0 R/W-0/0 CPSxOUT TxXCS bit 0 /4. OSC ...

Page 127

... Microchip Technology Inc. PIC16(L)F707 U-0 R/W-0/0 R/W-0/0 CPSxCH3 CPSxCH2 U Unimplemented bit, read as 0 ...

Page 128

... TAPS0 0-00 0000 0-00 0000 TBPS0 0-00 0000 0-00 0000 TMR1ON 0000 00-0 0000 00-0 TMR3ON 0000 -0-0 0000 -0-0 TRISA0 1111 1111 1111 1111 TRISB0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 TRISD0 1111 1111 1111 1111 TRISE0 ---- 1111 ---- 1111 2010-2011 Microchip Technology Inc. ...

Page 129

... If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1, affecting the value captured on the CCP1 pin. Note: CCPRx and CCPx throughout document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. 2010-2011 Microchip Technology Inc. PIC16(L)F707 TABLE 17-1: CCP MODE TIMER RESOURCES REQUIRED CCP Mode Capture Compare PWM Note: Timer3 has no connection to either CCP ...

Page 130

... Note 1: A/D conversion start feature is available only on CCP2. DS41418B-page 130 R/W-0 R/W-0 R/W-0 DCxB0 CCPxM3 CCPxM2 U Unimplemented bit, read as 0 0 Bit is cleared (1) is started if the ADC module is enabled. CCPx pin is unaffected.) 2010-2011 Microchip Technology Inc. R/W-0 R/W-0 CCPxM1 CCPxM0 bit Bit is unknown ...

Page 131

... In Asynchronous Counter mode or when Timer1 is clocked the capture operation may OSC not work. 2010-2011 Microchip Technology Inc. 17.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts ...

Page 132

... TMR1IF 0000 0000 0000 0000 CCP2IF 0000 ---0 0000 ---0 TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 0000 0x00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TRISB0 1111 1111 1111 1111 1111 1111 TRISC0 1111 1111 2010-2011 Microchip Technology Inc. ...

Page 133

... Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. 2010-2011 Microchip Technology Inc. 17.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...

Page 134

... TMR1IF 0000 0000 0000 0000 CCP2IF 0000 ---0 0000 ---0 TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 0000 0x00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TRISB0 1111 1111 1111 1111 1111 1111 TRISC0 1111 1111 2010-2011 Microchip Technology Inc. ...

Page 135

... In PWM mode, CCPRxH is a read-only register. 2010-2011 Microchip Technology Inc. The PWM output (period) and a time that the output stays high (duty cycle). FIGURE 17-4: ...

Page 136

... When the 10-bit time base matches the CCPRxH and (refer to 2-bit latch, then the CCPx pin is cleared (refer to Figure 17-3). PULSE WIDTH CCPRxL:CCPxCON<5:4> T (TMR2 Prescale Value) OSC 1/F OSC DUTY CYCLE RATIO CCPRxL:CCPxCON<5:4> ---------------------------------------------------------------------- - 4 PR2 bits of OSC 2010-2011 Microchip Technology Inc. ...

Page 137

... Refer to Section 7.0 Oscillator Module additional details. 17.3.7 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 2010-2011 Microchip Technology Inc. PIC16(L)F707 EQUATION 17-4: PWM RESOLUTION Resolution Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged ...

Page 138

... CCP2M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 0000 0000 0000 0000 TRISB0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 2010-2011 Microchip Technology Inc. ...

Page 139

... Multiplier x4 SYNC 1 SPBRG BRGH x 2010-2011 Microchip Technology Inc. The AUSART module includes the following capabilities: Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Synchronous Address detection in 9-bit mode (AUSART) • ...

Page 140

... DS41418B-page 140 MSb Data Stop Recovery F OSC ÷ x16 x64 FERR and CREN OERR RSR Register LSb ( START RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE 2010-2011 Microchip Technology Inc. ...

Page 141

... TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the TX/CK I/O pin as an output. 2010-2011 Microchip Technology Inc. PIC16(L)F707 Note 1: When the SPEN bit is set, the RX/DT I/O pin is automatically configured as an input, ...

Page 142

... PEIE bits of the INTCON register are also set 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 2010-2011 Microchip Technology Inc. Stop bit ...

Page 143

... AUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 2010-2011 Microchip Technology Inc. bit 0 bit 1 bit 7/8 Word 1 ...

Page 144

... The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by setting the AUSART by clearing the SPEN bit of the RCSTA register. 2010-2011 Microchip Technology Inc. ...

Page 145

... Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. 2010-2011 Microchip Technology Inc. PIC16(L)F707 overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 18.1.2.9 ...

Page 146

... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 2010-2011 Microchip Technology Inc. ...

Page 147

... TRMT: Transmit Shift Register Status bit 1 TSR empty 0 TSR full TX9D: Ninth bit of Transmit Data bit 0 Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Synchronous mode. 2010-2011 Microchip Technology Inc. R/W-0 U-0 R/W-0 (1) SYNC BRGH U Unimplemented bit, read as 0 ...

Page 148

... This can be address/data bit or a parity bit and must be calculated by user firmware. Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure TRISx 1. DS41418B-page 148 R/W-0 R/W-0 R-0 CREN ADDEN FERR U Unimplemented bit, read as 0 0 Bit is cleared (1) 2010-2011 Microchip Technology Inc. R-0 R-x OERR RX9D bit Bit is unknown ...

Page 149

... CSRC TX9 TXEN Legend unknown unimplemented read as 0. Shaded cells are not used for the Baud Rate Generator. 2010-2011 Microchip Technology Inc. EXAMPLE 18-1: For a device with F 9600, and Asynchronous mode with SYNC 0 and BRGH 0 (as seen in Desired Baud Rate ...

Page 150

... F 11.0592 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) 103 9600 0. 10473 0. 19.20k 0. 57.60k 0.00 11 115.2k 0.00 5 2010-2011 Microchip Technology Inc. ...

Page 151

... Microchip Technology Inc. SYNC 0, BRGH 4.000 MHz F 3.6864 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) 1202 ...

Page 152

... If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. 8. Start transmission by loading data to the TXREG register. 2010-2011 Microchip Technology Inc. ...

Page 153

... TRISC6 TRISC5 TXREG AUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as 0. Shaded cells are not used for synchronous master transmission. 2010-2011 Microchip Technology Inc. bit 2 bit 7 bit 0 Word 2 bit 0 bit 2 bit 1 Bit 4 Bit 3 Bit 2 ...

Page 154

... Read the 8-bit received data by reading the RCREG register. 11 overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit, which resets the AUSART. Receiving 9-bit Characters Synchronous Master Reception Set-up: 2010-2011 Microchip Technology Inc. ...

Page 155

... RX9 SREN TRISC TRISC7 TRISC6 TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as 0. Shaded cells are not used for synchronous master reception. 2010-2011 Microchip Technology Inc. bit 1 bit 2 bit 3 bit 4 Bit 4 Bit 3 Bit 2 Bit 1 ANSC2 ...

Page 156

... RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 RX9D 0000 000X 0000 000X TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 2010-2011 Microchip Technology Inc. ...

Page 157

... TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as 0. Shaded cells are not used for synchronous slave reception. 2010-2011 Microchip Technology Inc. 18.3.2.4 Synchronous Slave Reception Set- up: 1. Set the SYNC and SPEN bits and clear the CSRC bit. ...

Page 158

... TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. 2010-2011 Microchip Technology Inc. ...

Page 159

... Shift Register (SSPSR) LSb MSb General I/O Processor 1 2010-2011 Microchip Technology Inc. A typical SPI connection between microcontroller devices is shown in than one slave device is accomplished via multiple hardware slave select lines. External hardware and additional I/O pins must be used to support multiple slave select addressing. This prevents extra overhead in software for communication ...

Page 160

... TRIS register as follows: SDI configured as input SDO configured as output SCK configured as output (Figure 19-1, Master Mode Operation the transmission/reception shows the loading of the SSPBUF Enabling Master I/O 2010-2011 Microchip Technology Inc. is ...

Page 161

... In Master mode, all module clocks are halted and the transmission/reception will remain in their current state, paused, until the device wakes from Sleep. After the device wakes up from Sleep, the module will continue to transmit/receive data. 2010-2011 Microchip Technology Inc. PIC16(L)F707 DS41418B-page 161 ...

Page 162

... MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA reg contents of TXDATA MOVWF SSPBUF ;New data to xmit DS41418B-page 162 bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 1 bit 3 2010-2011 Microchip Technology Inc. 4 Clock Modes bit 0 bit 0 bit 0 bit 0 ...

Page 163

... A SPI module transmits and receives at the same time, occasionally causing dummy data to be transmitted/ received the user to determine which data used and what can be discarded. 2010-2011 Microchip Technology Inc. PIC16(L)F707 19.1.2.2 Enabling Slave I/O To enable the serial port, the SSPEN bit of the SSPCON register must be set ...

Page 164

... SCK (CKP 1 CKE 1) Write to SSPBUF SDO bit 7 SDI (SMP 0) bit 7 Input Sample (SMP 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41418B-page 164 bit 6 bit 5 bit 4 bit 2 bit 3 bit 6 bit 2 bit 5 bit 4 bit 3 bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 2010-2011 Microchip Technology Inc. ...

Page 165

... Interrupt Flag SSPSR to SSPBUF 2010-2011 Microchip Technology Inc. When the SPI module resets, the bit counter is cleared to 0. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. shows the timing waveform for such a synchronization event ...

Page 166

... SPI Slave mode, clock SCK pin. SS pin control disabled. SS can be used as I/O pin. Note 1: When enabled, these pins must be properly configured as input or output. DS41418B-page 166 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U Unimplemented bit, read as 0 0 Bit is cleared /4 OSC /16 OSC /64 OSC 2010-2011 Microchip Technology Inc. R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (1) ...

Page 167

... UA: Update Address bit 2 Used mode only. bit 0 BF: Buffer Full Status bit 1 Receive complete, SSPBUF is full 0 Receive not complete, SSPBUF is empty 2010-2011 Microchip Technology Inc. PIC16(L)F707 R-0 R Unimplemented bit, read as 0 0 Bit is cleared ...

Page 168

... SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 2010-2011 Microchip Technology Inc. ...

Page 169

... Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect SSPADD Reg Start and Stop bit Detect 2010-2011 Microchip Technology Inc. FIGURE 19-8: Master SDA SCL 2 C The SSP module has six registers for I They are: SSP Control (SSPCON) register • ...

Page 170

... SSPOV. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. Generate ACK Pulse Yes Yes Stop Condition shows the results of when a data Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes 2010-2011 Microchip Technology Inc. ...

Page 171

... For a 10-bit address, the first byte would equal 1111 0, where A9 and A8 are the two MSbs of the address. 2010-2011 Microchip Technology Inc. PIC16(L)F707 The sequence of events for 10-bit address is as follows for reception: 1 ...

Page 172

... Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. Receiving Data ACK Bus Master sends Stop condition ACK is not sent. 2010-2011 Microchip Technology Inc. ...

Page 173

Clock is held low until update of SSPADD has taken place Receive First Byte of Address Receive Second Byte of Address ACK R/W SDA ...

Page 174

... Cleared in software SSPBUF is written in software From SSP Interrupt to clear BF flag Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Transmitting Data ACK Service Routine 2010-2011 Microchip Technology Inc. ...

Page 175

Clock is held low until update of SSPADD has taken place R Receive First Byte of Address Receive Second Byte of Address SDA ...

Page 176

... Refer to Application Note AN578, Use of the SSP Module in the I (DS00578) for more information bus may Note AN554, Software 2 C Bus Master (DS00554) for more 2 C Multi-Master Environment 2010-2011 Microchip Technology Inc. ...

Page 177

... SDA DX SCL CKP WR SSPCON 2010-2011 Microchip Technology Inc. 19.2.11 SLEEP OPERATION While in Sleep mode, the I addresses of data, and when an address match master complete byte transfer occurs, wake the processor from Sleep (if SSP interrupt is enabled) ...

Page 178

... When enabled, these pins must be properly configured as input or output using the associated TRIS bit. DS41418B-page 178 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U Unimplemented bit, read as 0 0 Bit is cleared (1) 2010-2011 Microchip Technology Inc MODE) R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (2) ...

Page 179

... Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive Receive complete, SSPBUF is full 0 Receive not complete, SSPBUF is empty Transmit Transmit in progress, SSPBUF is full 0 Transmit complete, SSPBUF is empty 2010-2011 Microchip Technology Inc. R-0 R Unimplemented bit, read as 0 0 Bit is cleared 2 C Standard mode (100 kHz and 1 MHz) ...

Page 180

... TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 SSPM0 0000 0000 0000 0000 1111 1111 1111 1111 BF 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 2010-2011 Microchip Technology Inc. ...

Page 181

... LOWPMBYTE MOVF PMDATH, W MOVWF HIGHPMBYTE 2010-2011 Microchip Technology Inc. The value written to the PMADRH:PMADRL register pair determines which program memory location is read. The read operation will be initiated by setting the RD bit of the PMCON1 register. The program memory flash controller takes two instructions to complete the read ...

Page 182

... R/W-x R/W-x PMD12 PMD11 PMD10 U Unimplemented bit, read as 0 0 Bit is cleared R/W-x R/W-x R/W-x PMD4 PMD3 PMD2 U Unimplemented bit, read as 0 0 Bit is cleared 2010-2011 Microchip Technology Inc. U-0 R/S-0 RD bit Bit is unknown R/W-x R/W-x PMD9 PMD8 bit Bit is unknown R/W-x R/W-x PMD1 ...

Page 183

... PMDATL Program Memory Read Data Register Low Byte Legend unknown unchanged, unimplemented, read as 0. Shaded cells are not used by the program memory read. 2010-2011 Microchip Technology Inc. R/W-x R/W-x PMA12 PMA11 U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 184

... PIC16(L)F707 NOTES: DS41418B-page 184 2010-2011 Microchip Technology Inc. ...

Page 185

... Section 11.0 Digital-to-Analog Con- verter (DAC) Module and Section 10.0 Fixed Volt- age Reference for more information on these modules. 2010-2011 Microchip Technology Inc. PIC16(L)F707 21.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. ...

Page 186

... Bit 0 other POR, BOR Resets IOCIF 0000 000x 0000 000x IOCBF0 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 CCP2IE 0000 ---0 0000 ---0 TMR1IF 0000 0000 0000 0000 CCP2IF 0000 ---0 0000 ---0 C 0001 1xxx 000q quuu 2010-2011 Microchip Technology Inc. ...

Page 187

... The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ISCPCLK pin is the clock input. For more information on ICSP refer to the PIC16F707/PIC16LF707 Specification (DS41405A). Note: The ICD 2 produces a V than the maximum V PIC16(L)F707. When using this program- ...

Page 188

... PIC16(L)F707 NOTES: DS41418B-page 188 2010-2011 Microchip Technology Inc. ...

Page 189

... PORTB instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- tended consequence of clearing the condition that set the RBIF flag. 2010-2011 Microchip Technology Inc. PIC16(L)F707 TABLE 23-1: OPCODE FIELD DESCRIPTIONS ...

Page 190

... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk 2010-2011 Microchip Technology Inc. ...

Page 191

... Status Affected: Z Description: AND the W register with register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 2010-2011 Microchip Technology Inc. BCF Syntax: k Operands: Operation: Status Affected: ...

Page 192

... Operands: d [0,1] ( (destination) Operation: Status Affected: Z Description: Decrement register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 2010-2011 Microchip Technology Inc. ...

Page 193

... Description: The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. 2010-2011 Microchip Technology Inc. PIC16(L)F707 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0  ...

Page 194

... MOVWF f 0 f 127 (W) (f) None Move data from W register to register f’ MOVW OPTION F Before Instruction OPTION 0xFF W 0x4F After Instruction OPTION 0x4F W 0x4F No Operation [ label ] NOP None No operation None No operation NOP 2010-2011 Microchip Technology Inc. ...

Page 195

... Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC TOS GIE 1 2010-2011 Microchip Technology Inc. PIC16(L)F707 RETLW Return with literal in W Syntax: [ label ] RETLW k 0 k 255 Operands: k (W); Operation: TOS PC Status Affected: None ...

Page 196

... SUBLW k 0 k 255 k - (W) W) The W register is subtracted (2s complement method) from the eight-bit literal k. The result is placed in the W register. W   W<3:0> k<3:0> W<3:0> k<3:0> 2010-2011 Microchip Technology Inc. ...

Page 197

... The upper and lower nibbles of register f are exchanged. If d is 0, the result is placed in the W register. If d is 1, the result is placed in register f. 2010-2011 Microchip Technology Inc. PIC16(L)F707 XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k 0  ...

Page 198

... PIC16(L)F707 NOTES: DS41418B-page 198 2010-2011 Microchip Technology Inc. ...

Page 199

... PICkit 3 Debug Express Device Programmers - PICkit 2 Programmer - MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 2010-2011 Microchip Technology Inc. 24.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

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... Support for the entire device instruction set ® standard HEX Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 2010-2011 Microchip Technology Inc. ...

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