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PIC16LF722A Datasheet

Download or read online Microchip Technology PIC16LF722A 28-Pin Flash Microcontrollers With NanoWatt XLP Technology pdf datasheet.



Summary of Contents

Page 1

... Flash Microcontrollers with 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Data Sheet nanoWatt XLP Technology DS41417B ...

Page 2

... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010-2012, Microchip Technology Incorporated, Printed in the U ...

Page 3

... Factory calibrated to ±1%, typical - Software tunable - Software selectable ÷1, ÷2, ÷4 or ÷8 divider 1.8V-5.5V Operation PIC16F722A/723A 1.8V-3.6V Operation PIC16LF722A/723A Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Brown-out Reset (BOR): - Selectable between two trip points - Disable in Sleep option • ...

Page 4

... PIC16(L)F722A/723A Program Memory SRAM Device Flash (bytes) (words) PIC16F722A/ 2048 128 PIC16LF722A PIC16F723A/ 4096 192 PIC16LF723A Note 1: One pin is input-only. DS41417B-page 4 8-bit A/D (1) I/Os Interrupts AUSART (ch 2010-2012 Microchip Technology Inc. Timers CCP 8/16-bit Yes 2 2/1 Yes 2 2/1 ...

Page 5

... PIC16F722A/723A PIC16LF722A/723A RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/CPS5/T1G RB4/AN11/CPS4 (1) RB3/AN9/CPS3/CCP2 RB2/AN8/CPS2 RB1/AN10/CPS1 RB0/AN12/CPS0/INT RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA (1) RB3/AN9/CPS3/CCP2 RB2/AN8/CPS2 RB1/AN10/CPS1 RB0/AN12/CPS0/INT RC7/RX/DT ...

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... For more information, see CAP Regulator. The PIC16LF722A/723A devices do not have the Interrupt Pull-Up Basic (4) V CAP ...

Page 7

... Appendix A: Data Sheet Revision History... 275 ® Appendix B: Migrating From Other PIC Devices... 275 The Microchip Web Site ... 283 Customer Change Notification Service ... 283 Customer Support ... 283 Reader Response ... 284 Product Identification System ... 285 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A DS41417B-page 7 ...

Page 8

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41417B-page 8 to receive the most current information on all of our products. 2010-2012 Microchip Technology Inc. ...

Page 9

... DEVICE OVERVIEW The PIC16(L)F722A/723A devices are covered by this data sheet. They are available in 28-pin packages. Figure 1-1 shows a block diagram PIC16(L)F722A/723A devices. Table 1-1 pinout descriptions. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A of the shows the DS41417B-page 9 ...

Page 10

... RC4 RC5 RC6 RC7 PORTE RE3 SDI/ SCK/ SDI/ SCK/ SDI/ SCK/ SDO SDO SDO SDA SCL SDA SCL SDA SCL Synchronous Synchronous Synchronous Serial Port Serial Port Serial Port Capacitive Sensing Module CPS7 CPS6 2010-2012 Microchip Technology Inc. ...

Page 11

... RB3/AN9/CPS3/CCP2 RB3 AN9 CPS3 CCP2 Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input High Voltage XTAL Crystal levels 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Input Output Type Type TTL CMOS General purpose I/O. AN A/D Channel 0 input. ...

Page 12

... General purpose input. ST Master Clear with internal pull-up. HV Programming voltage. Power Positive supply. Power Ground reference. Schmitt Trigger input with CMOS levels I Description OD Open Drain 2 2 C Schmitt Trigger input with I C 2010-2012 Microchip Technology Inc. ...

Page 13

... V Section 5.0 Low Dropout (LDO) Voltage voltage regulator and therefore no external capacitor is required. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A pins to stabilize the regulator. For more information, see CAP Regulator. The PIC16LF722A/723A devices do not have the DS41417B-page 13 ...

Page 14

... PIC16(L)F722A/723A NOTES: DS41417B-page 14 2010-2012 Microchip Technology Inc. ...

Page 15

... RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector Interrupt Vector On-chip Program Page 0 Memory Wraps to Page 0 Wraps to Page 0 Wraps to Page 0 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A FIGURE 2-2: CALL, RETURN RETFIE, RETLW On-chip Program Memory 0000h 0004H 0005h 07FFh 0800h ...

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... The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the core are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. 2010-2012 Microchip Technology Inc. Table 2-1). ...

Page 17

... Register 32 Bytes General Purpose Register 96 Bytes Accesses 70h-7Fh 7Fh Bank 0 Bank 1 Legend: Unimplemented data memory locations, read as 0’ Not a physical register. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A () () 80h Indirect addr. 100h 81h TMR0 101h 82h PCL 102h 83h STATUS ...

Page 18

... A0h General Purpose 120h Register 16 Bytes 12Fh 130h EFh 16Fh F0h Accesses 170h 70h-7Fh FFh 17Fh Bank 2 2010-2012 Microchip Technology Inc. File Address () Indirect addr. 180h OPTION 181h PCL 182h STATUS 183h FSR 184h ANSELA 185h ANSELB 186h 187h ...

Page 19

... These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> 1001. Accessible only when SSPM<3:0> 1001 This bit is always 1 as RE3 is input only. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO PD ...

Page 20

... WPUB1 WPUB0 1111 1111 57,35 IOCB1 IOCB0 58,35 0000 0000 TRMT TX9D 142,35 0000 -010 BRG1 BRG0 144,35 0000 0000 SSSEL CCP2SEL ---- --00 47,35 ADFVR1 ADFVR0 97,35 q0-- --00 ADREF1 ADREF0 0000 --00 93,35 2010-2012 Microchip Technology Inc. ...

Page 21

... These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> 1001. Accessible only when SSPM<3:0> 1001 This bit is always 1 as RE3 is input only. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Bit 5 Bit 4 Bit 3 Bit 2 RP0 — ...

Page 22

... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1 R Unimplemented bit, read as 0 0 Bit is cleared (ADDWF, ADDLW, SUBLW, SUBWF instructions) Section 21.0 Summary). R/W-x R/W-x R/W-x (1) ( bit Bit is unknown (1) (1) 2010-2012 Microchip Technology Inc. ...

Page 23

... Bit Value Timer0 Rate 000 001 010 011 100 101 110 111 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Note: To achieve a 1:1 prescaler assignment for 2- Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to 1. Refer to Prescaler. R/W-1 ...

Page 24

... A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Note 1: Set BOREN<1:0> the Configuration Word register for this bit to control the BOR. DS41417B-page 24 2-3. U-0 U-0 U-0 — Unimplemented bit, read as 0 0 Bit is cleared 2010-2012 Microchip Technology Inc. R/W-q R/W-q POR BOR bit Bit is unknown ...

Page 25

... PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on). 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. ...

Page 26

... BTFSSFSR,4 ;all done? GOTONEXT CONTINUE 2-6. 2-2. 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 2-3 and 2-4. INDIRECT ADDRESSING ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;no clear next ;yes continue Indirect Addressing 7 0 File Select Register Location Select 1FFh 2010-2012 Microchip Technology Inc. ...

Page 27

... CLKIN PWRT 11-bit Ripple Counter WDTOSC Note 1: Refer to the Configuration Word Register 1 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal between operation. TO and PD bits are set or cleared differently ...

Page 28

... If a Status bit is not implemented, that bit will be read as 0. DS41417B-page 28 Condition (2) Program STATUS Counter Register 0000h 0001 1xxx ---- --0x 0000h 000u uuuu ---- --uu 0000h 0001 0uuu ---- --uu 0000h 0000 1uuu ---- -- uuu0 0uuu ---- --uu 0000h 0001 1uuu ---- --u0 ( uuu1 0uuu ---- --uu 2010-2012 Microchip Technology Inc. PCON Register ...

Page 29

... If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, Power-up Trouble Shooting (DS00607). 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 3.3 Power-up Timer (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset ...

Page 30

... Exit Sleep System Clock T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep System Clock XT, HS, LP DS41417B-page 30 From TMR0 Clock Source 0 Postscaler Divide by 1 512 0 PSA To T1G WDTE Cleared until the end of OST 2010-2012 Microchip Technology Inc. 8 PS<2:0> TO TMR0 1 WDT Reset WDT Cleared ...

Page 31

... Internal Reset V DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to 0. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A If V falls below V for greater than parameter DD BOR (T ) (see Section 23.0 Electrical Specifica- BOR tions), the brown-out situation will reset the device. ...

Page 32

... T PWRT Condition Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep may have DD Section 3.5 Brown-Out Wake-up from Sleep PWRTE 1 1024 T 1024 T OSC OSC 2010-2012 Microchip Technology Inc. ...

Page 33

... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A T PWRT T OST T PWRT T OST DD T PWRT T OST ): CASE 3 ...

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... Microchip Technology Inc. ...

Page 35

... See Table 3-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A MCLR Reset/ (1) WDT Reset 1111 1111 1111 1111 1111 1111 ...

Page 36

... uuu0 0uuu 0000h 0001 1xxx ( uuu1 0uuu unimplemented bit, reads as 0. - Bit 5 Bit 4 Bit 3 Bit 2 RP0 PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu Register on Bit 1 Bit 0 Page POR BOR 24 2010-2012 Microchip Technology Inc. ...

Page 37

... IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 TMR1GIF TMR1GIE 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The PIC16(L)F722A/723A device family has 12 interrupt sources, differentiated by corresponding interrupt enable and flag bits: Timer0 Overflow Interrupt External Edge Detect on INT Pin Interrupt PORTB Change Interrupt • ...

Page 38

... Interrupt Latency Inst ( Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency where Section 23.0 Electrical Figure 4 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) instruction cycle time. Latency CY Specifications. 2010-2012 Microchip Technology Inc. ...

Page 39

... MOVWFSTATUS ;Move W into STATUS register SWAPFW_TEMP,F ;Swap W_TEMP SWAPFW_TEMP,W ;Swap W_TEMP into W 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and PCLATH registers. Note: The microcontroller does not normally require saving the PCLATH register. However, if computed GOTO’ ...

Page 40

... GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1) (2) INTE RBIE T0IF U Unimplemented bit, read as 0 0 Bit is cleared (1) (2) 2010-2012 Microchip Technology Inc. R/W-0 R/W-x INTF RBIF bit Bit is unknown ...

Page 41

... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...

Page 42

... Enables the CCP2 interrupt 0 Disables the CCP2 interrupt DS41417B-page 42 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. U-0 U-0 U-0 — Unimplemented bit, read as 0 0 Bit is cleared 2010-2012 Microchip Technology Inc. U-0 R/W-0 CCP2IE bit Bit is unknown ...

Page 43

... A Timer2 to PR2 match occurred (must be cleared in software Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 The TMR1 register overflowed (must be cleared in software The TMR1 register did not overflow 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A ensure the R-0 R/W-0 ...

Page 44

... CCP1IE RCIF TXIF SSPIF CCP1IF U-0 U-0 R/W-0 CCP2IF bit Bit is unknown Register on Bit 1 Bit 0 Page INTF RBIF 40 PS1 PS0 23 TMR2IE TMR1IE 41 CCP2IE 42 TMR2IF TMR1IF 43 CCP2IF 44 2010-2012 Microchip Technology Inc. ...

Page 45

... The PIC16F722A/723A devices differ from the PIC16LF722A/723A devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F722A/ 723A contain an internal LDO, while the PIC16LF722A/ 723A do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5 ...

Page 46

... PIC16(L)F722A/723A NOTES: DS41417B-page 46 2010-2012 Microchip Technology Inc. ...

Page 47

... SSSEL: SS Input Pin Selection bit function is on RA5/AN4/CPS7/SS function is on RA0/AN0/SS/V bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 CCP2 function is on RC1/T1OSI/CCP2 1 CCP2 function is on RB3/CCP2 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A U-0 U-0 U-0 — Unimplemented bit, read as 0 ...

Page 48

... Bit is cleared R/W-1 R/W-1 TRISA4 TRISA3 TRISA2 U Unimplemented bit, read as 0 0 Bit is cleared INITIALIZING PORTA ; ;Init PORTA ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<7:4,1:0> ;as outputs R/W-x R/W-x R/W-x RA2 RA1 RA0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISA1 TRISA0 bit Bit is unknown 2010-2012 Microchip Technology Inc. ...

Page 49

... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R/W-1 R/W-1 R/W-1 ...

Page 50

... Clock output Voltage regulator capacitor pin (PIC16F722A/ 723A only) 6.2.2.8 RA7/OSC1/CLKIN Figure 6-6 shows the diagram for this pin. This pin is configurable to function as one of the following: General purpose I/O Crystal/resonator connection Clock input 2010-2012 Microchip Technology Inc. CAP ...

Page 51

... FIGURE 6-1: BLOCK DIAGRAM OF RA0 PIC16F722A/723A only To Voltage Regulator VCAPEN 00 Data Bus PORTA TRISA RD TRISA ANSA0 RD PORTA TO SSP SS Input 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A A/D Converter V DD I/O Pin V SS DS41417B-page 51 ...

Page 52

... CK Q PORTA TRISA RD TRISA ANSAx RD PORTA FIGURE 6-3: BLOCK DIAGRAM OF RA4 Data Bus PORTA TRISA RD TRISA ANSA4 RD PORTA To Timer0 Clock MUX To Cap Sensor DS41417B-page I/O Pin A/D Converter V DD I/O Pin V SS 2010-2012 Microchip Technology Inc. ...

Page 53

... FIGURE 6-4: BLOCK DIAGRAM OF RA5 PIC16F722A/723A only VCAPEN 01 Data Bus PORTA TRISA RD TRISA ANSA5 RD PORTA To SSP SS Input 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A To Voltage Regulator To A/D Converter To Cap Sensor V DD I/O Pin V SS DS41417B-page 53 ...

Page 54

... Note 1: CLKOUT Enable 1 when F OSC FIGURE 6-6: BLOCK DIAGRAM OF RA7 Data Bus PORTA TRISA RD TRISA OSC INTOSC or INTOSCIO RD PORTA DS41417B-page 54 RA7/OSC1 INTOSC (No I/O Selected). RA6/OSC2 Oscillator Circuit V DD I/O Pin V SS Oscillator Circuit V DD I/O Pin V SS 2010-2012 Microchip Technology Inc. ...

Page 55

... Bit -/6 (1) CONFIG2 13:8 7:0 Legend: unimplemented location, read as 0. Shaded cells are not used by clock sources. Note 1: PIC16F722A/723A only. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 ...

Page 56

... RBIF flag will always be set. If multiple PORTB pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state. (Register 6-9) is used to executing read-modify-write Register 6-7). Each weak pull- The interrupt-on-change feature is 2010-2012 Microchip Technology Inc. ...

Page 57

... WPUB<7:0>: Weak Pull-up Register bits 1 Pull-up enabled 0 Pull-up disabled Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R/W-x R/W-x R/W-x RB4 RB3 RB2 U Unimplemented bit, read as ‘ ...

Page 58

... U Unimplemented bit, read as 0 0 Bit is cleared R/W-1 R/W-1 R/W-1 ANSB4 ANSB3 ANSB2 U Unimplemented bit, read as 0 0 Bit is cleared (1) . Digital input buffer disabled. 2010-2012 Microchip Technology Inc. R/W-0 R/W-0 IOCB1 IOCB0 bit Bit is unknown R/W-1 R/W-1 ANSB1 ANSB0 bit Bit is unknown ...

Page 59

... This pin is configurable to function as one of the following: General purpose I/O Analog input for the ADC Capacitive sensing input 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 6.3.4.6 RB5/AN13/CPS5/T1G Figure 6-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • ...

Page 60

... CK Q WPUB RD WPUB PORTB TRISB RD TRISB ANSB0 RD PORTB IOCB RD IOCB Interrupt-on- Change RD PORTB To External Interrupt Logic DS41417B-page 60 RBPU A/D Converter To Cap Sensor 2010-2012 Microchip Technology Inc Weak V DD I/O Pin V SS ...

Page 61

... WPUB RD WPUB PORTB TRISB RD TRISB ANSB<4,2,1> RD PORTB IOCB RD IOCB Interrupt-on- Change 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A RBPU A/D Converter Cap Sensor EN RD PORTB V DD Weak V DD I/O Pin V SS DS41417B-page 61 ...

Page 62

... PORTB IOCB RD IOCB Interrupt-on- Change (1) To CCP2 Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register. DS41417B-page 62 CCP2OUT Enable RBPU CCP2OUT PORTB To A/D Converter To Cap Sensor V DD Weak V DD I/O Pin V SS 2010-2012 Microchip Technology Inc. ...

Page 63

... CK Q PORTB TRISB RD TRISB ANSB<5,3> RD PORTB IOCB RD IOCB Interrupt-on- Change To Timer1 Gate 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A CCP2OUT Enable RBPU CCP2OUT PORTB To A/D Converter To Cap Sensor V DD Weak V DD I/O Pin V SS ...

Page 64

... Data Bus WPUB RD WPUB PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change ICSPCLK DS41417B-page 64 RBPU PORT_ICDCLK TRIS_ICDCLK PORTB V DD Weak V DD I/O Pin V SS 2010-2012 Microchip Technology Inc. ...

Page 65

... CK Q WPUB RD WPUB PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change ICSPDAT_IN 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A RBPU PORT_ICDDAT TRIS_ICDDAT PORTB V DD Weak V DD I/O Pin V SS DS41417B-page 65 ...

Page 66

... WPUB3 WPUB2 Register Bit 1 Bit 0 on Page GO/ ADON 92 DONE ANSB1 ANSB0 58 SSSEL CCP2SEL 47 CCP2M1 CCP2M0 124 T0XCS 121 CPSCH1 CPSCH0 122 INTF RBIF 40 IOCB1 IOCB0 58 PS1 PS0 23 RB1 RB0 57 T1GSS1 T1GSS0 113 TRISB1 TRISB0 57 WPUB1 WPUB0 57 2010-2012 Microchip Technology Inc. ...

Page 67

... TRISC<7:0>: PORTC Tri-State Control bits 1 PORTC pin configured as an input (tri-stated PORTC pin configured as an output 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The TRISC register pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the ...

Page 68

... General purpose I/O Asynchronous serial output Synchronous clock I/O DS41417B-page 68 6.4.8 RC7/RX/DT Figure 6-20 shows the diagram for this pin. This pin is configurable to function as one of the following: General purpose I/O Asynchronous serial input Synchronous serial data I/O 2010-2012 Microchip Technology Inc. ...

Page 69

... PORTC TRISC RD TRISC T1OSCEN RD PORTC (1) To CCP2 Input Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Oscillator RC1/T1OSI RC0/T1OSO 1 0 Circuit V DD I/O Pin V SS Oscillator Circuit V DD I/O Pin V SS DS41417B-page 69 ...

Page 70

... SCL Input 2 Note Schmitt Trigger has special input levels. 2 ™ Slew Rate limiting controlled by SMP bit of SSPSTAT register. DS41417B-page SSPEN I/O Pin I/O Pin (1) ™ 2010-2012 Microchip Technology Inc. ...

Page 71

... Slew Rate limiting controlled by SMP bit of SSPSTAT register. FIGURE 6-18: BLOCK DIAGRAM OF RC5 SSPEN SSPM SPI Mode Data Bus SDO PORTC D Q SDO TRISC RD TRISC RD PORTC 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A I/O Pin (1) ™ I/O Pin V ...

Page 72

... Sync Clock Input FIGURE 6-20: BLOCK DIAGRAM OF RC7 SPEN SYNC Data Bus USART_DT PORTC TRISC RD TRISC RD PORTC SPEN SYNC TXEN SREN CREN To USART Data Input DS41417B-page I/O Pin I/O Pin V SS 2010-2012 Microchip Technology Inc. ...

Page 73

... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TXSTA CSRC TX9 TRISC TRISC7 TRISC6 Legend unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTB. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Bit 5 Bit 4 Bit 3 Bit 2 DC1B1 ...

Page 74

... U Unimplemented bit, read as 0 0 Bit is cleared Bit 4 Bit 3 Bit 2 RE3 (1) TRISE3 U-0 U-0 U-0 bit Bit is unknown U-0 U-0 U-0 bit Bit is unknown Register on Bit 1 Bit 0 Page 74 74 2010-2012 Microchip Technology Inc. ...

Page 75

... FIGURE 6-21: BLOCK DIAGRAM OF RE3 ICSP Mode Detect In-Circuit Serial Programming Mode MCLR Circuit MCLR Pulse Filter Data Bus RD TRISE PORTE 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A V DD Weak High-Voltage Detect I/O Pin V SS Power for Programming Flash DS41417B-page 75 ...

Page 76

... PIC16(L)F722A/723A NOTES: DS41417B-page 76 2010-2012 Microchip Technology Inc. ...

Page 77

... Internal Oscillator 500 kHz 0 32x 1 PLL PLLEN (Configuration Word 1) 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation External Resistor-Capacitor (RC) with F /4 output on OSC2/CLKOUT ...

Page 78

... IRCF bits takes effect. This is because the old and new frequencies are derived from INTOSC via the postscaler and multiplexer. Start-up delay specifications are located in in Section 23.0 Electrical for more Figure 7-1). The Table 23-2 Specifications. 2010-2012 Microchip Technology Inc. ...

Page 79

... ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy bit 1-0 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A (Figure 7-1) clock. ...

Page 80

... Code execution continues during this shift. There is no indication that the shift has occurred. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U Unimplemented bit, read as 0 0 Bit is cleared 2010-2012 Microchip Technology Inc. R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown ...

Page 81

... LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes ...

Page 82

... Alternate pin functions are described in Section 6.1 Alternate Pin Function. Output depends upon RC or RCIO clock mode. ) and capacitor (C ) values EXT EXT Register Bit 1 Bit 0 on Page 79 TUN1 TUN0 80 Register Bit 10/2 Bit 9/1 Bit 8/0 on Page BORV BOREN1 BOREN0 83 FOSC<2:0> 2010-2012 Microchip Technology Inc. ...

Page 83

... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. ® 4: MPLAB IDE masks unimplemented Configuration bits to 0. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 8.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. ...

Page 84

... R Readable bit W Writable bit -n Value at POR 1 Bit is set bit 13-6 Unimplemented: Read as 1 bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits For the PIC16LF722A/723A: These bits are ignored. All V For the PIC16F722A/723A functionality is enabled on RA0 CAP functionality is enabled on RA5 ...

Page 85

... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB IDE. PIC16F72X/PIC16LF72X Memory Specification (DS41332) for more information. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A not been Specification See the Programming DS41417B-page 85 ...

Page 86

... PIC16(L)F722A/723A NOTES: DS41417B-page 86 2010-2012 Microchip Technology Inc. ...

Page 87

... REF AN0 AN1 AN2 AN3 AN4 Reserved Reserved Reserved AN8 AN9 AN10 AN11 AN12 AN13 Reserved FV REF CHS<3:0> 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A (ADC) allows shows the AV DD ADREF 0x ADREF 11 ADREF 10 0000 0001 0010 0011 0100 0101 0110 0111 ...

Page 88

... ADC clock selections. Note: Unless using the F system clock frequency will change the ADC adversely affect the ADC result. Section 6.0 Section 9 external periods AD specifica- AD for Table 9-1 gives examples of appro- , any changes in the RC clock frequency, which may 2010-2012 Microchip Technology Inc. ...

Page 89

... Tcy Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz 8 MHz (2) (2) 100 ns 125 ns 250 ns ...

Page 90

... Using the Special Event Trigger does not assure proper ADC timing the users responsibility to ensure that the ADC timing requirements are met. Refer to Section 15.0 (CCP) Module for more information. 2010-2012 Microchip Technology Inc. RC clock source is selected, the RC Capture/Compare/PWM ...

Page 91

... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 9.3 A/D Acquisition Requirements. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A EXAMPLE 9-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ...

Page 92

... A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 ADC is enabled 0 ADC is disabled and consumes no operating current DS41417B-page 92 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U Unimplemented bit, read as 0 0 Bit is cleared ) REF 2010-2012 Microchip Technology Inc. R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown ...

Page 93

... ADRES5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits 8-bit conversion result. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R/W-0 U-0 U-0 ADCS0 U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 94

... HOLD Equation 9-1 may be used. This 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED 2010-2012 Microchip Technology Inc. ...

Page 95

... T Note 1: Refer to Section 23.0 Electrical Specifications FIGURE 9-4: ADC TRANSFER FUNCTION FFh FEh FDh FCh FBh 04h 03h 02h 01h 00h V SS 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A V DD Sampling Switch 0.  Rss R IC LEAKAGE (1) I 0. ...

Page 96

... CCP1IF TRISA5 TRISA4 TRISA3 TRISA2 TRISB5 TRISB4 TRISB3 TRISB2 Register Bit 1 Bit 0 on Page GO/ ADON 92 DONE ADREF1 ADREF0 93 ANSA1 ANSA0 49 ANSB1 ANSB0 58 93 124 ADFVR1 ADFVR0 97 INTF RBIF 40 TMR2IE TMR1IE 41 TMR2IF TMR1IF 43 TRISA1 TRISA0 48 TRISB1 TRISB0 57 2010-2012 Microchip Technology Inc. ...

Page 97

... A/D Converter Fixed Voltage Reference Peripheral output is off A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V) Note 1: Fixed Voltage Reference output cannot exceed V 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 10-1. U-0 U-0 U-0 — ...

Page 98

... PIC16(L)F722A/723A NOTES: DS41417B-page 98 2010-2012 Microchip Technology Inc. ...

Page 99

... T0SE Oscillator T1GSS 11 TMR1GE WDTE Low-Power WDT OSC 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...

Page 100

... T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 23.0 Electrical Specifications. DS41417B-page 100 2010-2012 Microchip Technology Inc. ...

Page 101

... TMR0 Timer0 Module Register TRISA TRISA7 TRISA6 Legend: – implemented locations, read as 0’ unchanged unknown. Shaded cells are not used by the Timer0 module. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R/W-1 R/W-1 T0SE PSA U Unimplemented bit, read as 0 0 Bit is cleared ...

Page 102

... PIC16(L)F722A/723A NOTES: DS41417B-page 102 2010-2012 Microchip Technology Inc. ...

Page 103

... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Selectable Gate Source Polarity Gate Toggle Mode Gate Single-pulse Mode • ...

Page 104

... T1CKI is high then Timer1 is enabled (TMR1ON1) when T1CKI is low. T1OSCEN System Clock ( OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator 0 External Clocking on T1CKI Pin Oscillator Circuit on T1OSI/T1OSO Pins 1 system clock or they can run Clock Source /4) 2010-2012 Microchip Technology Inc. ...

Page 105

... When switching from synchronous to asynchronous operation possible to skip an increment. When switching from asynchronous to synchronous operation possible to produce an additional increment. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 12.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...

Page 106

... WDT is enabled, when the CLRWDT instruction is executed, and so on, Toggle mode must be used. A specific sequence is required to put the device into the correct state to capture the next WDT counter interval. 2010-2012 Microchip Technology Inc. Table 12-5. ...

Page 107

... This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A WDT Oscillator WDT Reset Enable Y Y ...

Page 108

... Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 9.2.5 Special Event Trigger. 2010-2012 Microchip Technology Inc utilize OSC ...

Page 109

... TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 12-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A DS41417B-page 109 ...

Page 110

... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41417B-page 110 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL 2010-2012 Microchip Technology Inc. Cleared by software ...

Page 111

... T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Cleared by software DS41417B-page 111 ...

Page 112

... Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 (Clears Timer1 gate flip-flop) DS41417B-page 112 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U Unimplemented bit, read as 0 0 Bit is cleared ) OSC /4) OSC ) OSC 2010-2012 Microchip Technology Inc. U-0 R/W-0 TMR1ON bit Bit is unknown ...

Page 113

... T1GSS<1:0>: Timer1 Gate Source Select bits 00 Timer1 gate pin 01 Timer0 Overflow output 10 TMR2 Match PR2 output 11 Watchdog Timer scaler overflow Watchdog Timer oscillator is turned on if TMR1GE 1, regardless of the state of TMR1ON 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R/W-0 R/W-0 R-x T1GSPM T1GGO/ T1GVAL DONE U Unimplemented bit, read as ‘ ...

Page 114

... TRISC3 TRISC2 T1GTM T1GSPM T1GGO/ T1GVAL DONE Register Bit 1 Bit 0 on Page ANSB1 ANSB0 58 124 124 INTF RBIF 40 TMR2IE TMR1IE 41 TMR2IF TMR1IF 43 RB1 RB0 57 108 108 TRISB1 TRISB0 57 TRISC1 TRISC0 67 TMR1ON 112 T1GSS1 T1GSS0 113 2010-2012 Microchip Technology Inc. ...

Page 115

... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...

Page 116

... Bit 3 Bit 2 T0IE INTE RBIE T0IF RCIE TXIE SSPIE CCP1IE RCIF TXIF SSPIF CCP1IF R/W-0 R/W-0 R/W-0 TMR2ON T2CKPS1 T2CKPS0 bit Bit is unknown Register Bit 1 Bit 0 on Page INTF RBIF 40 41 TMR2IE TMR1IE 43 TMR2IF TMR1IF 115 115 116 2010-2012 Microchip Technology Inc. ...

Page 117

... LP WDT WDT OSC Scaler PS<2:0> Note 1: If CPSON 0, disabling capacitive sensing, no channel is selected. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • ...

Page 118

... Refer to Section 12.0 Timer1 Module with Gate Control additional information. TABLE 14-1: TIMER1 ENABLE FUNCTION TMR1ON TMR1GE Timer1 Operation Count Enabled by input 1 1 2010-2012 Microchip Technology Inc. for for Off Off On ...

Page 119

... This frequency should be less than the value obtained during the nominal frequency measurement. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 14.5.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator ...

Page 120

... Timer1, any other source that wakes the part up early will cause the WDT over- flow to be delayed, affecting the value captured by Timer1. 2: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements Sleep. DS41417B-page 120 in 2010-2012 Microchip Technology Inc. ...

Page 121

... The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0 Timer0 Clock Source is the capacitive sensing oscillator 0 Timer0 Clock Source is the T0CKI pin If T0CS 0 Timer0 clock source is controlled by the core/Timer0 module and is F 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A U-0 R/W-0 R/W-0 — ...

Page 122

... TRISA4 TRISA3 TRISA2 TRISB5 TRISB4 TRISB3 TRISB2 R/W-0 R/W-0 CPSCH1 CPSCH0 bit Bit is unknown Register Bit 1 Bit 0 on Page ANSA1 ANSA0 49 ANSB1 ANSB0 58 PS1 PS0 23 TMR2IE TMR1IE 41 TMR2IF TMR1IF 43 TMR1ON 112 116 TRISA1 TRISA0 48 TRISB1 TRISB0 57 2010-2012 Microchip Technology Inc. ...

Page 123

... If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1, affecting the value captured on the CCP1 pin. Note: CCPRx and CCPx throughout document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A TABLE 15-1: CCP MODE TIMER RESOURCES REQUIRED CCP Mode Capture Compare PWM ...

Page 124

... Note 1: A/D conversion start feature is available only on CCP2. DS41417B-page 124 R/W-0 R/W-0 R/W-0 DCxB0 CCPxM3 CCPxM2 U Unimplemented bit, read as 0 0 Bit is cleared (1) is started if the ADC module is enabled. CCPx pin is unaffected.) 2010-2012 Microchip Technology Inc. R/W-0 R/W-0 CCPxM1 CCPxM0 bit Bit is unknown ...

Page 125

... Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode or when Timer1 is clocked the capture operation may OSC not work. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 15.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts ...

Page 126

... TRISC2 Register Bit 1 Bit 0 on Page ANSB1 ANSB0 58 SSSEL CCP2SEL 47 124 124 125 125 INTF RBIF 40 TMR2IE TMR1IE 41 CCP2IE 42 TMR2IF TMR1IF 43 CCP2IF 44 TMR1ON 112 T1GSS1 T1GSS0 113 108 108 TRISB1 TRISB0 57 TRISC1 TRISC0 67 2010-2012 Microchip Technology Inc. ...

Page 127

... Note: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 15.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...

Page 128

... Bit 0 on Page GO/ ADON 92 DONE ANSB1 ANSB0 58 SSSEL CCP2SEL 47 CCP1M0 124 CCP2M0 124 125 125 INTF RBIF 40 TMR2IE TMR1IE 41 CCP2IE 42 TMR2IF TMR1IF 43 CCP2IF 44 TMR1ON 112 T1GSS0 113 108 108 TRISB1 TRISB0 57 TRISC1 TRISC0 67 2010-2012 Microchip Technology Inc. ...

Page 129

... In PWM mode, CCPRxH is a read-only register. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The PWM output (period) and a time that the output stays high (duty cycle). ...

Page 130

... When the 10-bit time base matches the CCPRxH and (refer to 2-bit latch, then the CCPx pin is cleared (refer to Figure 15-3). PULSE WIDTH CCPRxL:CCPxCON<5:4> T (TMR2 Prescale Value) OSC 1/F OSC DUTY CYCLE RATIO CCPRxL:CCPxCON<5:4> ---------------------------------------------------------------------- - 4 PR2 bits of OSC 2010-2012 Microchip Technology Inc. ...

Page 131

... Refer to Section 7.0 Oscillator Module additional details. 15.3.7 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A EQUATION 15-4: PWM RESOLUTION Resolution Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged ...

Page 132

... DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 TRISB4 TRISB3 TRISB2 TRISC4 TRISC3 TRISC2 Register Bit 1 Bit 0 on Page ANSB1 ANSB0 58 SSSEL CCP2SEL 47 124 124 125 125 115 116 115 TRISB1 TRISB0 57 TRISC1 TRISC0 67 2010-2012 Microchip Technology Inc. ...

Page 133

... Multiplier x4 SYNC 1 SPBRG BRGH x 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The AUSART module includes the following capabilities: Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Synchronous Address detection in 9-bit mode (AUSART) • ...

Page 134

... DS41417B-page 134 MSb Data Stop Recovery F OSC ÷ x16 x64 FERR and CREN OERR RSR Register LSb ( START RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE 2010-2012 Microchip Technology Inc. ...

Page 135

... TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the TX/CK I/O pin as an output. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, ...

Page 136

... PEIE bits of the INTCON register are also set 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 2010-2012 Microchip Technology Inc. Stop bit ...

Page 137

... TRISC6 TRISC5 TXREG AUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as 0. Shaded cells are not used for Asynchronous Transmission. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A bit 0 bit 1 bit 7/8 Word Bit 4 Bit 3 Bit 2 ...

Page 138

... INTCON register GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit of the PIR1 register will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 2010-2012 Microchip Technology Inc. Receive Refer to Overrun ...

Page 139

... FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 16.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...

Page 140

... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG 2010-2012 Microchip Technology Inc. Start bit Stop bit 7/8 bit ...

Page 141

... BRG6 BRG5 TRISC TRISC7 TRISC6 TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as 0. Shaded cells are not used for Asynchronous Reception. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF TXIE SSPIE ...

Page 142

... TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Synchronous mode. DS41417B-page 142 R/W-0 U-0 R/W-0 (1) SYNC BRGH U Unimplemented bit, read as 0 0 Bit is cleared (1) R-1 R/W-0 TRMT TX9D bit Bit is unknown 2010-2012 Microchip Technology Inc. ...

Page 143

... No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure TRISx 1. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R/W-0 R/W-0 R-0 CREN ...

Page 144

... Baud Rate Formula F /[64 (n1)] OSC F /[16 (n1)] OSC F /[4 (n1)] OSC Value on Value on Bit 0 all other POR, BOR Resets RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 2010-2012 Microchip Technology Inc. ...

Page 145

... Microchip Technology Inc. PIC16(L)F722A/723A SYNC 0, BRGH 18.432 MHz F 16.0000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) ...

Page 146

... F 1.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) 300 0.16 207 191 1202 0. 2404 0. 21 10417 0. 3 1 2010-2012 Microchip Technology Inc. ...

Page 147

... One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 16.3.1.2 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin ...

Page 148

... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 2010-2012 Microchip Technology Inc. ...

Page 149

... CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 16.3.1.7 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When ...

Page 150

... POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000X 0000 000X TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 2010-2012 Microchip Technology Inc. ...

Page 151

... CSRC TX9 TXEN Legend unknown unimplemented read as 0. Shaded cells are not used for Synchronous Slave Transmission. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. ...

Page 152

... POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000X 0000 000X TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 2010-2012 Microchip Technology Inc. ...

Page 153

... Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 0004h will be called. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 16.4.2 SYNCHRONOUS TRANSMIT DURING SLEEP ...

Page 154

... PIC16(L)F722A/723A NOTES: DS41417B-page 154 2010-2012 Microchip Technology Inc. ...

Page 155

... Shift Register (SSPSR) LSb MSb General I/O Processor 1 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A A typical SPI connection between microcontroller devices is shown in than one slave device is accomplished via multiple hardware slave select lines. External hardware and additional I/O pins must be used to support multiple slave select addressing ...

Page 156

... SSPBUF Reg SSPSR Reg SDI bit 0 bit 7 Shift Clock SDO SS Control RA5/SS Enable RA0/SS SSSEL 2 Clock Select Edge Select 2 Edge Select Prescaler SCK 4 TRISx SSPM<3:0> DS41417B-page 156 Internal Data Bus Write TMR2 Output F OSC 4, 16, 64 2010-2012 Microchip Technology Inc. ...

Page 157

... TRIS register as follows: SDI configured as input SDO configured as output SCK configured as output 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 17.1.1.3 Master Mode Setup In Master mode, the data is transmitted/received as soon as the SSPBUF register is loaded with a byte ...

Page 158

... MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA reg contents of TXDATA MOVWF SSPBUF ;New data to xmit DS41417B-page 158 bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 2 bit 1 bit 3 2010-2012 Microchip Technology Inc. 4 Clock Modes bit 0 bit 0 bit 0 bit 0 ...

Page 159

... A SPI module transmits and receives at the same time, occasionally causing dummy data to be transmitted/ received the user to determine which data used and what can be discarded. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 17.1.2.2 Enabling Slave I/O To enable the serial port, the SSPEN bit of the SSPCON register must be set ...

Page 160

... SCK (CKP 1 CKE 1) Write to SSPBUF SDO bit 7 SDI (SMP 0) bit 7 Input Sample (SMP 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41417B-page 160 bit 6 bit 5 bit 4 bit 2 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 2010-2012 Microchip Technology Inc. ...

Page 161

... SSPIF Interrupt Flag SSPSR to SSPBUF 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A When the SPI module resets, the bit counter is cleared to 0. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. shows the timing waveform for such a synchronization event ...

Page 162

... SPI Slave mode, clock SCK pin. SS pin control disabled. SS can be used as I/O pin. Note 1: When enabled, these pins must be properly configured as input or output. DS41417B-page 162 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U Unimplemented bit, read as 0 0 Bit is cleared /4 OSC /16 OSC /64 OSC 2010-2012 Microchip Technology Inc. R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (1) ...

Page 163

... UA: Update Address bit 2 Used mode only. bit 0 BF: Buffer Full Status bit 1 Receive complete, SSPBUF is full 0 Receive not complete, SSPBUF is empty 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R-0 R Unimplemented bit, read as 0 0 Bit is cleared ...

Page 164

... SSPM2 D R/W TRISA4 TRISA3 TRISA2 TRISC4 TRISC3 TRISC2 Register Bit 1 Bit 0 on Page ANSA1 ANSA0 49 SSSEL CCP2SEL 47 INTF RBIF 40 41 TMR2IE TMR1IE 43 TMR2IF TMR1IF 115 157 SSPM1 SSPM0 162 UA BF 163 TRISA1 TRISA0 48 TRISC1 TRISC0 67 116 2010-2012 Microchip Technology Inc. ...

Page 165

... Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect SSPADD Reg Start and Stop bit Detect 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A FIGURE 17-8: Master SDA SCL 2 C The SSP module has six registers for I They are: SSP Control (SSPCON) register • ...

Page 166

... SSPOV. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. Generate ACK Pulse Yes Yes Stop Condition shows the results of when a data Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes 2010-2012 Microchip Technology Inc. ...

Page 167

... An ACK pulse is generated. SSP interrupt flag bit, SSPIF of the PIR1 register, is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 17.2.4.2 10-bit Addressing In 10-bit Address mode, two address bytes need to be ...

Page 168

... Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. Receiving Data ACK Bus Master sends Stop condition ACK is not sent. 2010-2012 Microchip Technology Inc. ...

Page 169

Clock is held low until update of SSPADD has taken place Receive First Byte of Address Receive Second Byte of Address ACK R/W SDA SCL ...

Page 170

... Cleared in software SSPBUF is written in software From SSP Interrupt to clear BF flag Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Transmitting Data ACK Service Routine 2010-2012 Microchip Technology Inc. ...

Page 171

Clock is held low until update of SSPADD has taken place R Receive First Byte of Address Receive Second Byte of Address SDA ...

Page 172

... Refer to Application Note AN578, Use of the SSP Module in the I (DS00578) for more information bus may Note AN554, Software 2 C Bus Master (DS00554) for more 2 C Multi-Master Environment 2010-2012 Microchip Technology Inc. ...

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... SDA DX SCL CKP WR SSPCON 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 17.2.11 SLEEP OPERATION While in Sleep mode, the I addresses of data, and when an address match or C master device complete byte transfer occurs, wake the processor from Sleep (if SSP interrupt is enabled) ...

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... When enabled, these pins must be properly configured as input or output using the associated TRIS bit. DS41417B-page 174 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U Unimplemented bit, read as 0 0 Bit is cleared (1) 2010-2012 Microchip Technology Inc MODE) R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (2) ...

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... Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive Receive complete, SSPBUF is full 0 Receive not complete, SSPBUF is empty Transmit Transmit in progress, SSPBUF is full 0 Transmit complete, SSPBUF is empty 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R-0 R Unimplemented bit, read as 0 ...

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... Bit is unknown 2 C address match 2 C address match R/W-0 R/W-0 R/W-0 ADD2 ADD1 ADD0 bit Bit is unknown Register on Bit 1 Bit 0 Page INTF RBIF 40 TMR2IF TMR1IF 43 TMR2IE TMR1IE 41 157 165 SSPM1 SSPM0 174 176 UA BF 175 TRISC1 TRISC0 67 2010-2012 Microchip Technology Inc. ...

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... LOWPMBYTE; MOVF PMDATH, W Byte of Program Memory Read MOVWF HIGHPMBYTE; 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The value written to the PMADRH:PMADRL register pair determines which program memory location is read. The read operation will be initiated by setting the RD bit of the PMCON1 register. The program memory Flash controller takes two instructions to complete the read ...

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... R/W-x R/W-x PMD12 PMD11 PMD10 U Unimplemented bit, read as 0 0 Bit is cleared R/W-x R/W-x R/W-x PMD4 PMD3 PMD2 U Unimplemented bit, read as 0 0 Bit is cleared 2010-2012 Microchip Technology Inc. U-0 R/S-0 RD bit Bit is unknown R/W-x R/W-x PMD9 PMD8 bit Bit is unknown R/W-x R/W-x PMD1 ...

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... PMDATL Program Memory Read Data Register Low Byte Legend unknown unchanged, unimplemented, read as 0. Shaded cells are not used by the Program Memory Read. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A R/W-x R/W-x PMA12 PMA11 U Unimplemented bit, read as 0 ...

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... PIC16(L)F722A/723A NOTES: DS41417B-page 180 2010-2012 Microchip Technology Inc. ...

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... The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The following peripheral interrupts can wake the device from Sleep: 1. ...

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... CCP1IE TXIF SSPIF CCP1IF — 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page IOCB1 IOCB0 58 INTF RBIF 40 TMR2IE TMR1IE 41 CCP2IE 42 TMR2IF TMR1IF 43 CCP2IF 44 2010-2012 Microchip Technology Inc. ...

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... GND Data Clock 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/V Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications ...

Page 184

... PIC16(L)F722A/723A NOTES: DS41417B-page 184 2010-2012 Microchip Technology Inc. ...

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... PORTB instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- tended consequence of clearing the condition that set the RBIF flag. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A TABLE 21-1: OPCODE FIELD DESCRIPTIONS ...

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... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 0000 0110 0011 TO DC, Z 110x kkkk kkkk 1010 kkkk kkkk Z 2010-2012 Microchip Technology Inc. ...

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... Status Affected: Z Description: AND the W register with register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A BCF Syntax: k Operands: Operation: ...

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... Operands: d [0,1] ( (destination) Operation: Status Affected: Z Description: Decrement register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 2010-2012 Microchip Technology Inc. ...

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... Description: The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0  ...

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... MOVWF f 0 f 127 (W) (f) None Move data from W register to register f’ MOVW OPTION F Before Instruction OPTION 0xFF W 0x4F After Instruction OPTION 0x4F W 0x4F No Operation [ label ] NOP None No operation None No operation NOP 2010-2012 Microchip Technology Inc. ...

Page 191

... Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC TOS GIE 1 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A RETLW Return with literal in W Syntax: [ label ] RETLW k 0 k 255 Operands: k (W); Operation: TOS PC Status Affected: None ...

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... SUBLW k 0 k 255 k - (W) W) The W register is subtracted (2s complement method) from the eight-bit literal k. The result is placed in the W register. W   W<3:0> k<3:0> W<3:0> k<3:0> 2010-2012 Microchip Technology Inc. ...

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... The upper and lower nibbles of register f are exchanged. If d is 0, the result is placed in the W register. If d is 1, the result is placed in register f. 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k 0  ...

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... PIC16(L)F722A/723A NOTES: DS41417B-page 194 2010-2012 Microchip Technology Inc. ...

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... MPLAB ICD 3 - PICkit 3 Debug Express Device Programmers - PICkit 2 Programmer - MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 2010-2012 Microchip Technology Inc. PIC16(L)F722A/723A 22.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

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... Support for the entire device instruction set ® standard HEX Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 2010-2012 Microchip Technology Inc. ...

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... Microchip Technology Inc. PIC16(L)F722A/723A 22.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...

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... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® 2010-2012 Microchip Technology Inc. ...

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... V , PIC16F722A/723A ... -0.3V to 6. Voltage on V pin with respect to V CAP SS Voltage on V with respect PIC16LF722A/723A ... -0.3V to 4. Voltage on MCLR with respect to Vss ... -0.3V to 9.0V Voltage on all other pins with respect to V (1) Total power dissipation ... 800 mW Maximum current out of V pin ... 95 mA ...

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... D002 V RAM Data Retention Voltage DR PIC16LF722A/723A D002 PIC16F722A/723A V Power-on Reset Release Voltage POR V Power-on Reset Rearm Voltage PORR PIC16LF722A/723A PIC16F722A/723A D003 V Fixed Voltage Reference Voltage, FVR Initial Accuracy D004 Rise Rate to ensure internal VDD DD Power-on Reset signal These parameters are characterized but not tested. ...

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