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PIC16(L)F1824 Datasheet

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PIC16(L)F1824/1828
Data Sheet
14/20-Pin Flash Microcontrollers
with XLP Technology
 2010-2012 Microchip Technology Inc.
DS41419D

Summary of Contents

Page 1

... Flash Microcontrollers 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Data Sheet with XLP Technology DS41419D ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010-2012, Microchip Technology Incorporated, Printed in the U ...

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... Operating Voltage Range: - 1.8V-5.5V (PIC16F1824/1828) - 1.8V-3.6V (PIC16LF1824/1828) Programmable Code Protection Power-Saving Sleep mode 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Extreme Low-Power Management PIC16LF1824/1828 with XLP: Sleep mode 1.8V, typical Watchdog Timer: 200 nA @ 1.8V, typical Timer1 Oscillator: 650 kHz, 1.8V, typical • ...

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... PIC12(L)F1822/PIC16(L)F1823 Data Sheet, 8/14-Pin Flash Microcontrollers DS41441 PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers. DS41419 PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers DS41440 PIC16(L)F1825/1829 Data Sheet, 14/20-Pin Flash Microcontrollers. DS41391 PIC16(L)F1826/1827 Data Sheet, 18/20/28-Pin Flash Microcontrollers. ...

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... FIGURE 1: 14-PIN DIAGRAM FOR PIC16(L)F1824 PDIP, SOIC, TSSOP MCLR/V FIGURE 2: 16-PIN DIAGRAM FOR PIC16(L)F1824 QFN MCLR/V 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 RA5 RA0/ICSPDAT 13 2 RA4 RA1/ICSPCLK 12 3 /RA3 RA2 RC5 10 RC0 5 RC4 6 RC1 ...

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... PIC16(L)F1824/1828 TABLE 1: 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1824) RA0 13 12 AN0 V - CPS0 REF DACOUT RA1 12 11 AN1 V CPS1 REF RA2 11 10 AN2 CPS2 RA3 4 3 RA4 3 2 AN3 CPS3 RA5 2 1 ...

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... FIGURE 3: 20-PIN DIAGRAM FOR PIC16(L)F1828 PDIP, SOIC, SSOP MCLR/V FIGURE 4: PIC16(L)F1828 20-PIN QFN QFN MCLR/V 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 RA0/ICSPDAT RA5 19 2 RA4 RA1/ICSPCLK 18 3 /RA3 RA2 RC5 16 RC0 5 RC4 RC1 6 15 ...

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... PIC16(L)F1824/1828 TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F1828) RA0 19 16 AN0 V - CPS0 REF DACOUT RA1 18 15 AN1 V CPS1 REF RA2 17 14 AN2 CPS2 RA3 4 1 RA4 3 20 AN3 CPS3 RA5 2 19 RB4 13 10 AN10 — ...

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... Packaging Information... 421 Appendix A: Revision History... 441 Appendix B: Device Differences ... 441 Index ... 443 The Microchip Web Site ... 451 Customer Change Notification Service ... 451 Customer Support ... 451 Reader Response ... 452 Product Identification System ... 453 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 ) ... 335 DS41419D-page 9 ...

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... PIC16(L)F1824/1828 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...

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... DEVICE OVERVIEW The PIC16(L)F1824/1828 are described within this data sheet. They are available in 14/20 pin packages. Figure 1-1 shows a block diagram PIC16(L)F1824/1828 devices. Tables 1-2 the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral ADC Capacitive Sensing Module (CSM) ...

Page 12

... PIC16(L)F1824/1828 FIGURE 1-1: PIC16(L)F1824/1828 BLOCK DIAGRAM CLKR Clock Reference OSC2/CLKOUT Timing Generation OSC1/CLKIN INTRC Oscillator MCLR ADC Timer0 10-Bit SR ECCP1 Latch Note 1: See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. 2: PIC16(L)F1828 only. 3: DS41419D-page 12 ...

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... TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION Name Function RA0/AN0/CPS0/C1IN/V -/ RA0 REF (1) (1) DACOUT/TX /CK / AN0 ICSPDAT/ICDDAT CPS0 C1IN V REF DACOUT TX CK ICSPDAT ICDDAT RA1/AN1/CPS1/C12IN0-/V / RA1 REF (1) (1) SRI/RX /DT /ICSPCLK/ AN1 ICDCLK CPS1 C12IN0- V REF SRI RX DT ICSPCLK ICDCLK RA2/AN2/CPS2/T0CKI/INT/ RA2 C1OUT/SRQ/CCP3/FLT0 AN2 CPS2 ...

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... PIC16(L)F1824/1828 TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION (CONTINUED) Name Function RA4/AN3/CPS3/OSC2/ RA4 CLKOUT/T1OSO/CLKR/ AN3 (1) (1) (1,2) SDO /P2B /T1G CPS3 OSC2 CLKOUT T1OSO CLKR SDO P2B T1G RA5/CLKIN/OSC1/T1OSI/ RA5 (1) (1) T1CKI/P2A /CCP2 CLKIN OSC1 T1OSI T1CKI P2A CCP2 RC0/AN4/CPS4/C2IN/SCL/ RC0 (1) SCK/P1D ...

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... TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION (CONTINUED) Name Function RC3/AN7/CPS7/C12IN3-/ RC3 (1,2) (1,2) (1,2) P2A /CCP2 /P1C / AN7 (1,2) SS /MDMIN CPS7 C12IN3- P2A CCP2 P1C SS MDMIN (1,2) RC4/C2OUT/SRNQ/P1B/TX / RC4 (1,2) CK /MDOUT C2OUT SRNQ P1B TX CK MDOUT (1,2) (1,2) RC5/P1A/CCP1/RX /DT / RC5 MDCIN2 P1A CCP1 RX DT MDCIN2 Legend Analog input or output CMOS CMOS compatible input or output ...

Page 16

... PIC16(L)F1824/1828 TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION Name Function RA0/AN0/CPS0/C1IN/V -/ RA0 REF DACOUT/ICSPDAT/ICDDAT AN0 CPS0 C1IN V REF DACOUT ICSPDAT ICDDAT RA1/AN1/CPS1/C12IN0-/V / RA1 REF SRI/ICSPCLK/ICDCLK AN1 CPS1 C12IN0- V REF SRI ICSPCLK ICDCLK RA2/AN2/CPS2/T0CKI/INT/ RA2 C1OUT/SRQ/CCP3/FLT0 AN2 CPS2 T0CKI INT C1OUT SRQ CCP3 ...

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... Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input High Voltage XTAL Crystal Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers 2: Default function location. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Input Output Type Type TTL CMOS General purpose I/O. CMOS — ...

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... PIC16(L)F1824/1828 TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION (CONTINUED) Name Function RC3/AN7/CPS7/C12IN3-/ RC3 (1,2) (1,2) (1,2) P2A /CCP2 /P1C / AN7 MDMIN CPS7 C12IN3- P2A CCP2 P1C MDMIN (1) RC4/C2OUT/SRNQ/P1B/TX / RC4 (1) CK /MDOUT C2OUT SRNQ P1B TX CK MDOUT (1) (1) RC5/P1A/CCP1/RX /DT / RC5 MDCIN2 P1A CCP1 RX DT MDCIN2 RC6/AN8/CPS8/CCP4/SS ...

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... Section 3.5 Indirect Addressing 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 Instruction Set Summary details. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Saving, for more for more DS41419D-page 19 ...

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... PIC16(L)F1824/1828 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control OSC1/CLKIN Timing Timing ...

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... The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. implemented for the PIC16(L)F1824/1828 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is ...

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... PIC16(L)F1824/1828 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1824/1828 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 On-chip Program Memory Page 1 Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 1 DS41419D-page 22 3 ...

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... See Section 3.5 Addressing for more information. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These ...

Page 24

... PIC16(L)F1824/1828 3.2.1.1 STATUS Register The STATUS register, shown in Register the arithmetic status of the ALU the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...

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... DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-3. TABLE 3-3: Device PIC16(L)F1824 PIC16(L)F1828 BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM (80 bytes maximum) Common RAM ...

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TABLE 3-4: PIC16F1824/PIC16F1828 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...

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TABLE 3-5: PIC16F1824/PIC16F1828 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 480h INDF0 500h 400h 401h INDF1 481h INDF1 501h 402h PCL 482h PCL 502h 403h STATUS 483h STATUS 503h 404h FSR0L 484h FSR0L 504h 405h FSR0H 485h FSR0H ...

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... TABLE 3-6: PIC16(L)F1824/1828 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H 905h 806h FSR1L 886h ...

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... TABLE 3-7: PIC16(L)F1824/1828 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H D05h C06h FSR1L C86h ...

Page 30

... PIC16(L)F1824/1828 TABLE 3-8: PIC16(L)F1824/1828 MEMORY MAP, BANK 31 Bank 31 FA0h Unimplemented Read as 0 FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh FECh FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Unimplemented data memory locations, read as ‘ ...

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... Legend: Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 ...

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... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. DS41419D-page 32 Bit 5 Bit 4 Bit 3 — — ...

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... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 — ...

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... ABDOVF RCIDL Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. DS41419D-page 34 Bit 5 Bit 4 Bit 3 Bit 2 ...

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... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 — ...

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... Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. DS41419D-page 36 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 37

... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 ...

Page 38

... MDCHODIS MDCHPOL MDCHSYNC x unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. DS41419D-page 38 Bit 5 Bit 4 Bit 3 Bit 2 — ...

Page 39

... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 ...

Page 40

... Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. 1: These registers can be addressed from any bank. Note 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. DS41419D-page 40 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 41

... Legend: Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1828 only. 3: PIC16(L)F1824 only. 4: Unimplemented, read as 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 ...

Page 42

... PIC16(L)F1824/1828 3.3 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. ...

Page 43

... FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

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... PIC16(L)F1824/1828 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL DS41419D-page 44 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the ...

Page 45

... These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 0x0F Return Address 0x0E Return Address 0x0D Return Address ...

Page 46

... PIC16(L)F1824/1828 FIGURE 3-8: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41419D-page 46 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved ...

Page 47

... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0000 0x00 0x7F Bank 0 Bank 1 Bank 2 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Indirect Addressing 7 FSRxH Bank Select 0001 0010 1111 Bank FSRxL ...

Page 48

... PIC16(L)F1824/1828 3.5.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger ...

Page 49

... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a 1. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 by device DS41419D-page 49 ...

Page 50

... PIC16(L)F1824/1828 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 FCMEN bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor is enabled 0 Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit ...

Page 51

... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. 3: 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 DS41419D-page 51 ...

Page 52

... PIC16(L)F1824/1828 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 (1) LVP bit 13 U-1 U-1 U-1 bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set Legend: bit 13 LVP: Low-Voltage Programming Enable bit 1 Low-voltage programming enabled 0 High-voltage on MCLR must be used for programming ...

Page 53

... See Section 11.5 User ID, Device ID and Configuration Word Access for more information on accessing these memory locations. For more information on checksum calculation, see the PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification (DS41390). 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Write such as DS41419D-page 53 ...

Page 54

... PIC16(L)F1824/1828 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 User ID, Device ID and Configuration Word Access for more information on accessing these memory locations ...

Page 55

... XT, HS modes) and switch automatically to the internal oscillator. Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low-Power mode (0 MHz to 0 ...

Page 56

... PIC16(L)F1824/1828 FIGURE 5-1: SIMPLIFIED PIC External Oscillator OSC2 Sleep OSC1 Timer1 Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI Internal Oscillator Block HFPLL 16 MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) DS41419D-page 56 ® MCU CLOCK SOURCE BLOCK DIAGRAM LP, XT, HS, RC PLL FOSC< ...

Page 57

... High power, 4-32 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low power, 0-0.5 MHz (FOSC 101) 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

Page 58

... PIC16(L)F1824/1828 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the Oscillator mode F selected (typically between 2 M M. ...

Page 59

... MCU T1OSI C1 32.768 kHz Quartz Crystal T1OSO C2 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Note 1: Quartz according manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. Section 30.0 2: Always verify oscillator performance over the V expected for the application. ...

Page 60

... PIC16(L)F1824/1828 5.2.1.6 External RC Mode The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1 ...

Page 61

... OSCCON register to 1x The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 5.2.2.3 The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by (Register 5-3) ...

Page 62

... PIC16(L)F1824/1828 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The outputs of the 16 MHz HFINTOSC postscaler and the LFINTOSC connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF< ...

Page 63

... If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 30.0 Specifications. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Electrical DS41419D-page 63 ...

Page 64

... PIC16(L)F1824/1828 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC 0 IRCF <3:0> System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time ...

Page 65

... Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the Timer1 Oscillator. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 5.3.3 TIMER1 OSCILLATOR The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral optimized for timekeeping operations with a 32 ...

Page 66

... PIC16(L)F1824/1828 5.4 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device ...

Page 67

... OSC2 Program Counter System Clock 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator ...

Page 68

... PIC16(L)F1824/1828 5.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1 ...

Page 69

... Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Oscillator Failure Test Test Failure Detected Test ...

Page 70

... PIC16(L)F1824/1828 5.6 Oscillator Control Registers REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 SPLLEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Word SPLLEN bit is ignored. 4xPLL is always enabled (subject to oscillator requirements) ...

Page 71

... LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 LFINTOSC is ready 0 LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 HFINTOSC is at least 0.5% accurate 0 HFINTOSC is not 0.5% accurate 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 72

... PIC16(L)F1824/1828 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 TUN<4:0>: Frequency Tuning bits 011111 Maximum frequency 011110 • ...

Page 73

... The users firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 6.3 Conflicts with the CLKR pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...

Page 74

... PIC16(L)F1824/1828 REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 Reference Clock module is enabled 0 Reference Clock module is disabled ...

Page 75

... Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented locations, read as 0. Shaded cells are not used by reference clock sources. Legend: 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC<1:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE< ...

Page 76

... PIC16(L)F1824/1828 NOTES: DS41419D-page 76 2010-2012 Microchip Technology Inc. ...

Page 77

... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 PWRT Zero 64 ms LFINTOSC PWRTEN Device Reset DS41419D-page 77 ...

Page 78

... PIC16(L)F1824/1828 7.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

Page 79

... BROWN-OUT SITUATIONS V DD Internal Reset V DD Internal Reset V DD Internal Reset Note 1: T delay only if PWRTE bit is programmed to 0. PWRT 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 T BORRDY BOR Protection Active (1) T PWRT < T PWRT PWRT (1) T (1) T PWRT V BOR V ...

Page 80

... PIC16(L)F1824/1828 REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 SBOREN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 1 01: SBOREN is read/write, but has no effect on the BOR. If BOREN < ...

Page 81

... Word 2. See Section 3.4.2 Overflow/Underflow Reset for more information. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 7.7 Programming Mode Exit Upon exit of Programming mode, the device will behave POR had just occurred. 7.8 Power-up Timer The Power-up Timer optionally delays device execution after a BOR or POR event ...

Page 82

... PIC16(L)F1824/1828 FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC DS41419D-page 82 T PWRT T MCLR T OST 2010-2012 Microchip Technology Inc. ...

Page 83

... Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution Status bit is not implemented, that bit will be read as 0. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 POR BOR TO ...

Page 84

... PIC16(L)F1824/1828 7.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR) ...

Page 85

... Legend: unimplemented bit, reads as 0. Shaded cells are not used by Resets. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 86

... PIC16(L)F1824/1828 NOTES: DS41419D-page 86 2010-2012 Microchip Technology Inc. ...

Page 87

... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Interrupt to CPU DS41419D-page 87 ...

Page 88

... PIC16(L)F1824/1828 FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR6IF TMR6IE EEIF EEIE OSFIF OSFIE C1IF C1IE C2IF C2IE BCL1IF BCL1IE PIC16(L)F1828 only. Note 1: DS41419D-page 88 To Interrupt Logic (Figure 8-1)  ...

Page 89

... Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...

Page 90

... PIC16(L)F1824/1828 FIGURE 8-3: INTERRUPT LATENCY OSC1 CLKOUT Interrupt GIE PC Execute 1 Cycle Instruction at PC Interrupt GIE PC Execute 2 Cycle Instruction at PC Interrupt GIE PC-1 PC FSR ADDR ...

Page 91

... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT is not available in all oscillator modes. 4: For minimum width of INT pulse, refer to the AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 ...

Page 92

... PIC16(L)F1824/1828 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector ...

Page 93

... The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCxF register Note 1: have been cleared by software. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of ...

Page 94

... PIC16(L)F1824/1828 8.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 8-2. REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 95

... Unimplemented: Read as 0 bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 Enables the CCP2 Interrupt 0 Disables the CCP2 Interrupt Note 1: PIC16(L)F1828 only. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 EEIE BCL1IE — ...

Page 96

... PIC16(L)F1824/1828 8.5.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as shown in Register 8-4. REGISTER 8-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0/0 CCP4IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as ‘ ...

Page 97

... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register ...

Page 98

... PIC16(L)F1824/1828 8.5.6 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 8-6. REGISTER 8-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 (1) OSFIF C2IF C1IF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared ...

Page 99

... Interrupt is pending 0 Interrupt is not pending bit 0 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Note 1: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register ...

Page 100

... PIC16(L)F1824/1828 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 INTCON GIE PEIE OPTION_REG WPUEN INTEDG PIE1 TMR1GIE ADIE PIE2 OSFIE C2IE PIE3 TMR1GIF ADIF PIR1 OSFIF C2IF PIR2 PIR3 unimplemented locations, read as 0. Shaded cells are not used by interrupts. ...

Page 101

... Converter (DAC) Module and Section 14.0 Fixed Voltage Reference (FVR) for more information on these modules. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 102

... PIC16(L)F1824/1828 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. ...

Page 103

... Configurable time-out period is from 1ms to 256 seconds (typical) Multiple Reset conditions Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> WDT Time-out DS41419D-page 103 ...

Page 104

... PIC16(L)F1824/1828 10.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1. 10.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Word 1 are set to ‘ ...

Page 105

... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> 1x: This bit is ignored. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS3 WDTPS2 WDTPS1 U Unimplemented bit, read as 0 -m/n Value at POR and BOR/Value at all other Resets ...

Page 106

... PIC16(L)F1824/1828 NOTES: DS41419D-page 106 2010-2012 Microchip Technology Inc. ...

Page 107

... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

Page 108

... PIC16(L)F1824/1828 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information variables or other data that are updated often). When variables in one section change frequently, while vari- ables in another section do not change possible to ...

Page 109

... Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 EEADRH,EEADRL PC3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here INSTR ( ...

Page 110

... See Table 11-1 for details. TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Erase Block Device (Row) Size/ Write Latches/ Boundary PIC16(L)F1824 32 words, PIC16(L)F1828 EEADRL<4:0> EEADRL<4:0> 00000 DS41419D-page 110 11.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: programming 1 ...

Page 111

... Initiate read NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 (Figure 11-1) (Figure 11-1) DS41419D-page 111 ...

Page 112

... PIC16(L)F1824/1828 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. Load the EEADRH:EEADRL register pair with the address of the new row to be erased. 2. Clear the CFGS bit of the EECON1 register. 3. Set the EEPGD, FREE and WREN bits of the EECON1 register ...

Page 113

... EEADRL<4:0> 00000 EEADRL<4:0> 00001 Buffer Register 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 continue to run. The processor does not stall when LWLO 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...

Page 114

... PIC16(L)F1824/1828 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF INTCON,GIE BANKSEL EEADRL MOVF ADDRL,W MOVWF ...

Page 115

... MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...

Page 116

... PIC16(L)F1824/1828 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. Load the starting address of the row to be modified ...

Page 117

... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 DS41419D-page 117 ...

Page 118

... PIC16(L)F1824/1828 REGISTER 11-1: EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER ...

Page 119

... RD: Read Control bit 1 Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W/HC-0/0 R/W-x/q R/W-0/0 FREE ...

Page 120

... PIC16(L)F1824/1828 REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 bit 7 Legend Readable bit W Writable bit S Bit can only be set x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register ...

Page 121

... Data Register Data Bus Read PORTx To peripherals ANSELx 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 12.1 Alternate Pin Function The Alternate Pin Function Control 0 (APFCON0) and Alternate Pin Function Control 1 (APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and ...

Page 122

... TX/CK function is on RC4 1 TX/CK function is on RA0 (PIC16(L)F1828 TX/CK function is on RB7 1 TX/CK function is on RC4 bit 1-0 Unimplemented: Read as 0 Note 1: PIC16(L)F1824 only. DS41419D-page 122 U-0 R/W-0/0 R/W-0/0 (1) T1GSEL TXCKSEL — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets U-0 U-0 — ...

Page 123

... P2B function is on RC2 1 P2B function is on RA4 bit 0 CCP2SEL: Pin Selection 0 CCP2 function is on RC3 1 CCP2 function is on RA5 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 U-0 R/W-0/0 R/W-0/0 P1DSEL P1CSEL — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-0/0 ...

Page 124

... PORTA register and also the level at which an Interrupt-on-Change occurs, if that feature is enabled. See Section 30.4 DC Characteristics: PIC16(L)F1824/1828-I/E for more information on threshold levels. Changing the input threshold selection Note: should be performed while all peripheral modules are disabled ...

Page 125

... RA0 1. ICSPDAT 2. ICDDAT 3. DACOUT (DAC) RA1 1. ICSPCLK 2. ICDCLK 3. RX/DT (EUSART) RA2 1. SRQ 2. C1OUT (Comparator) 3. CCP3 RA3 No output priorities. Input only pin. RA4 1. CLKOUT 2. T1OSO 3. CLKR 4. SDO 5. P2B RA5 1. CCP2/P2A 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 DS41419D-page 125 ...

Page 126

... PIC16(L)F1824/1828 REGISTER 12-3: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x RA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 RA<5:0>: PORTA I/O Value bits 1 Port pin is > Port pin is < V ...

Page 127

... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-x/u U-0 R/W-x/u LATA4 ...

Page 128

... PIC16(L)F1824/1828 REGISTER 12-7: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 WPUA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 WPUA<5:0>: Weak Pull-up Register bits 1 Pull-up enabled 0 Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled ...

Page 129

... TRISA WPUA Legend unknown unchanged, unimplemented locations, read as 0. Shaded cells are not used by PORTA. Unshaded cells apply to PIC16(L)F1824 only. Note 1: TABLE 12-2: SUMMARY OF CONFIGURATION WORD WITH PORTA Name Bits Bit -/7 Bit -/6 13:8 ...

Page 130

... PORTB register and also the level at which an Interrupt-on-Change occurs, if that feature is enabled. See Section 30.4 DC Characteristics: for more information on PIC16(L)F1824/1828-I/E threshold levels. Changing the input threshold selection Note: should be performed while all peripheral modules are disabled. Changing the ...

Page 131

... Certain digital input functions override other port functions and are included in the priority list. RB4 SDA (MSSP) RB5 RX/DT (EUSART) RB6 SCL/SCK (MSSP) RB7 TX/CK (EUSART) 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 DS41419D-page 131 ...

Page 132

... PIC16(L)F1824/1828 REGISTER 12-9: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 RB<7:4>: PORTB General Purpose I/O Pin bits 1 Port pin is > Port pin is < bit 3-0 Unimplemented: Read as ‘ ...

Page 133

... INLVLB<7:4>: PORTB Input Level Select bits For RB<7:4> pins, respectively input used for PORT reads and interrupt-on-change 0 TTL input used for PORT reads and interrupt-on-change bit 3-0 Unimplemented: Read as 0 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-1/1 U-0 U-0 ANSB4 ...

Page 134

... PIC16(L)F1824/1828 TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 ANSELB ANSB7 ANSB6 INLVLB INLVLB7 INLVLB6 LATB LATB7 LATB6 PORTB RB7 RB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 Legend unknown unchanged unimplemented locations, read as 0. Shaded cells are not used by PORTB. ...

Page 135

... The input threshold is important in determining the value of a read of the PORTC register and also the level at which an Interrupt-on-Change occurs, if that feature is enabled. See Section 30.4 DC Character- istics: PIC16(L)F1824/1828-I/E for more information on threshold levels. Changing the input threshold selection Note: should be performed while all peripheral modules are disabled ...

Page 136

... RC0 1. SCL (MSSP) (PIC16(L)F1824 only) 2. SCK (MSSP) (PIC16(L)F1824 only) 3. P1D RC1 1. SDA (MSSP) (PIC16(L)F1824 only) 2. P1C 3. CCP4 (PIC16(L)F1828 only) RC2 1. SDO (MSSP) (PIC16(L)F1824 only) 2. P1D 3. P2B RC3 1. SS (MSSP) (PIC16(L)F1824 only) 2. CCP2 3. P1C 4. P2A RC4 1. ...

Page 137

... LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values. 2: LATC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as 0. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U Unimplemented bit, read as ‘ ...

Page 138

... PIC16(L)F1824/1828 REGISTER 12-18: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 U-0 (1) (1) ANSC7 ANSC6 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively 0 Digital I/O. Pin is assigned to port or digital special function. ...

Page 139

... TTL input used for PORT reads and Interrupt-on-Change Note 1: INLVLC<7:6> available on PIC16(L)F1828 only. Otherwise, they are unimplemented and read as 0. 2: PIC16(L)F1828 only, Reset default value. 3: PIC16(L)F1824 only, Reset default value. TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 ...

Page 140

... PIC16(L)F1824/1828 NOTES: DS41419D-page 140 2010-2012 Microchip Technology Inc. ...

Page 141

... A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 13.3 Interrupt Flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port ...

Page 142

... PIC16(L)F1824/1828 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx RAx IOCAPx DS41419D-page 142 IOCIE IOCAFx From all other IOCAFx individual pin detectors Q2 Clock Cycle 2010-2012 Microchip Technology Inc. IOC Interrupt to CPU Core ...

Page 143

... An enabled change was detected on the associated pin. Set when IOCAPx 1 and a rising edge was detected on RAx, or when IOCANx 1 and a falling edge was detected on RAx change was detected, or the user cleared the detected change. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 R/W-0/0 R/W-0/0 IOCAP4 ...

Page 144

... PIC16(L)F1824/1828 REGISTER 13-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER (PIC16(L)F1828 ONLY) R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 Interrupt-on-Change enabled on the pin for a positive going edge ...

Page 145

... TRISB6 TRISB Legend: unimplemented location, read as 0. Shaded cells are not used by interrupt-on-change. PIC16(L)F1828 only. Note 1: 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 U-0 IOCBF4 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 146

... PIC16(L)F1824/1828 NOTES: DS41419D-page 146 2010-2012 Microchip Technology Inc. ...

Page 147

... VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x 4x, to produce the three possible voltage levels ...

Page 148

... PIC16(L)F1824/1828 REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 0 Fixed Voltage Reference is disabled ...

Page 149

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 FIGURE 15-1: 15.2 Minimum Operating V Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications ...

Page 150

... PIC16(L)F1824/1828 NOTES: DS41419D-page 150 2010-2012 Microchip Technology Inc. ...

Page 151

... FVR Buffer1 CHS<4:0> Note 1: When ADON 0, all multiplexer inputs are disconnected. PIC16(L)F1828 only. 2: 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADNREF 1 ...

Page 152

... CHANNEL SELECTION There are channel selections available: AN<7:0> pins (PIC16(L)F1824 only) AN<11:0> pins (PIC16(L)F1828 only) DAC Output FVR (Fixed Voltage Reference) Output Refer to Section 17.0 Digital-to-Analog Converter (DAC) Module” ...

Page 153

... Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) ...

Page 154

... PIC16(L)F1824/1828 16.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...

Page 155

... Timer1 counter resets to zero. TABLE 16-2: SPECIAL EVENT TRIGGER Device CCPx/ECCPx PIC16(L)F1824/1828 CCP4 Using the Special Event Trigger does not assure proper ADC timing the users responsibility to ensure that the ADC timing requirements are met. Refer to Section 24.0 “ ...

Page 156

... PIC16(L)F1824/1828 16.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: Disable pin output driver (Refer to the TRIS register) Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: Select ADC conversion clock • ...

Page 157

... Note 1: See Section 17.0 Digital-to-Analog Converter (DAC) See 2: Section 14.0 Fixed Voltage Reference (FVR) 3: PIC16(L)F1828 only. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (2) Modulefor more information. ...

Page 158

... PIC16(L)F1824/1828 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 Right justified. Six Most Significant bits of ADRESH are set to 0 when the conversion result is loaded Left justified. Six Least Significant bits of ADRESL are set to ‘ ...

Page 159

... Bit is set 0 Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-x/u ...

Page 160

... PIC16(L)F1824/1828 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 1 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits ...

Page 161

... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 162

... PIC16(L)F1824/1828 FIGURE 16-4: ANALOG INPUT MODEL Analog Input pin Rs C PIN Legend Sample/Hold Capacitance HOLD C Input Capacitance PIN I Leakage current at the pin due to LEAKAGE various junctions R Interconnect Resistance Resistance of Sampling Switch Sampling Switch V Threshold Voltage T Note 1: Refer to Section 30.0 Electrical Specifications ...

Page 163

... Shaded cells are not used for ADC Legend: module. Note 1: PIC16(L)F1828 only. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS<2:0> ...

Page 164

... PIC16(L)F1824/1828 NOTES: DS41419D-page 164 2010-2012 Microchip Technology Inc. ...

Page 165

... Section 30.0 Specifications. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 17.3 DAC Voltage Reference Output The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to 1. Selecting the DAC reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin ...

Page 166

... PIC16(L)F1824/1828 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACLPS 1 DACNSS V - REF V SS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41419D-page 166 Digital-to-Analog Converter (DAC SRC ...

Page 167

... DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 This is also the method used to output the voltage level from the FVR to an output pin. See information. ...

Page 168

... PIC16(L)F1824/1828 REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 DACEN DACLPS DACOE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit ...

Page 169

... FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 unimplemented, read as 0. Shaded cells are unused by the DAC module. Legend: 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> DACOE DACPSS<1:0> DACR<4:0> ...

Page 170

... PIC16(L)F1824/1828 NOTES: DS41419D-page 170 2010-2012 Microchip Technology Inc. ...

Page 171

... The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to Set or Reset the SR latch, respectively. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time ...

Page 172

... PIC16(L)F1824/1828 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse (2) Gen SRI SRSPE SRCLK SRSCKE (3) SYNCC2OUT SRSC2E (3) SYNCC1OUT SRSC1E SRPR Pulse (2) Gen SRI SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. ...

Page 173

... No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 Pulse reset input for 1 Q-clock period effect on reset input. Note 1: Set only, always reads back 0. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 MHz MHz OSC OSC 39.0 kHz 31 ...

Page 174

... PIC16(L)F1824/1828 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit latch is set when the SRI pin is high ...

Page 175

... TRISC TRISC7 TRISC6 Legend: unimplemented, read as 0. Shaded cells are unused by the SR latch module. Note 1: PIC16(L)F1828 only. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 INLVLA5 INLVLA4 INLVLA3 ...

Page 176

... PIC16(L)F1824/1828 NOTES: DS41419D-page 176 2010-2012 Microchip Technology Inc. ...

Page 177

... CxON PCH<1:0> Note 1: When CxON 0, all multiplexer inputs are disconnected and the Comparator will produce a 0 at the output. 2: Output of comparator can be frozen during debugging. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 FIGURE 19- Output ...

Page 178

... PIC16(L)F1824/1828 19.2 Comparator Control Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register Control and Status bits for the following: Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization ...

Page 179

... Timer1 Block Diagram (Figure 20-1) information. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. When either edge detector is triggered and its ...

Page 180

... PIC16(L)F1824/1828 19.7 Comparator Negative Input Selection The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. To use CxIN and CxINx- pins as analog Note: input, the appropriate bits must be set in the ANSEL register and the correspond- ing TRIS bits must also be set to disable the output drivers ...

Page 181

... Leakage Current at the pin due to various junctions LEAKAGE R Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 Electrical 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 V DD 0. (1) I LEAKAGE 0. Vss Specifications. To Comparator ...

Page 182

... PIC16(L)F1824/1828 REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 CxON CxOUT CxOE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CxON: Comparator Enable bit 1 Comparator is enabled and consumes no active power 0 Comparator is disabled ...

Page 183

... Bit is cleared bit 7-2 Unimplemented: Read as 0 bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets SS ...

Page 184

... PIC16(L)F1824/1828 TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 CM1CON0 C1ON C1OUT CM2CON0 C2ON C2OUT CM1CON1 C1NTP C1INTN CM2CON1 C2NTP C2INTN CMOUT DACCON0 DACEN DACLPS DACCON1 FVRCON FVREN FVRRDY INLVLA (1) (1) INLVLC ...

Page 185

... T0CKI 1 TMR0SE TMR0CS 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...

Page 186

... PIC16(L)F1824/1828 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256 ...

Page 187

... PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 001 010 011 100 101 110 111 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets /4) OSC ...

Page 188

... PIC16(L)F1824/1828 TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 CPSCON0 CPSON CPSRM FVRCON FVREN FVRRDY INLVLA INTCON GIE PEIE OPTION_REG WPUEN INTEDG TMR0CS TMR0SE TMR0 Timer0 Module Register TRISA Legend: Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module. ...

Page 189

... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...

Page 190

... PIC16(L)F1824/1828 21.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...

Page 191

... This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry ...

Page 192

... PIC16(L)F1824/1828 21.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 21.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry ...

Page 193

... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 21.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

Page 194

... PIC16(L)F1824/1828 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41419D-page 194 2010-2012 Microchip Technology Inc. ...

Page 195

... T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Cleared by software DS41419D-page 195 ...

Page 196

... PIC16(L)F1824/1828 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41419D-page 196 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL  ...

Page 197

... Synchronize asynchronous clock input with system clock (F bit 1 Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 and clears Timer1 gate flip-flop 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 198

... PIC16(L)F1824/1828 REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON 0: This bit is ignored If TMR1ON Timer1 counting is controlled by the Timer1 gate function ...

Page 199

... T1GPOL T1GCON unimplemented location, read as 0. Shaded cells are not used by the Timer1 module. Legend: Page provides register information. Note 1: PIC16(L)F1828 only. 2010-2012 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 ANSA4 ANSA2 DC1B<1:0> ...

Page 200

... PIC16(L)F1824/1828 NOTES: DS41419D-page 200 2010-2012 Microchip Technology Inc. ...

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