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PIC16LF1507 Datasheet - Page 72

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7.6.7
PIR3 REGISTER
The PIR3 register contains the interrupt flag bits, as
shown in
Register
7-7.
REGISTER 7-7:
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0
U-0
U-0
bit 7
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
CLC2IF: Configurable Logic Block 2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
CLC1IF: Configurable Logic Block 1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
 2011 Microchip Technology Inc.
PIC16(L)F1507
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
software
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
U-0
U-0
U-0
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
Preliminary
should
ensure
the
R/W-0/0
R/W-0/0
CLC2IF
CLC1IF
bit 0
DS41586A-page 72

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