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PIC16LF1507 Datasheet - Page 209

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PIC16(L)F1507
TABLE 24-3:
PIC16(L)F1507 ENHANCED INSTRUCTION SET
Mnemonic,
Description
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f, d
Add W and f
ADDWFC
f, d
Add with Carry W and f
ANDWF
f, d
AND W with f
ASRF
f, d
Arithmetic Right Shift
LSLF
f, d
Logical Left Shift
LSRF
f, d
Logical Right Shift
CLRF
f
Clear f
CLRW
Clear W
COMF
f, d
Complement f
DECF
f, d
Decrement f
INCF
f, d
Increment f
IORWF
f, d
Inclusive OR W with f
MOVF
f, d
Move f
MOVWF
f
Move W to f
Rotate Left f through Carry
RLF
f, d
RRF
f, d
Rotate Right f through Carry
SUBWF
f, d
Subtract W from f
SUBWFB
f, d
Subtract with Borrow W from f
SWAPF
f, d
Swap nibbles in f
XORWF
f, d
Exclusive OR W with f
f, d
Decrement f, Skip if 0
DECFSZ
f, d
Increment f, Skip if 0
INCFSZ
BIT-ORIENTED FILE REGISTER OPERATIONS
f, b
Bit Clear f
BCF
f, b
Bit Set f
BSF
BTFSC
f, b
Bit Test f, Skip if Clear
BTFSS
f, b
Bit Test f, Skip if Set
LITERAL OPERATIONS
ADDLW
k
Add literal and W
ANDLW
k
AND literal with W
IORLW
k
Inclusive OR literal with W
MOVLB
k
Move literal to BSR
MOVLP
k
Move literal to PCLATH
MOVLW
k
Move literal to W
SUBLW
k
Subtract W from literal
XORLW
k
Exclusive OR literal with W
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP .
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
DS41586A-page 209
14-Bit Opcode
Cycles
MSb
1
00
1
11
1
00
1
11
1
11
1
11
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
00
1
11
1
00
1
00
BYTE ORIENTED SKIP OPERATIONS
1(2)
00
1(2)
00
1
01
1
01
BIT-ORIENTED SKIP OPERATIONS
1 (2)
01
1 (2)
01
1
11
1
11
1
11
1
00
1
11
1
11
1
11
1
11
Preliminary
Status
Notes
Affected
LSb
C, DC, Z
2
0111
dfff
ffff
C, DC, Z
2
1101
dfff
ffff
Z
2
0101
dfff
ffff
C, Z
2
0111
dfff
ffff
C, Z
2
0101
dfff
ffff
C, Z
2
0110
dfff
ffff
Z
2
0001
lfff
ffff
Z
0001
0000
00xx
Z
2
1001
dfff
ffff
Z
2
0011
dfff
ffff
Z
2
1010
dfff
ffff
Z
2
0100
dfff
ffff
Z
2
1000
dfff
ffff
2
0000
1fff
ffff
C
2
1101
dfff
ffff
C
2
1100
dfff
ffff
C, DC, Z
2
0010
dfff
ffff
C, DC, Z
2
1011
dfff
ffff
2
1110
dfff
ffff
Z
2
0110
dfff
ffff
1, 2
1011
dfff
ffff
1, 2
1111
dfff
ffff
2
00bb
bfff
ffff
2
01bb
bfff
ffff
1, 2
10bb
bfff
ffff
1, 2
11bb
bfff
ffff
C, DC, Z
1110
kkkk
kkkk
Z
1001
kkkk
kkkk
Z
1000
kkkk
kkkk
0000
001k
kkkk
0001
1kkk
kkkk
0000
kkkk
kkkk
C, DC, Z
1100
kkkk
kkkk
Z
1010
kkkk
kkkk
 2011 Microchip Technology Inc.

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