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PIC16LF1507 Datasheet - Page 162

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20.1
CLCx Setup
Programming the CLCx module is performed by config-
uring the 4 stages in the logic signal flow. The 4 stages
are:
• Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
TABLE 20-1:
CLCx DATA INPUT SELECTION
lcxd1
lcxd2
Data Input
D1S
D2S
CLCxIN[0]
000
CLCxIN[1]
001
CLCxIN[2]
010
CLCxIN[3]
011
CLCxIN[4]
100
000
CLCxIN[5]
101
001
CLCxIN[6]
110
010
CLCxIN[7]
111
011
CLCxIN[8]
100
CLCxIN[9]
101
CLCxIN[10]
110
CLCxIN[11]
111
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
 2011 Microchip Technology Inc.
PIC16(L)F1507
20.1.1
DATA SELECTION
There are 16 signals available as inputs to the configu-
rable logic. Four 8-input multiplexers are used to select
the inputs to pass on to the next stage. The 16 inputs to
the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in
each case, paired with a different group. This arrange-
ment makes possible selection of up to two from a
group without precluding a selection from another
group.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers
(Register 20-3
respectively).
Data inputs are selected with CLCxSEL0 and
CLCxSEL1 registers
(Register 20-3
respectively).
Data selection is through four multiplexers as indicated
on the left side of
Figure
are identified by a generic numbered input name.
Table 20-1
correlates the generic input name to the
actual signal for each CLC module. The columns labeled
lcxd1 through lcxd4 indicate the MUX output for the
selected data input. D1S through D4S are abbreviations
for the MUX select input codes: LCxD1S<2:0> through
LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
Note:
Data selections are undefined at power-up.
lcxd3
lcxd4
CLC 1
D3S
D4S
CLC1IN0
100
CLC1IN1
101
Reserved
110
Reserved
111
F
OSC
TMR0IF
TMR1IF
TMR2 = PR2
lcx1_out
000
lcx2_out
001
lcx3_out
010
lcx4_out
011
NCO1OUT
100
000
HFINTOSC
101
001
PWM3OUT
110
010
PWM4OUT
111
011
Preliminary
and
Register
20-4,
and
Register
20-4,
20-2. Data inputs in the figure
CLC 2
CLC2IN0
CLC2IN1
Reserved
Reserved
F
OSC
TMR0IF
TMR1IF
TMR2 = PR2
lcx1_out
lcx2_out
lcx3_out
lcx4_out
LFINTOSC
ADCFRC
PWM1OUT
PWM2OUT
DS41586A-page 162

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