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PIC16LF1507 Datasheet

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PIC16(L)F1507
Data Sheet
20-Pin Flash, 8-Bit Microcontrollers
Preliminary
 2011 Microchip Technology Inc.
DS41586A

Summary of Contents

Page 1

... Flash, 8-Bit Microcontrollers 2011 Microchip Technology Inc. PIC16(L)F1507 Data Sheet Preliminary DS41586A ...

Page 2

... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...

Page 3

... MHz to 31 kHz 31 kHz Low-Power Internal Oscillator Three External Clock modes MHz Special Microcontroller Features: Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1507) - 2.3V to 5.5V (PIC16F1507) Self-Programmable under Software Control Power-on Reset (POR) Power-up Timer (PWRT) Programmable Low-Power Brown-Out Reset (LPBOR) • ...

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... PIC16(L)F1507 Family Types Program Device Memory Flash (words) PIC16F1507 2048 PIC16LF1507 Note 1: One pin is input-only. FIGURE 1: 20-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1507 PDIP, SOIC, SSOP MCLR/V Note: See Table 1 for location of all peripheral functions. 2011 Microchip Technology Inc. ...

Page 5

... QFN PACKAGE DIAGRAM FOR PIC16(L)F1507 QFN 4x4 MCLR/V /RA3 PP RC5 RC4 RC3 RC6 Note: See Table 1 for location of all peripheral functions. DS41586A-page RA1/ICSPCLK 15 1 RA2 14 2 PIC16F1507 13 RC0 3 PIC16LF1507 12 RC1 4 RC2 Preliminary 2011 Microchip Technology Inc. ...

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... SS Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register. Alternate location for peripheral pin function selected by the APFCON register. 2: 2011 Microchip Technology Inc. ...

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... Packaging Information ... 245 Appendix A: Data Sheet Revision History ... 255 Index ... 257 The Microchip Web Site ... 263 Customer Change Notification Service ... 263 Customer Support ... 263 Reader Response ... 264 Product Identification System ... 265 Worldwide Sales and Service ... 266 DS41586A-page 7 Preliminary 2011 Microchip Technology Inc. ...

Page 8

... NOTES: 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 8 ...

Page 9

... Analog-to-Digital Converter (ADC) Complementary Wave Generator (CWG) Fixed Voltage Reference (FVR) Numerically Controlled Oscillator (NCO) Temperature Indicator Configurable Logic Cell (CLC) CLC1 CLC2 PWM Modules PWM1 PWM2 PWM3 PWM4 Timers Timer0 Timer1 Timer2 DS41586A-page 9 shows Preliminary 2011 Microchip Technology Inc. ...

Page 10

... MCLR CLC1 CLC2 Temp. ADC Indicator 10-Bit Note 1: See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. 2: 2011 Microchip Technology Inc. Program Flash Memory CPU (Figure 2-1) Timer0 Timer1 Timer2 CWG1 FVR PWM1 PWM2 PWM3 Preliminary ...

Page 11

... CMOS Pulse Width Module source output. CMOS Numerically Controlled Oscillator is source output. TTL CMOS General purpose I/O. AN A/D Channel input. Schmitt Trigger input with CMOS levels I Preliminary Description OD Open Drain 2 2 C Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...

Page 12

... High Voltage XTAL Crystal Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register. 2: Alternate location for peripheral pin function selected by the APFCON register. 2011 Microchip Technology Inc. PIC16(L)F1507 Input Output Type Type TTL CMOS General purpose I/O ...

Page 13

... FSRs. See Section 3.5 Indirect Addressing for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 24.0 Instruction Set Summary for more details. DS41586A-page 13 Preliminary 2011 Microchip Technology Inc. ...

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... Timing CLKOUT Generation Generation Generation Internal Internal Internal Oscillator Oscillator Oscillator Block Block Block 2011 Microchip Technology Inc. PIC16(L)F1507 15 Data Bus Data Bus Data Bus Program Counter Program Counter Program Counter 16-Level Stack 8 Level Stack 8 Level Stack RAM (15-bit) ...

Page 15

... Core Registers - Special Function Registers - General Purpose RAM - Common RAM TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16F1507 PIC16LF1507 DS41586A-page 15 The following features are associated with access and control of program memory and data memory: PCL and PCLATH Stack Indirect Addressing 3.1 ...

Page 16

... Page 0 Memory Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 2011 Microchip Technology Inc. PIC16(L)F1507 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in pro- gram memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory ...

Page 17

... Preliminary Table 3-2. For for detailed 3-4. BANKx INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2011 Microchip Technology Inc. ...

Page 18

... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2011 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...

Page 19

... Special Function Registers (20 bytes maximum) 1Fh 20h General Purpose RAM (80 bytes maximum) 6Fh 70h 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1507 are as shown in Table 3-3. Preliminary 2011 Microchip Technology Inc. Memory Region Core Registers (12 bytes) Common RAM (16 bytes) ...

Page 20

TABLE 3-3: PIC16(L)F1507 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh ...

Page 21

TABLE 3-3: PIC16(L)F1507 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch 40Dh 48Dh 50Dh 40Eh 48Eh ...

Page 22

TABLE 3-3: PIC16(L)F1507 MEMORY MAP (CONTINUED) BANK 24 BANK 25 C00h C80h D00h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) C0Bh C8Bh D0Bh C0Ch C8Ch D0Ch C0Dh C8Dh D0Dh C0Eh C8Eh ...

Page 23

... Unimplemented data memory locations, read as 0. DS41586A-page 23 Bank 31 F8Ch Unimplemented Read as 0 FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh FECh FEDh STKPTR FEEh TOSL FEFh TOSH Preliminary 2011 Microchip Technology Inc. ...

Page 24

... Write Buffer for the upper 7 bits of the Program Counter x8Ah x0Bh or INTCON GIE PEIE x8Bh x unknown unchanged value depends on condition unimplemented, read as 0’ reserved. Legend: Shaded locations are unimplemented, read as 0. 2011 Microchip Technology Inc. can be Bit 5 Bit 4 Bit 3 Bit 2 — — ...

Page 25

... POR BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 SCS<1:0> -011 1-00 -011 1-00 LFIOFR HFIOFS 1-q0 --00 q-qq --qq xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 --00 0000 --00 0000 ---- 0000 ---- 2011 Microchip Technology Inc. ...

Page 26

... Unimplemented 31Fh Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. PIC16F1507 only. Note 1: Unimplemented, read as 1. 2: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 LATA5 LATA4 LATA2 LATB5 LATB4 ...

Page 27

... N1PFM 0000 ---0 0000 ---0 N1CKS<1:0> 0000 --00 0000 --00 2011 Microchip Technology Inc. ...

Page 28

... Unimplemented 69Fh Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as 0. Note 1: PIC16F1507 only. Unimplemented, read as 1. 2: 2011 Microchip Technology Inc. PIC16(L)F1507 Bit 5 Bit 4 Bit 3 Bit 2 PWM1DCH<7:0> ...

Page 29

... LC2D1S<2:0> -xxx -xxx -uuu -uuu LC2D3S<2:0> -xxx -xxx -uuu -uuu LC2G1D1N xxxx xxxx uuuu uuuu LC2G2D1N xxxx xxxx uuuu uuuu LC2G3D1N xxxx xxxx uuuu uuuu LC2G4D1N xxxx xxxx uuuu uuuu 2011 Microchip Technology Inc. ...

Page 30

... Top-of-Stack High byte TOSH x unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as 0. Note 1: PIC16F1507 only. 2: Unimplemented, read as 1. 2011 Microchip Technology Inc. PIC16(L)F1507 Bit 5 Bit 4 Bit 3 Bit 2 Z_SHAD — ...

Page 31

... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. BRA Preliminary 2011 Microchip Technology Inc. ...

Page 32

... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2011 Microchip Technology Inc. PIC16(L)F1507 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...

Page 33

... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2011 Microchip Technology Inc. ...

Page 34

... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2011 Microchip Technology Inc. PIC16(L)F1507 0x0F Return Address 0x0E Return Address ...

Page 35

... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41586A-page 35 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0x7FFF 0xFFFF Preliminary 2011 Microchip Technology Inc. ...

Page 36

... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2011 Microchip Technology Inc. PIC16(L)F1507 Indirect Addressing 7 FSRxH Bank Select 11111 Bank 31 Preliminary ...

Page 37

... FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP 7 0 FSRnL 0 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2011 Microchip Technology Inc. ...

Page 38

... NOTES: 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 38 ...

Page 39

... Device Configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. DS41586A-page 39 Preliminary 2011 Microchip Technology Inc. ...

Page 40

... ECM: External Clock, Medium-Power mode: on CLKIN pin 01 ECL: External Clock, Low-Power mode: on CLKIN pin 00 INTOSC oscillator: I/O function on CLKIN pin Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: 2: Once enabled, code-protect can only be disabled by bulk erasing the device. 2011 Microchip Technology Inc. U-1 R/P-1 CLKOUTEN R/P-1 R/P-1 WDTE< ...

Page 41

... LPBOR: Low-Power BOR Enable bit 1 Low-Power Brown-out Reset is disabled 0 Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-Out Reset Voltage Selection bit 1 Brown-out Reset voltage set to: 1.9V (PIC16LF1507) 2.4V (PIC16F1507), typical 0 Brown-out Reset voltage set to 2.7V (typical) bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 Stack Overflow or Underflow will cause a Reset ...

Page 42

... See Section 10.4 User ID, Device ID and Configuration Word Access for more information on accessing these memory locations. For more information on checksum calculation, see the PIC12(L)F1501/PIC16(L)F150X Memory Programming Specification (DS41573). 2011 Microchip Technology Inc. PIC16(L)F1507 Write such as Preliminary ...

Page 43

... Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 13-5 DEV<8:0>: Device ID bits Device PIC16F1507 10 1101 000 PIC16LF1507 10 1101 110 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). DS41586A-page DEV<8:3> ...

Page 44

... NOTES: 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 44 ...

Page 45

... MCU CLOCK SOURCE BLOCK DIAGRAM IRCF<3:0> Internal Oscillator 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz FOSC<1:0> 62.5 kHz 31.25 kHz 31 kHz WDT, PWRT and other modules Preliminary EC Sleep CPU and Peripherals Clock Control SCS<1:0> 2011 Microchip Technology Inc. ...

Page 46

... An external clock source determined by the value of the FOSC bits. See Section 5.3 Clock Switchingfor more informa- tion. 2011 Microchip Technology Inc. PIC16(L)F1507 5.2.1.1 EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source ...

Page 47

... OSCCON register to 1x Internal Peripherals that use the LFINTOSC are: Power-up Timer (PWRT) Internal Watchdog Timer (WDT) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. Preliminary 2011 Microchip Technology Inc. ...

Page 48

... Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 2011 Microchip Technology Inc. PIC16(L)F1507 5.2.2.4 Internal Oscillator Clock Switch Timing ...

Page 49

... System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock DS41586A-page 49 Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT is enabled 2-cycle Sync 0 Preliminary Running Running Running 2011 Microchip Technology Inc. ...

Page 50

... EC LFINTOSC EC Any clock source HFINTOSC Any clock source LFINTOSC 2011 Microchip Technology Inc. PIC16(L)F1507 5.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. ...

Page 51

... SCS<1:0>: System Clock Select bits 1x Internal oscillator block 01 Reserved 00 Clock determined by FOSC<1:0> in Configuration Words. Duplicate frequency derived from HFINTOSC. Note 1: DS41586A-page 51 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> bit 0 2011 Microchip Technology Inc. ...

Page 52

... Bit -/6 13:8 CONFIG1 7:0 MCLRE CP Legend: unimplemented location, read as 0. Shaded cells are not used by clock sources. 2011 Microchip Technology Inc. R-0/q U-0 HFIOFR — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Conditional Bit 5 Bit 4 ...

Page 53

... ICSP Programming Mode Exit RESET Instruction Stack Pointer MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR (1) Active See Table 6-1 for BOR active conditions. Note 1: DS41586A-page 53 PWRT R Done PWRTE LFINTOSC Preliminary 2011 Microchip Technology Inc. Device Reset ...

Page 54

... BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and V is higher than the BOR threshold. DD 2011 Microchip Technology Inc. 6.2 Brown-Out Reset (BOR) has The BOR circuit holds the device in Reset when V DD reaches a selectable minimum level ...

Page 55

... BOREN<1:0> bits are located in Configuration Words. Note 1: DS41586A-page 55 PWRT (1) T < T PWRT (1) T PWRT PWRT (1) T U-0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition (1) Preliminary 2011 Microchip Technology Inc. V BOR V BOR V BOR U-0 R-q/u BORRDY bit 0 ...

Page 56

... When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.2 PORTA Regis- ters for more information. 2011 Microchip Technology Inc. 6.5 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period ...

Page 57

... PIC16(L)F1507 FIGURE 6-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC DS41586A-page 57 T PWRT T MCLR Preliminary 2011 Microchip Technology Inc. ...

Page 58

... Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution Status bit is not implemented, that bit will be read as 0. 2011 Microchip Technology Inc. PIC16(L)F1507 RI ...

Page 59

... A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS41586A-page 59 6-2. R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT RMCLR Bit is set by hardware U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition Preliminary R/W/HC-q/u R/W/HC-q/u POR BOR bit 0 2011 Microchip Technology Inc. ...

Page 60

... CONFIG1 7:0 CP MCLRE 13:8 CONFIG2 7:0 unimplemented location, read as 0. Shaded cells are not used by Flash program memory. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RWDT RMCLR RI TO ...

Page 61

... A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> DS41586A-page 61 TMR0IF TMR0IE INTF INTE IOCIF IOCIE PEIE GIE Preliminary 2011 Microchip Technology Inc. Wake-up (If in Sleep mode) Interrupt to CPU ...

Page 62

... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2011 Microchip Technology Inc. PIC16(L)F1507 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...

Page 63

... Inst(PC) NOP NOP PC1/FSR New PC/ 0004h ADDR PC1 Inst(PC) NOP NOP FSR ADDR PC1 PC2 INST(PC) NOP NOP FSR ADDR PC1 PC2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h Inst(0004h) Inst(0005h) NOP 0004h 0005h Inst(0004h) NOP NOP 2011 Microchip Technology Inc. ...

Page 64

... Asynchronous interrupt latency 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: For minimum width of INT pulse, refer to AC specifications in Section 25.0 Electrical Specifications” INTF is enabled to be set any time during the Q4-Q1 cycles. 2011 Microchip Technology Inc ...

Page 65

... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the users appli- cation, other registers may also need to be saved. DS41586A-page 65 Preliminary 2011 Microchip Technology Inc. ...

Page 66

... None of the interrupt-on-change pins have changed state The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register Note 1: have been cleared by software. 2011 Microchip Technology Inc. PIC16(L)F1507 Interrupt flag bits are set when an interrupt Note: ...

Page 67

... Disables the Timer1 overflow interrupt DS41586A-page 67 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. U-0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 ...

Page 68

... Unimplemented: Read as 0 bit 2 NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit 1 Enables the NCO interrupt 0 Disables the NCO interrupt bit 1-0 Unimplemented: Read as 0 2011 Microchip Technology Inc. PIC16(L)F1507 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. U-0 U-0 R/W-0/0 — ...

Page 69

... Disables the CLC 1 interrupt DS41586A-page 69 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. U-0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 CLC2IE CLC1IE bit 0 ...

Page 70

... Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1507 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register ...

Page 71

... Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. U-0 U-0 R/W-0/0 NCO1IF U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. U-0 U-0 bit 0 ...

Page 72

... Interrupt is not pending bit 0 CLC1IF: Configurable Logic Block 1 Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1507 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...

Page 73

... NCO1IF Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 66 PS<2:0> 137 TMR2IE TMR1IE 67 68 CLC2IE CLC1IE 69 TMR2IF TMR1IF 70 71 CLC2IF CLC1IF 72 2011 Microchip Technology Inc. ...

Page 74

... NOTES: 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 74 ...

Page 75

... If the interrupt occurs during or after the execu- tion of a SLEEP instruction - SLEEP instruction will be completely exe- cuted - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Preliminary 2011 Microchip Technology Inc. ...

Page 76

... T1 ; See Section 25.0 Electrical Specifications . OSC GIE 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE 0, execution will continue in-line. 4: 2011 Microchip Technology Inc. PIC16(L)F1507 (3) T1 OSC ...

Page 77

... Sleep. This will have a direct effect on the Sleep mode current. Please refer to sections 20.5 Operation During Sleep, 21.7 Operation In Sleep and 22.10 Oper- ation During Sleep for more information. The PIC16LF1507 does not have a con- Note: figurable Low-Power PIC16LF1507 is an unregulated device ...

Page 78

... STATUS WDTCON Legend: unimplemented, read as 0. Shaded cells are not used in Power-down mode. 2011 Microchip Technology Inc. U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Bit 5 Bit 4 ...

Page 79

... Configurable time-out period is from 256 seconds (typical) Multiple Reset conditions Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep DS41586A-page 79 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary 2011 Microchip Technology Inc. WDT Time-out ...

Page 80

... WDTE<1:0> and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep System Clock INTOSC, EXTCLK Change INTOSC divider (IRCF bits) 2011 Microchip Technology Inc. PIC16(L)F1507 9.3 Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 256 seconds (nominal). ...

Page 81

... WDTPS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ( (Interval 4s nominal (Interval 8s nominal (Interval 16s nominal (Interval 32s nominal (Interval 64s nominal (Interval 128s nominal (Interval 256s nominal) Preliminary R/W-1/1 R/W-0/0 SWDTEN bit 0 2011 Microchip Technology Inc. ...

Page 82

... SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Name Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented location, read as 0. Shaded cells are not used by Watchdog Timer. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 IRCF<3:0> RWDT RMCLR RI — WDTPS< ...

Page 83

... See Table 10-1 write latches for Flash program memory. TABLE 10-1: Device PIC16F1507 PIC16LF1507 Preliminary for Erase Row size and the number of FLASH MEMORY ORGANIZATION BY DEVICE Write Row Erase Latches (words) ...

Page 84

... Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on instruction after the RD bit is set. 2011 Microchip Technology Inc. PIC16(L)F1507 FIGURE 10-1: to the Program or Configuration Memory the next Instruction Fetched ignored ...

Page 85

... Store in user location DS41586A-page 85 PMADRH,PMADRL PC3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP Forced NOP executed here executed here (Figure 10-2) (Figure 10-2) Preliminary INSTR ( INSTR( INSTR( executed here executed here 2011 Microchip Technology Inc. ...

Page 86

... Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. 2011 Microchip Technology Inc. PIC16(L)F1507 FIGURE 10-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART ...

Page 87

... Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE 1) Enable Write/Erase Operation (WREN 1) Unlock Sequence Figure 10-3 (FIGURE x-x) CPU stalls while Erase operation completes (2ms typical) Disable Write/Erase Operation (WREN 0) Re-enable Interrupts (GIE 1) End Erase Operation Preliminary 2011 Microchip Technology Inc. ...

Page 88

... PMCON1,WR NOP NOP BCF PMCON1,WREN BSF INTCON,GIE 2011 Microchip Technology Inc. PIC16(L)F1507 ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ...

Page 89

... Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. Preliminary 2011 Microchip Technology Inc. ...

Page 90

FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES PMADRH - r10 Row PMADRH<6:0> Address :PMADRL<7:4> Decode ...

Page 91

... Last word to write ? No Unlock Sequence (Figure x-x) Figure 10-3 No delay when writing to Program Memory Latches Increment Address (PMADRH:PMADRL) Preliminary 2011 Microchip Technology Inc. Write Latches to Flash (LWLO 0) Unlock Sequence (Figure x-x) Figure 10-3 CPU stalls while Write operation completes (2ms typical) Disable Write/Erase Operation ...

Page 92

... PMCON2 MOVLW 0AAh MOVWF PMCON2 BSF PMCON1,WR NOP NOP BCF PMCON1,WREN BSF INTCON,GIE 2011 Microchip Technology Inc. PIC16(L)F1507 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Not configuration space ; Enable writes ; Only Load Write Latches ...

Page 93

... Figure 10-2 An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (Figure x.x) Figure 10-4 Write Operation use RAM image (Figure x.x) Figure 10-5 Modify Operation Preliminary 2011 Microchip Technology Inc. End ...

Page 94

... INTCON,GIE ; Restore interrupts MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16(L)F1507 10-2, the Function Read Access User IDs Yes Yes Yes Figure 10-2) Figure 10-2) ...

Page 95

... RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 10-2 PMDAT No RAM image ? Fail Yes Verify Operation No Last Word ? Yes End Verify Operation DS41586A-page 95 Preliminary 2011 Microchip Technology Inc. ...

Page 96

... Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 Unimplemented: Read as 1 bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 97

... The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE DS41586A-page 97 R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE WRERR WREN U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets HC Bit is cleared by hardware (3) (2) Preliminary R/S/HC-0/0 R/S/HC-0 bit 0 2011 Microchip Technology Inc. ...

Page 98

... CONFIG2 7:0 Legend: unimplemented location, read as 0 . Shaded cells are not used by Flash program memory. 2011 Microchip Technology Inc. W-0/0 W-0/0 Program Memory Control Register Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Bit 5 ...

Page 99

... I/O port, without the interfaces to other peripherals, is shown in DS41586A-page 99 FIGURE 11-1: D Write LATx Write PORTx Data Register Data Bus Read PORTx To peripherals Figure 11-1. Preliminary GENERIC I/O PORT OPERATION Read LATx TRISx I/O pin V SS ANSELx 2011 Microchip Technology Inc. ...

Page 100

... CLC1SEL: Pin Selection bit 1 CLC1 function is on RC5 0 CLC1 function is on RA2 bit 0 NCO1SEL: Pin Selection bit 1 NCO1 function is on RC6 0 NCO1 function is on RC1 2011 Microchip Technology Inc. PIC16(L)F1507 U-0 U-0 U-0 — Unimplemented bit, read as 0 ...

Page 101

... Pin Name RA0 RA1 RA2 RA3 RA4 RA5 Priority listed from highest to lowest. Note 1: Default pin (see APFCON register). 2: Preliminary 11-2. Table 11-2. PORTA OUTPUT PRIORITY (1) Function Priority ICSPDAT RA0 RA1 (2) CLC1 PWM3 RA2 None CLKOUT RA4 RA5 2011 Microchip Technology Inc. ...

Page 102

... Unimplemented: Read as 1 bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 PORTA pin configured as an input (tri-stated PORTA pin configured as an output Unimplemented, read as 1. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/x R-x/x R/W-x/x RA4 RA3 RA2 U Unimplemented bit, read as 0 ...

Page 103

... Value at POR and BOR/Value at all other Resets (1) (1) R/W-1/1 U-0 R/W-1/1 ANSA4 ANSA2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. (1) . Digital input buffer disabled. Preliminary R/W-x/u R/W-x/u LATA1 LATA0 bit 0 R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 2011 Microchip Technology Inc. ...

Page 104

... Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented location, read as 0 . Shaded cells are not used by PORTA. Legend: 2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 R/W-1/1 WPUA4 WPUA3 WPUA2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (3) Bit 5 Bit 4 ...

Page 105

... TABLE 11-5: Pin Name RB4 RB5 RB6 RB7 Note 1: Priority listed from highest to lowest. Default pin (see APFCON register). 2: Preliminary 11-5. PORTB OUTPUT PRIORITY (1) Function Priority RB4 RB5 RB6 RB7 2011 Microchip Technology Inc. ...

Page 106

... Bit is cleared bit 7-4 LATB<7:4>: PORTB Output Latch Value bits bit 3-0 Unimplemented: Read as 0 Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u U-0 U-0 RB4 ...

Page 107

... TRISB4 WPUB5 WPUB4 Preliminary U-0 U-0 U-0 bit 0 U-0 U-0 U-0 bit 0 Register Bit 1 Bit 0 on Page 107 106 106 106 107 2011 Microchip Technology Inc. ...

Page 108

... The ANSELC bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to 0 by user software. 2011 Microchip Technology Inc. 11.4.2 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The ...

Page 109

... U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0 2011 Microchip Technology Inc. ...

Page 110

... RC6 TRISC TRISC7 TRISC6 WPUC WPUC7 WPUC6 Legend unknown unchanged unimplemented locations read as 0. Shaded cells are not used by PORTC. 2011 Microchip Technology Inc. U-0 R/W-1/1 R/W-1/1 ANSC3 ANSC2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) ...

Page 111

... Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep. Preliminary 2011 Microchip Technology Inc. ...

Page 112

... INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTB EXAMPLE) IOCBNx RBx IOCBPx Q4Q1 Q4Q1 2011 Microchip Technology Inc. PIC16(L)F1507 Q4Q1 Edge Detect Data Bus Write IOCBFx CK From all other IOCBFx individual Pin Detectors Q4Q1 ...

Page 113

... IOCAFx bit and IOCIF R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF4 IOCAF3 IOCAF2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCAP1 IOCAP0 bit 0 flag will be set R/W-0/0 R/W-0/0 IOCAN1 IOCAN0 bit 0 flag will be set R/W/HS-0/0 R/W/HS-0/0 IOCAF1 IOCAF0 bit 0 2011 Microchip Technology Inc. ...

Page 114

... An enabled change was detected on the associated pin. Set when IOCBPx 1 and a rising edge was detected on RAx, or when IOCANx 1 and a falling edge was detected on RBx change was detected, or the user cleared the detected change. bit 5-0 Unimplemented: Read as 0 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-0/0 U-0 U-0 IOCBP4 — ...

Page 115

... Bit 1 Bit 0 on Page ANSA1 ANSA0 103 107 INTF IOCIF 66 IOCAF1 IOCAF0 113 IOCAN1 IOCAN0 113 IOCAP1 IOCAP0 113 114 114 114 TRISA1 TRISA0 102 106 2011 Microchip Technology Inc. ...

Page 116

... NOTES: 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 116 ...

Page 117

... INTOSC is active and device is not in Sleep. BOR always enabled. BOR disabled in Sleep mode, BOR Fast Start enabled. BOR under software control, BOR Fast Start enabled. The device runs off of the Low-Power Regulator when in Sleep mode. Preliminary FVR BUFFER1 (To ADC Module) Description 2011 Microchip Technology Inc. ...

Page 118

... SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Name Bit 7 Bit 6 FVRCON FVREN FVRRDY Legend: Shaded cells are unused by the Fixed Voltage Reference module. 2011 Microchip Technology Inc. R/W-0/0 U-0 TSRNG — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition (1) ...

Page 119

... In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. Preliminary TEMPERATURE CIRCUIT DIAGRAM V DD TSEN TSRNG V OUT To ADC DD , must be high DD vs. DD RECOMMENDED V VS. DD RANGE Min TSRNG 0 DD 1.8V 2011 Microchip Technology Inc. ...

Page 120

... TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Name Bit 7 Bit 6 FVRCON FVREN FVRRDY Legend: Shaded cells are unused by the temperature indicator module. 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG Preliminary PIC16(L)F1507 Register Bit 1 ...

Page 121

... ADPREF ADPREF 10 REF REF REF 00000 00001 00010 00011 00100 00101 00110 00111 01000 ADC 01001 GO/DONE 01010 01011 ADON 11101 V SS 11110 11111 Preliminary Left Justify ADFM 1 Right Justify 16 ADRESH ADRESL 2011 Microchip Technology Inc. ...

Page 122

... DD FVR 2.048V FVR 4.096V (Not available on LF devices) See Section 13.0 Fixed Voltage Reference (FVR) for more details on the Fixed Voltage Reference. 2011 Microchip Technology Inc. PIC16(L)F1507 15.1.4 CONVERSION CLOCK The source of the conversion clock is software select- able via the ADCS bits of the ADCON1 register. There are seven possible clock options: • ...

Page 123

... ADIF bit is set, holding capacitor is connected to analog input. Preliminary ) OSC 4 MHz 1 MHz (2) 2.0 s 500 ns 1.0 s 4.0 s 2.0 s 8.0 s (3) 4.0 s 16.0 s (3) 8.0 s (3) 32.0 s (3) 16.0 s (3) 64.0 s (3) 1.0-6.0 s (1,4) 1.0-6.0 s (1, 2011 Microchip Technology Inc. ...

Page 124

... A/D CONVERSION RESULT FORMAT (ADFM 0 ) MSB bit 7 (ADFM 1 ) bit 7 Unimplemented: Read as 0 2011 Microchip Technology Inc. 15.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 15-3 shows the two output formats ...

Page 125

... Using the auto-conversion trigger does not assure proper ADC timing the users responsibility to ensure that the ADC timing requirements are met. Auto-Conversion sources are: TMR0 TMR1 TMR2 CLC1 CLC2 Preliminary 2011 Microchip Technology Inc. RC ...

Page 126

... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 15.3 A/D Acquisition Requirements. 2011 Microchip Technology Inc. EXAMPLE 15-1: ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ...

Page 127

... See Section 13.0 Fixed Voltage Reference (FVR) for more information. See Section 14.0 Temperature Indicator Module for more information. 2: DS41586A-page 127 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (2) (1) Preliminary R/W-0/0 R/W-0/0 GO/DONE ADON bit 0 2011 Microchip Technology Inc. ...

Page 128

... V REF 11 Reserved When selecting the V pin as the source of the positive reference, be aware that a minimum voltage Note 1: REF specification exists. See Section 25.0 Electrical Specifications for details. 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-0/0 U-0 U-0 — Unimplemented bit, read as 0 ...

Page 129

... This is a rising edge sensitive input for all sources. Note 1: 2: Signal also sets its corresponding interrupt flag. DS41586A-page 129 R/W-0/0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) (2) (2) (2) Preliminary U-0 U-0 bit 0 2011 Microchip Technology Inc. ...

Page 130

... Bit is set 0 Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 131

... Lower 8 bits of 10-bit conversion result DS41586A-page 131 R/W-x/u R/W-x/u R/W-x/u — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...

Page 132

... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 133

... V T  Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Transition Full-Scale V REF Transition Preliminary HOLD V - REF Sampling Switch (k ) Analog Input Voltage 1.5 LSB 2011 Microchip Technology Inc. ...

Page 134

... TRISC6 FVRCON FVREN FVRRDY x unknown unchanged, unimplemented read as 0 ’ value depends on condition. Shaded cells are not Legend: used for ADC module. Note 1: Unimplemented, read as 1 . 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ...

Page 135

... The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register. 1 Sync 8-bit Prescaler PSA 8 PS<2:0> Preliminary 2011 Microchip Technology Inc. Data Bus 8 TMR0 Set Flag bit TMR0IF on Overflow Overflow to Timer1 ...

Page 136

... Section 25.0 Electrical Specifications. 16.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 136 ...

Page 137

... Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF TMR0CS TMR0SE PSA (1) TRISA5 TRISA4 TRISA2 Preliminary R/W-1/1 R/W-1/1 PS<2:0> bit 0 Register Bit 1 Bit 0 on Page 129 INTF IOCIF 66 PS<2:0> 137 135 TRISA1 TRISA0 102 2011 Microchip Technology Inc. ...

Page 138

... NOTES: 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 138 ...

Page 139

... Prescaler T1CKPS<1:0> F OSC 01 Internal Clock F /4 OSC 00 Internal Clock Preliminary 0 Data Bus T1GVAL T1GCON Q1 EN Interrupt Set TMR1GIF det TMR1GE Synchronized 0 Clock Input 1 (3) Synchronize det OSC Sleep input Internal Clock 2011 Microchip Technology Inc. ...

Page 140

... Microchip Technology Inc. 17.2 Clock Source Selection The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. displays the clock source selections. 17.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the ...

Page 141

... T1GPOL bit of the T1GCON register. TABLE 17-4: TIMER1 GATE SOURCES T1GSS Timer1 Gate Source Timer1 Gate Pin 0 Overflow of Timer0 1 (TMR0 increments from FFh to 00h) Preliminary 2011 Microchip Technology Inc. for timing details. Timer1 Operation Counts 0 Holds Count 1 Holds Count 0 Counts 1 Table ...

Page 142

... This allows the cycle times on the Timer1 gate source to be measured. See Figure 17-6 details. 2011 Microchip Technology Inc. PIC16(L)F1507 17.5.5 TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized possible to read the most current level of the gate control value. ...

Page 143

... The device will wake- overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. Preliminary 2011 Microchip Technology Inc. ...

Page 144

... TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 17-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 144 ...

Page 145

... TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41586A-page 145 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. Cleared by software ...

Page 146

... T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16(L)F1507 Set by hardware on falling edge of T1GVAL Preliminary Cleared by hardware on falling edge of T1GVAL Cleared by software ...

Page 147

... TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 and clears Timer1 gate flip-flop DS41586A-page 147 R/W-0/u U-0 R/W-0/u T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ) OSC /4) OSC ) OSC Preliminary U-0 R/W-0/u TMR1ON bit 0 2011 Microchip Technology Inc. ...

Page 148

... Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1 Unimplemented: Read as 0 bit 0 T1GSS: Timer1 Gate Source Select bit 0 Timer1 gate pin 1 Timer0 overflow output 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U Unimplemented bit, read as ‘ ...

Page 149

... TRISA2 T1CKPS<1:0> T1SYNC T1GTM T1GSPM T1GGO/ T1GVAL DONE Preliminary Register Bit 1 Bit 0 on Page ANSA1 ANSA0 103 INTF IOCIF 66 TMR2IE TMR1IE 67 TMR2IF TMR1IF 70 143 143 TRISA1 TRISA0 102 TMR1ON 147 T1GSS 148 2011 Microchip Technology Inc. ...

Page 150

... NOTES: 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 150 ...

Page 151

... Optional use as the shift clock for the MSSP modules See Figure 18-1 for a block diagram of Timer2. FIGURE 18-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> DS41586A-page 151 TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary Sets Flag bit TMR2IF 2011 Microchip Technology Inc. ...

Page 152

... TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. 2011 Microchip Technology Inc. PIC16(L)F1507 18.3 Timer2 Output The unscaled output of TMR2 is available primarily to the PWMx module, where it is used as a time base for operation ...

Page 153

... Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 Prescaler Prescaler Prescaler Prescaler is 64 DS41586A-page 153 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 T2CKPS<1:0> bit 0 2011 Microchip Technology Inc. ...

Page 154

... T2CON TMR2 Holding Register for the 8-bit TMR2 Count Legend: unimplemented location, read as 0 . Shaded cells are not used for Timer2/4/6 module. Page provides register information. 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF — ...

Page 155

... CLC and CWG Output Polarity (PWMxPOL) (1) Clear Timer, PWMx pin and latch Duty Cycle Preliminary PWM OUTPUT TMR2 PR2 TMR2 PWM x DCH<7:0>:PWM x DCL<7:6> Output Enable (PWMxOE) TRIS Control PWMx adjusted by OSC 2011 Microchip Technology Inc. ...

Page 156

... Prescale Value) Note 1/F OSC OSC 2011 Microchip Technology Inc. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: TMR2 is cleared The PWM output is active. (Exception: When the PWM duty cycle 0%, the PWM output will remain inactive.) • ...

Page 157

... Preliminary 20 MHz) OSC 78.12 kHz 156.3 kHz 208.3 kHz 0x3F 0x1F 0x17 MHz) OSC 76.92 kHz 153.85 kHz 200.0 kHz 0x19 0x0C 0x09 2011 Microchip Technology Inc. ...

Page 158

... not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2: For operation with other peripherals only, disable PWMx pin outputs. 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 158 ...

Page 159

... PWMxPOL: PWMx Output Polarity Select bit 1 PWM output is active low 0 PWM output is active high bit 3-0 Unimplemented: Read as 0 DS41586A-page 159 R/W-0/0 U-0 U-0 PWMxPOL — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary U-0 U-0 bit 0 2011 Microchip Technology Inc. ...

Page 160

... Unimplemented locations, read as 0’ unchanged unknown. Shaded cells are not used by the PWM. Page provides register information. Note 1: Unimplemented, read as 1. 2011 Microchip Technology Inc. R/W-x/u R/W-x/u PWMxDCH<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 161

... Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset Q1 LCxEN lcxq lcx_out LCxPOL Interrupt det LCxINTP LCxINTN Interrupt det Preliminary LCxOUT D Q MLCxOUT LE LCxOE TRIS Control CLCx sets CLCxIF flag 2011 Microchip Technology Inc. ...

Page 162

... CLCxIN[14] CLCxIN[15] 2011 Microchip Technology Inc. PIC16(L)F1507 20.1.1 DATA SELECTION There are 16 signals available as inputs to the configu- rable logic. Four 8-input multiplexers are used to select the inputs to pass on to the next stage. The 16 inputs to the multiplexers are arranged in groups of four. Each group is available to two of the four multiplexers, in each case, paired with a different group ...

Page 163

... Setting the LCxPOL bit of the CLCxCON reg- ister inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled AND will cause an interrupt for the resulting output transition. NAND NOR OR Logic 0 Logic 1 Preliminary Figure 20-2. Figure 20-3. Each logic 2011 Microchip Technology Inc. ...

Page 164

... LCxINTP bit of the CLCxCON register (for a rising edge detection) LCxINTN bit of the CLCxCON register (for a fall- ing edge detection) 2011 Microchip Technology Inc. PIC16(L)F1507 PEIE and GIE bits of the INTCON register The LCxIF bit of the associated PIR registers, must be cleared in software as part of the interrupt service ...

Page 165

... LCxD3G1N lcxd2N LCxD4G1T LCxD4G1N lcxd3T (Same as Data GATE 1) lcxd3N (Same as Data GATE 1) (Same as Data GATE 1) lcxd4T lcxd4N All controls are undefined at power-up. Preliminary Data GATE 1 lcxg1 LCxG1POL Data GATE 2 lcxg2 Data GATE 3 lcxg3 Data GATE 4 lcxg4 2011 Microchip Technology Inc. ...

Page 166

... D Q lcxg1 R lcxg3 LCxMODE<2:0> 100 J-K Flip-Flop with R lcxg2 J Q lcxg1 lcxg4 K R lcxg3 LCxMODE<2:0> 110 2011 Microchip Technology Inc. PIC16(L)F1507 lcxg1 lcxg2 lcxq lcxg3 lcxg4 LCxMODE<2:0> 001 lcxg1 lcxg2 lcxg3 lcxg4 LCxMODE<2:0> 011 2-Input D Flip-Flop with R lcxg4 lcxq lcxg2 ...

Page 167

... Cell is 1-input D Flip-Flop with S and R 011 Cell is S-R latch 010 Cell is 4-input AND 001 Cell is OR-XOR 000 Cell is AND-OR DS41586A-page 167 R/W-0/0 R/W-0/0 R/W-0/0 LCxINTP LCxINTN U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 LCxMODE<2:0> bit 0 2011 Microchip Technology Inc. ...

Page 168

... The output of gate 2 is inverted when applied to the logic cell 0 The output of gate 2 is not inverted bit 0 LCxG1POL: Gate 1 Output Polarity Control bit 1 The output of gate 1 is inverted when applied to the logic cell 0 The output of gate 1 is not inverted 2011 Microchip Technology Inc. PIC16(L)F1507 U-0 R/W-x/u R/W-x/u ...

Page 169

... CLCxIN[1] is selected for lcxd1 000 CLCxIN[0] is selected for lcxd1 See Table 20-1 for signal names associated with inputs. Note 1: DS41586A-page 169 R/W-x/u U-0 R/W-x/u — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-x/u R/W-x/u LCxD1S<2:0> bit 0 2011 Microchip Technology Inc. ...

Page 170

... CLCxIN[10] is selected for lcxd3 001 CLCxIN[9] is selected for lcxd3 000 CLCxIN[8] is selected for lcxd3 See Table 20-1 for signal names associated with inputs. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u U-0 R/W-x/u — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 171

... LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit 1 lcxd1N is gated into lcxg1 0 lcxd1N is not gated into lcxg1 DS41586A-page 171 R/W-x/u R/W-x/u R/W-x/u LCxG1D3N LCxG1D2T LCxG1D2N U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u LCxG1D1T LCxG1D1N bit 0 2011 Microchip Technology Inc. ...

Page 172

... LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit 1 lcxd1T is gated into lcxg2 0 lcxd1T is not gated into lcxg2 bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit 1 lcxd1N is gated into lcxg2 0 lcxd1N is not gated into lcxg2 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u R/W-x/u R/W-x/u LCxG2D3N LCxG2D2T LCxG2D2N U Unimplemented bit, read as ‘ ...

Page 173

... LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit 1 lcxd1N is gated into lcxg3 0 lcxd1N is not gated into lcxg3 DS41586A-page 173 R/W-x/u R/W-x/u R/W-x/u LCxG3D3N LCxG3D2T LCxG3D2N U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u LCxG3D1T LCxG3D1N bit 0 2011 Microchip Technology Inc. ...

Page 174

... LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit 1 lcxd1T is gated into lcxg4 0 lcxd1T is not gated into lcxg4 bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit 1 lcxd1N is gated into lcxg4 0 lcxd1N is not gated into lcxg4 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u R/W-x/u R/W-x/u LCxG4D3N LCxG4D2T LCxG4D2N U Unimplemented bit, read as ‘ ...

Page 175

... Unimplemented: Read as 0 bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit DS41586A-page 175 U-0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. R-0 R-0 MLC2OUT MLC1OUT bit 0 ...

Page 176

... TRISB TRISB7 TRISB6 TRISC TRISC7 TRISC6 Legend: unimplemented read as 0,. Shaded cells are not used for CLC module. Unimplemented, read as 1 . Note 1: 2011 Microchip Technology Inc. Bit5 Bit4 BIt3 Bit2 ANSB5 ANSB4 ANSC3 ANSC2 ...

Page 177

... Fixed Duty Cycle (FDC) mode Pulse Frequency (PF) mode Output pulse width control Multiple clock input sources Output polarity control Interrupt capability Figure 21 simplified block diagram of the NCOx module. DS41586A-page 177 Preliminary 2011 Microchip Technology Inc. ...

Page 178

FIGURE 21-1: NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM Increment 16 (1) Buffer 16 20 NCO1CLK 11 LC1OUT 10 Accumulator F OSC 01 20 HFINTOSC 00 N xEN 2 N xCKS < 1:0 > NCOx Clock The increment ...

Page 179

... Writing to the NCOxINCH register first is neces- sary because then the buffer is loaded synchronously with the NCOx operation after the write is executed on the NCOxINCL register. Note: The increment buffer registers are not user-accessible. NCO Clock Frequency Increment Value --------------------------------------------------------------------------------------------------------------- - n 2 Preliminary 2011 Microchip Technology Inc. ...

Page 180

... The NCOx output can be used internally by source code or other peripherals. Accomplish this by reading the NxOUT (read-only) bit of the NCOxCON register. 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 180 ...

Page 181

FIGURE 21-2: FDC OUTPUT MODE OPERATION DIAGRAM Clock Source NCOx Increment Value NCOx 02000h 04000h 06000h Accumulator Input Accumulator Input Overflow NCOx 0000h 2000h 4000h Accumulator Value Overflow PWS 000 Interrupt Event NCOx Output FDC mode NCOx Output PF ...

Page 182

... APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 11.1 Alternate Pin Function for more information. 2011 Microchip Technology Inc. PIC16(L)F1507 Preliminary DS41586A-page 182 ...

Page 183

... U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets U-0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (1, 2) Preliminary U-0 R/W-0/0 NxPFM bit 0 R/W-0/0 R/W-0/0 NxCKS<1:0> bit 0 2011 Microchip Technology Inc. ...

Page 184

... W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared Unimplemented: Read as 0 bit 7-4 x bit 3-0 NCO ACC<19:16>: NCO 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<15:8> ...

Page 185

... NCOxINC<15:8>: NCOx Increment, high byte DS41586A-page 185 R/W-0/0 R/W-0/0 R/W-0/0 NCOxINC<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 NCOxINC<15:8> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-1/1 bit 0 R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...

Page 186

... TRISC TRISC7 TRISC6 Legend unknown unchanged, unimplemented read as 0 ’ value depends on condition. Shaded cells are not used for ADC module. Note 1: Unimplemented, read as 1 . 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 187

... Output enable control Output polarity control Dead-band control with independent 6-bit rising and falling edge dead-band counters Auto-shutdown control with: - Selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control DS41586A-page 187 Preliminary 2011 Microchip Technology Inc. ...

Page 188

FIGURE 22-1: CWG BLOCK DIAGRAM 1 GxCS F OSC 1 cwg_clock HFINTOSC 3 GxIS PWM1OUT PWM2OUT Input Source PWM3OUT PWM4OUT NCO1OUT LC1OUT CWG1FLT (INT pin) Auto-Shutdown GxASDS1 Source LC2OUT GxASDS0 GxASE Data Bit GxARSEN WRITE x CWG module number ...

Page 189

... PIC16(L)F1507 FIGURE 22-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band CWGxB DS41586A-page 189 Rising Edge Dead Band Falling Edge Dead Band Preliminary Rising Edge D Falling Edge Dead Band 2011 Microchip Technology Inc. ...

Page 190

... The output pin enables are dependent on the module enable bit, GxEN. When GxEN is cleared, CWG output enables and CWG drive levels have no effect. 2011 Microchip Technology Inc. PIC16(L)F1507 22.4.2 POLARITY CONTROL The polarity of each CWG output can be selected independently ...

Page 191

... When the rising and falling edges of the input source triggers the dead-band counters, the input may be asyn- chronous. This will create some uncertainty in the dead- band time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 22-1 detail. DS41586A-page 191 for more Preliminary 2011 Microchip Technology Inc. ...

Page 192

FIGURE 22-3: DEAD-BAND OPERATION, CWGxDBR 01H, CWGxDBF 02H cwg_clock Input Source CWGxA CWGxB FIGURE 22-4: DEAD-BAND OPERATION, CWGxDBR 03H, CWGxDBF 04H, SOURCE SHORTER THAN DEAD BAND cwg_clock Input Source CWGxA CWGxB source shorter than dead band ...

Page 193

... PIC16(L)F1507 EQUATION 22-1: DEAD-BAND UNCERTAINTY DEADBAND UNCERTAINTY Example: Fcwg_clock 16 MHz Therefore DEADBAND UNCERTAINTY 1 ------------------ - 16 MHz 625ns DS41586A-page 193 1 ---------------------------- - Fcwg_clock 1 ---------------------------- - Fcwg_clock Preliminary 2011 Microchip Technology Inc. ...

Page 194

... The shutdown state can- not be cleared, except by disabling auto- shutdown, as long as the shutdown input level persists. 2011 Microchip Technology Inc. PIC16(L)F1507 22.10 Operation During Sleep The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active ...

Page 195

... The GxASE bit will clear automatically when all shut- down sources go low. The overrides will remain in effect until the first rising edge event after the GxASE bit is cleared. The CWG will then resume operation. Preliminary 2011 Microchip Technology Inc. CWGxCON2 register ...

Page 196

FIGURE 22-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN 0,GxASDLA 01, GxASDLB 01) CWG Input Source Shutdown Source G x ASE CWG1A CWG1B No Shutdown FIGURE 22-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN 1,GxASDLA 01, GxASDLB 01) ...

Page 197

... Unimplemented: Read as 0 bit 0 GxCS0: CWGx Clock Source bit 1 HFINTOSC OSC DS41586A-page 197 R/W-0/0 R/W-0/0 U-0 GxPOLB GxPOLA — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition Preliminary U-0 R/W-0/0 GxCS0 bit 0 2011 Microchip Technology Inc. ...

Page 198

... GxIS<2:0>: CWGx Dead-Band Source Select bits 111 LC1OUT 110 N1OUT 101 PWM4OUT 100 PWM3OUT 011 PWM2OUT 010 PWM1OUT 001 Reserved 000 Reserved 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u U-0 R/W-0/0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition ...

Page 199

... GxASDCLC2: CWG Auto-shutdown on CLC2 Enable bit 1 Shutdown when LC2OUT is high 0 LC2OUT has no effect on shutdown DS41586A-page 199 U-0 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition Preliminary 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 GxASDFLT GxASDCLC2 bit 0 ...

Page 200

... Dead-band generation is bypassed. 2011 Microchip Technology Inc. PIC16(L)F1507 R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

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