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PIC16(L)F1782 Datasheet

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PIC16(L)F1782/3
Data Sheet
28-Pin 8-Bit Advanced Analog
Flash Microcontrollers
Preliminary
 2011-2012 Microchip Technology Inc.
DS41579C

Summary of Contents

Page 1

... Microchip Technology Inc. PIC16(L)F1782/3 28-Pin 8-Bit Advanced Analog Flash Microcontrollers Preliminary Data Sheet DS41579C ...

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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011-2012, Microchip Technology Incorporated, Printed in the U ...

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... Dead-band control with 8-bit counter - Auto-shutdown and restart - Leading and falling edge blanking - Burst mode 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Extreme Low-Power Management PIC16LF1782/3 with XLP: Sleep mode 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 kHz • ...

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... I - Debugging, Integrated on Chip Debugging, available using Debug Header. Note 1: One pin is input-only. 2: Data Sheet Index: (Unshaded devices are described in this document.) DS41579 PIC16(L)F1782/3 Data Sheet, 28-Pin Flash, 8-bit Advanced Analog MCUs. 1: Future Release PIC16(L)F1784/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs. 2: DS41579C-page 4 • ...

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... FIGURE 1: 28-PIN DIAGRAM FOR PIC16(L)F1782/3 SPDIP, SOIC, SSOP V /MCLR/RE3 PP Note: See Table 1 for the location of all peripheral functions. 2011-2012 Microchip Technology Inc. PIC16(L)F1782 RA0 3 RA1 RA2 24 5 RA3 6 23 RA4 RA5 RA7 ...

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... PIC16(L)F1782/3 FIGURE 2: 28-PIN DIAGRAM FOR PIC16(L)F1782/3 QFN, UQFN RA2 RA3 RA4 RA5 V SS RA7 RA6 See Table 1 for the location of all peripheral functions. Note: DS41579C-page RB3 2 RB2 RB1 PIC16(L)F1782 RB0 ...

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... TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1782/3) RA0 2 27 AN0 C1IN0- C2IN0- C3IN0- RA1 3 28 AN1 C1IN1- C2IN1- C3IN1- RA2 4 1 AN2 V - C1IN0 REF C2IN0 C3IN0 RA3 5 2 AN3 C1IN1 REF RA4 6 3 C1OUT (1) RA5 7 4 AN4 — ...

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... PIC16(L)F1782/3 Table of Contents 1.0 Device Overview ... 11 2.0 Enhanced Mid-Range CPU ... 17 3.0 Memory Organization ... 19 4.0 Device Configuration ... 43 5.0 Resets ... 49 6.0 Oscillator Module... 57 7.0 Reference Clock Module ... 75 8.0 Interrupts ... 79 9.0 Power-Down Mode (Sleep) ... 93 10.0 Low Dropout (LDO) Voltage Regulator ... 97 11.0 Watchdog Timer (WDT) ... 99 12.0 Date EEPROM and Flash Program Memory Control ... 103 13.0 I/O Ports ... 117 14 ...

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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Preliminary DS41579C-page 9 ...

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... PIC16(L)F1782/3 NOTES: DS41579C-page 10 Preliminary 2011-2012 Microchip Technology Inc. ...

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... DEVICE OVERVIEW The PIC16(L)F1782/3 are described within this data sheet. They are available in 28-pin packages. Figure 1-1 shows a block diagram PIC16(L)F1782/3 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 ...

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... PIC16(L)F1782/3 FIGURE 1-1: PIC16(L)F1782/3 BLOCK DIAGRAM CLKOUT Timing Generation HFINTOSC/ CLKIN LFINTOSC Oscillator MCLR Op Amps PSMCs Timer0 Temp. ADC Indicator 12-Bit See applicable chapters for more information on peripherals. Note 1: DS41579C-page 12 Program Flash Memory CPU Figure 2-1 Timer1 Timer2 MSSP Comparators FVR ...

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... TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN0-/C2IN0-/C3IN0- RA0 AN0 C1IN0- C2IN0- C3IN0- RA1/AN1/C1IN1-/C2IN1-/ RA1 C3IN1-/OPA1OUT AN1 C1IN1- C2IN1- C3IN1- OPA1OUT RA2/AN2/C1IN0/C2IN0/ RA2 C3IN0/DACOUT1/V -/ REF AN2 DACV - REF C1IN0 C2IN0 C3IN0 DACOUT V REF DACV (1) RA3/AN3/V ...

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... PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Name Function (1) RA7/V /PSMC1CLK/ RA7 REF PSMC2CLK/OSC1/CLKIN V REF PSMC1CLK PSMC2CLK OSC1 CLKIN RB0/AN12/C2IN1/PSMC1IN/ RB0 (1) PSMC2IN/CCP1 /INT AN12 C2IN1 PSMC1IN PSMC2IN CCP1 INT RB1/AN10/C1IN3-/C2IN3-/ RB1 C3IN3-/OPA2OUT AN10 C1IN3- C2IN3- C3IN3- OPA2OUT ...

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... TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Name Function (1) (1) (1) (1) RB6/TX /CK /SDI /SDA / RB6 ICSPCLK TX CK SDI SDA ICSPCLK (1) (1) RB7/DACOUT2/RX /DT / RB7 (1) (1) SCK /SCL /ICSPDAT DACOUT2 RX DT SCK SCL ICSPDAT RC0/T1OSO/T1CKI/PSMC1A RC0 T1OSO T1CKI PSMC1A (1) RC1/T1OSI/PSMC1B/CCP2 RC1 T1OSI PSMC1B CCP2 ...

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... PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Name Function RE3 RE3/MCLR/V PP MCLR Legend Analog input or output CMOS CMOS compatible input or output TTL TTL compatible input High Voltage XTAL Crystal Pin functions can be assigned to one of two locations via software. See Note 1: All pins have Interrupt-on-Change functionality ...

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... Section 3.6 Indirect Addressing 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 Instruction Set Summary details. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 for more details. for more Preliminary DS41579C-page 17 ...

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... PIC16(L)F1782/3 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control OSC1/CLKIN Timing Timing ...

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... The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. implemented for the PIC16(L)F1782/3 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1, and 3-2) ...

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... PIC16(L)F1782/3 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16F1782 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector On-chip Program Page 0 Memory Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 DS41579C-page 20 ...

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... Example 3-2 demonstrates access- ing the program memory via an FSR. The HIGH directive will set bit<7> label points to a location in program memory. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants retlw DATA0 retlw DATA1 ...

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... PIC16(L)F1782/3 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): 12 core registers 20 Special Function Registers (SFR) • bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘ ...

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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...

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... PIC16(L)F1782/3 3.3.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet ...

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... TABLE 3-3: PIC16(L)F1782/3 MEMORY MAP (BANKS 0-7) BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh 00Fh 08Fh ...

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... TABLE 3-4: PIC16(L)F1782/3 MEMORY MAP (BANKS 8-31) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch Unimplemented 510h 511h 512h 513h Unimplemented Unimplemented 514h Read as 0 Read as 0 Unimplemented 519h ...

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... TABLE 3-5: PIC16(L)F1782/3 MEMORY MAP (BANK 16 DETAILS) BANK 16 PSMC1CON 811h 831h PSMC1MDL 812h 832h PSMC1SYNC 813h 833h PSMC1CLK 814h 834h PSMC1OEN 815h 835h PSMC1POL 816h 836h PSMC1BLNK 817h 837h PSMC1REBS 818h 838h PSMC1FEBS 819h 839h PSMC1PHS 81Ah 83Ah PSMC1DCS 81Bh 83Bh ...

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... PIC16(L)F1782/3 3.3.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-7 addressed from any Bank. TABLE 3-7: CORE FUNCTION REGISTERS SUMMARY Addr Name Bit 7 Bit 6 Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 x80h (not a physical register) ...

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... Legend: Shaded locations are unimplemented, read as 0. These registers can be addressed from any bank. Note 1: Unimplemented, read as 1. 2: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 RE3 ...

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... PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addr Name Bit 7 Bit 6 Bank 2 10Ch LATA PORTA Data Latch 10Dh LATB PORTB Data Latch 10Eh LATC PORTC Data Latch 10Fh Unimplemented 110h Unimplemented 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP ...

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... Legend: Shaded locations are unimplemented, read as 0. These registers can be addressed from any bank. Note 1: Unimplemented, read as 1. 2: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 WPUA5 WPUA4 WPUA3 WPUA2 ...

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... PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addr Name Bit 7 Bit 6 Bank 7 38Ch INLVLA Input Type Control for PORTA 38Dh INLVLB Input Type Control for PORTB 38Eh INLVLC Input Type Control for PORTC 38Fh Unimplemented 390h INLVLE ...

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... Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as 1. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 P1MODE<3:0> P1MDLBIT ...

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... PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Addr Name Bit 7 Bit 6 Bank 16 (Continued) 831h PSMC2CON PSMC2EN PSMC2LD PSMC2DBFE PSMC2DBRE 832h PSMC2MDL P2MDLEN P2MDLPOL 833h PSMC2SYNC 834h PSMC2CLK 835h PSMC2OEN 836h PSMC2POL P2INPOL 837h PSMC2BLNK — ...

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... Shaded locations are unimplemented, read as 0. These registers can be addressed from any bank. Note 1: Unimplemented, read as 1. 2: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 ...

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... PIC16(L)F1782/3 3.4 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. ...

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... FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 3.5.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC ...

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... PIC16(L)F1782/3 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL DS41579C-page 38 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the ...

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... These locations are divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 0x0F Return Address 0x0E Return Address 0x0D Return Address ...

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... PIC16(L)F1782/3 FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41579C-page 40 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved ...

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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Indirect Addressing 7 FSRxH Bank Select 11111 Bank 31 Preliminary 7 ...

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... PIC16(L)F1782/3 3.6.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger ...

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... Configuration Word 2 at 8008h. The DEBUG bit in Configuration Words is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a 1. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 by device Preliminary DS41579C-page 43 ...

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... PIC16(L)F1782/3 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 FCMEN bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 7 Legend Readable bit P Programmable bit 0 Bit is cleared 1 Bit is set bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 Fail-Safe Clock Monitor and internal/external switchover are both enabled. ...

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... Data Code Protection bit is enabled, (CPD 0), the Bulk Erase Program Memory Command (through ICSP) can disable the Data Code Protection (CPD 1). When a Bulk Erase Program Memory Command is executed, the entire Program Flash Memory, Data EEPROM and configuration memory will be erased. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Preliminary DS41579C-page 45 ...

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... Unimplemented: Read as 1 bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 4 kW Flash memory (PIC16(L)F1782 only Write protection off 10 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 000h to 7FFh write-protected, no addresses may be modified by EECON control ...

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... See Section 12.5 User ID, Device ID and Configuration Accessfor more information on accessing Word these memory locations. For more information on checksum calculation, see the PIC16(L)F178X Memory Programming Specification (DS41457). 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Write Preliminary DS41579C-page 47 ...

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... PIC16(L)F1782/3 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 12.5 User ID, Device ID and Configuration for more information on accessing Word Access ...

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... Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR (1) Active See Table 5-1 for BOR active conditions. Note 1: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. PWRT R Done PWRTE LFINTOSC Preliminary Device Reset DS41579C-page 49 ...

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... PIC16(L)F1782/3 5.1 Power-On Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...

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... Unimplemented: Read as 0 bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 The Brown-out Reset circuit is active 0 The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 (1) T PWRT < T PWRT PWRT (1) T ...

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... PIC16(L)F1782/3 5.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset ...

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... FIGURE 5-3: RESET START-UP SEQUENCE V DD Internal POR Power-up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 T PWRT T MCLR T OST Preliminary DS41579C-page 53 ...

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... PIC16(L)F1782/3 5.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset condi- tions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE ...

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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 The PCON register bits are shown in R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT RMCLR Bit is set by hardware U Unimplemented bit, read as ‘ ...

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... PIC16(L)F1782/3 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN BORFS PCON STKOVF STKUNF STATUS WDTCON Legend: unimplemented location, read as 0. Shaded cells are not used by Resets. DS41579C-page 56 Bit 5 Bit 4 Bit 3 Bit 2 — ...

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... XT, HS modes) and switch automatically to the internal oscillator. Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 The oscillator module can be configured in one of eight clock modes. 1. ECL External Clock Low-Power mode (0 MHz to 0 ...

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... PIC16(L)F1782/3 FIGURE 6-1: SIMPLIFIED PIC Timer1 Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI External LP, XT, HS, RC, EC Oscillator OSC2 Sleep PRIMUX OSC1 Internal Oscillator Block HFPLL 16 MHz (HFINTOSC) 500 kHz 500 kHz Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) PLLEN or SCS FOSC<2:0> SPLLEN 0 100 ...

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... High power, 4-32 MHz (FOSC 111) Medium power, 0.5-4 MHz (FOSC 110) Low power, 0-0.5 MHz (FOSC 101) 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

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... PIC16(L)F1782/3 FIGURE 6-3: QUARTZ CRYSTAL OPERATION (LP MODE) ® PIC MCU OSC1/CLKIN C1 Quartz ( Crystal OSC2/CLKOUT ( Note 1: A series resistor (R ) may be required for S quartz crystals with low drive level. 2: The value of R varies with the Oscillator mode F selected (typically between 2 M M. ...

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... MCU T1OSI C1 32.768 kHz Quartz Crystal T1OSO C2 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Note 1: Quartz according manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. Section 30.0 2: Always verify oscillator performance over the V expected for the application. ...

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... PIC16(L)F1782/3 6.2.1.6 External RC Mode The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words ...

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... OSCCON register to 1x The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 6.2.2.3 The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by (Register 6-3) ...

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... PIC16(L)F1782/3 6.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure Internal Oscillator Frequency Select bits IRCF< ...

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... Clock switching time delays are shown in Table 6-1. Start-up delay specifications are located in the oscillator tables of Section 30.0 Specifications. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Electrical Preliminary DS41579C-page 65 ...

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... PIC16(L)F1782/3 FIGURE 6-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC 0 IRCF <3:0> System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time ...

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... OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the Timer1 oscillator. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 6.3.3 TIMER1 OSCILLATOR The Timer1 oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...

Page 68

... PIC16(L)F1782/3 6.4 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device ...

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... OSC2 Program Counter System Clock 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 6.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator ...

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... PIC16(L)F1782/3 6.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words ...

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... Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Oscillator Failure Test Test Preliminary Failure Detected ...

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... PIC16(L)F1782/3 6.6 Register Definitions: Oscillator Control REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 SPLLEN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) ...

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... LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 LFINTOSC is ready 0 LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 HFINTOSC is at least 0.5% accurate 0 HFINTOSC is not 0.5% accurate 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

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... PIC16(L)F1782/3 REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 Minimum frequency ...

Page 75

... The users firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 7.3 Conflicts with the CLKR Pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...

Page 76

... PIC16(L)F1782/3 7.5 Register Definition: Reference Clock Control REGISTER 7-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit ...

Page 77

... Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented locations read as 0. Shaded cells are not used by reference clock sources. Legend: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC<1:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE1< ...

Page 78

... PIC16(L)F1782/3 NOTES: DS41579C-page 78 Preliminary 2011-2012 Microchip Technology Inc. ...

Page 79

... A block diagram of the interrupt logic is shown in Figure 8-1. FIGURE 8-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 TMR0IF TMR0IE INTF INTE IOCIF IOCIE PEIE GIE Preliminary Wake-up (If in Sleep mode) ...

Page 80

... PIC16(L)F1782/3 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: GIE bit of the INTCON register Interrupt Enable bit(s) for the specific interrupt event(s) PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the ...

Page 81

... Execute 2 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Interrupt Sampled during Q1 PC1 0004h Inst(PC) NOP NOP PC1/FSR New PC/ 0004h ADDR PC1 Inst(PC) NOP NOP FSR ADDR ...

Page 82

... PIC16(L)F1782/3 FIGURE 8-3: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) INTF (5) GIE INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. ...

Page 83

... ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the users appli- cation, other registers may also need to be saved. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Section 9.0 Preliminary DS41579C-page 83 ...

Page 84

... PIC16(L)F1782/3 8.6 Register Definitions: Interrupt Control REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 GIE PEIE TMR0IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 Enables all active interrupts ...

Page 85

... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 Enables the Timer1 overflow interrupt 0 Disables the Timer1 overflow interrupt Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSPIE CCP1IE U Unimplemented bit, read as 0 ...

Page 86

... PIC16(L)F1782/3 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 Enables the Oscillator Fail interrupt ...

Page 87

... PSMC1SIE: PSMC1 Auto-Shutdown Interrupt Enable bit 1 Enables PSMC1 auto-shutdown interrupts 0 Disables PSMC1 auto-shutdown interrupts Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 U-0 U-0 PSMC1TIE — Unimplemented bit, read as 0 ...

Page 88

... PIC16(L)F1782/3 REGISTER 8-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 TMR1GIF ADIF RCIF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending ...

Page 89

... Global Enable bit, GIE, of the INTCON register. User software should appropriate interrupt flag bits are clear prior to enabling an interrupt. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 EEIF BCLIF U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ensure ...

Page 90

... PIC16(L)F1782/3 REGISTER 8-7: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER42 U-0 U-0 R/W-0/0 PSMC2TIF bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-6 Unimplemented: Read as 0 bit 5 PSMC2TIF: PSMC2 Time Base Interrupt Flag bit ...

Page 91

... PIR1 TMR1GIF ADIF PIR2 OSFIF C2IF PIR4 unimplemented location, read as 0. Shaded cells are not used by interrupts. Legend: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF TMR0CS TMR0SE PSA RCIE ...

Page 92

... PIC16(L)F1782/3 NOTES: DS41579C-page 92 Preliminary 2011-2012 Microchip Technology Inc. ...

Page 93

... Module Section 15.0 Fixed Volt- age Reference (FVR) for more information on these modules. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...

Page 94

... PIC16(L)F1782/3 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP ...

Page 95

... Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 9.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected ...

Page 96

... PIC16(L)F1782/3 9.3 Register Definitions: Voltage Regulator Control REGISTER 9-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-2 Unimplemented: Read as 0 bit 1 VREGPM: Voltage Regulator Power Mode Selection bit ...

Page 97

... Shaded cells are not used by LDO. Note 1: Not implemented on PIC16LF1782/3. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor ...

Page 98

... PIC16(L)F1782/3 NOTES: DS41579C-page 98 Preliminary 2011-2012 Microchip Technology Inc. ...

Page 99

... Configurable time-out period is from 256 seconds (nominal) Multiple Reset conditions Operation during Sleep FIGURE 11-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41579C-page 99 ...

Page 100

... PIC16(L)F1782/3 11.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1ms. See Section 30.0 Electrical Specifications LFINTOSC tolerances. 11.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE< ...

Page 101

... If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as 0 -m/n Value at POR and BOR/Value at all other Resets (1) ...

Page 102

... PIC16(L)F1782/3 TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 OSCCON SPLLEN STATUS WDTCON Legend unknown unchanged, unimplemented locations read as 0. Shaded cells are not used by Watchdog Timer. TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER ...

Page 103

... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 12.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...

Page 104

... PIC16(L)F1782/3 12.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program vari- ables or other data that are updated often). When vari- ables in one section change frequently, while variables ...

Page 105

... Flash ADDR Flash Data INSTR (PC) BSF PMCON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 EEADRH,EEADRL PC3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...

Page 106

... PIC16(L)F1782/3 12.3 Flash Program Memory Overview It is important to understand the Flash program mem- ory structure for erase and programming operations. Flash Program memory is arranged in rows. A row con- sists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software ...

Page 107

... Initiate read NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 (Figure 12-1) (Figure 12-1) Preliminary DS41579C-page 107 ...

Page 108

... PIC16(L)F1782/3 12.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. Load the EEADRH:EEADRL register pair with the address of new row to be erased. 2. Clear the CFGS bit of the EECON1 register. 3. Set the EEPGD, FREE, and WREN bits of the EECON1 register ...

Page 109

... MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2011-2012 Microchip Technology Inc. PIC16(L)F1782 EEDATH EEDATA 6 14 EEADRL<4:0> 00010 Buffer Register Buffer Register Program Memory ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ...

Page 110

... PIC16(L)F1782/3 EXAMPLE 12-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following The 16 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits 000) is loaded in ADDRH:ADDRL ...

Page 111

... EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 12.5 User ID, Device ID and Configuration Word Access Instead of accessing program memory or EEPROM data memory, the User IDs, Device ID/Revision ID and Configuration Words can be accessed when CFGS 1 in the EECON1 register. This is the region that would be pointed to by PC< ...

Page 112

... PIC16(L)F1782/3 12.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 12-6) to the desired value to be written. Example 12-6 shows how to verify a write to EEPROM. EXAMPLE 12-6: EEPROM WRITE VERIFY BANKSEL EEDATL ...

Page 113

... Unimplemented: Read as 1 bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address Unimplemented, read as 1. Note 1: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 114

... PIC16(L)F1782/3 REGISTER 12-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 EEPGD CFGS LWLO bit 7 Legend Readable bit W Writable bit S Bit can only be set x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 Accesses program space Flash memory ...

Page 115

... Shaded cells are not used by data EEPROM module. Legend: Page provides register information. 2: Unimplemented, read as 1. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 W-0/0 W-0/0 EEPROM Control Register Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Section 12.2.2 Writing to the Data EEPROM ...

Page 116

... PIC16(L)F1782/3 DS41579C-page 116 Preliminary 2011-2012 Microchip Technology Inc. ...

Page 117

... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 FIGURE 13-1: D Write LATx Write PORTx Data Register ...

Page 118

... PIC16(L)F1782/3 13.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 13-1. For this device family, the following functions can be moved between different pins. C2OUT output • ...

Page 119

... RXSEL: RX Pin Selection bit pin RB7 pin RC7 bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 1 CCP2 is on pin RB3 0 CCP2 is on pin RC1 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 R/W-0/0 SCKSEL SDISEL TXSEL U Unimplemented bit, read as 0 ...

Page 120

... PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See PIC16(L)F1782/3-I/E (Industrial, Extended) information on threshold levels. Changing the input threshold selection Note: should be performed while all peripheral 13-2) reads the modules are disabled ...

Page 121

... Pin Name Function Priority RA0 RA0 RA1 OPA1OUT RA1 RA2 DACOUT1 RA2 RA3 RA3 RA4 C1OUT RA4 RA5 C2OUT RA5 RA6 CLKOUT C2OUT RA6 RA7 RA7 Priority listed from highest to lowest. Note 1: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 (1) Preliminary DS41579C-page 121 ...

Page 122

... PIC16(L)F1782/3 13.4 Register Definitions: PORTA REGISTER 13-2: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RA<7:0>: PORTA I/O Value bits 1 Port pin is > Port pin is < V ...

Page 123

... Pull-up enabled 0 Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is in configured as an output. 2: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-1/1 R/W-1/1 R/W-1/1 ANSA4 ANSA3 ANSA2 U Unimplemented bit, read as 0 ...

Page 124

... PIC16(L)F1782/3 REGISTER 13-7: ODCONA: PORTA OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 ODA7 ODA6 ODA5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 ODA<7:0>: PORTA Open Drain Enable bits For RA<7:0> pins, respectively 1 Port pin operates as open-drain drive (sink current only) ...

Page 125

... Name Bits Bit -/7 Bit -/6 13:8 CONFIG1 7:0 CP MCLRE unimplemented location, read as 0. Shaded cells are not used by PORTA. Legend: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 ANSA5 ANSA4 ANSA3 ANSA2 INLVLA5 INLVLA4 INLVLA3 INLVLA2 LATA5 ...

Page 126

... CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTB register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See PIC16(L)F1782/3-I/E (Industrial, Extended) information on threshold levels. 13-10) reads the Changing the input threshold selection Note: should be performed while all peripheral modules are disabled ...

Page 127

... RB0 RB1 OPA2OUT RB1 RB2 CLKR RB2 RB3 CCP2 RB3 RB4 RB4 RB5 SDO C3OUT RB5 RB6 ICSPCLK SDA TX/CK RB6 RB7 ICSPDAT DACOUT2 SCL/SCK DT RB7 Note 1: Priority listed from highest to lowest. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 (1) Preliminary DS41579C-page 127 ...

Page 128

... PIC16(L)F1782/3 13.6 Register Definitions: PORTB REGISTER 13-10: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 RB<7:0>: PORTB General Purpose I/O Pin bits 1 Port pin is > Port pin is < V ...

Page 129

... Pull-up enabled 0 Pull-up disabled Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. 2: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U Unimplemented bit, read as 0 ...

Page 130

... PIC16(L)F1782/3 REGISTER 13-15: ODCONB: PORTB OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 ODB7 ODB6 ODB5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 ODB<7:0>: PORTB Open Drain Enable bits For RB<7:0> pins, respectively 1 Port pin operates as open-drain drive (sink current only) ...

Page 131

... SLRB7 SLRB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 x unknown unchanged unimplemented locations read as 0. Shaded cells are not used by Legend: PORTB. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 INLVLB5 INLVLB4 INLVLB3 INLVLB2 ...

Page 132

... The input threshold is important in determining the value of a read of the PORTC register and also the level at which an interrupt-on-change occurs, if that DS41579C-page 132 feature is enabled. See istics: PIC16(L)F1782/3-I/E (Industrial, Extended) for more information on threshold levels. Changing the input threshold selection Note: is ...

Page 133

... Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U Unimplemented bit, read as 0 ...

Page 134

... PIC16(L)F1782/3 REGISTER 13-21: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 R/W-1/1 R/W-1/1 WPUC7 WPUC6 WPUC5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 WPUC<7:0>: Weak Pull-up Register bits 1 Pull-up enabled 0 Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. ...

Page 135

... RC7 RC6 SLRCONC SLRC7 SLRC6 x unknown unchanged unimplemented locations read as 0. Shaded cells are not used by Legend: PORTC. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-1/1 R/W-1/1 R/W-1/1 INLVLC4 INLVLC3 INLVLC2 U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

Page 136

... The input threshold is important in determining the value of a read of the PORTE register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Section 30.1 DC Characteristics: PIC16(L)F1782/3-I/E (Industrial, Extended) information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled ...

Page 137

... Unimplemented: Read as 0 Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is in configured as an output. 2: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 (1) U-0 U-1 U-0 ...

Page 138

... PIC16(L)F1782/3 REGISTER 13-28: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER U-0 U-0 U-0 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-4 Unimplemented: Read as 0 bit 3 INLVLE3: PORTE Input Level Select bit ...

Page 139

... A pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in both of the IOCxP and IOCxN registers. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 14.3 Interrupt Flags The bits located in the IOCxF registers are status flags that correspond to the Interrupt-on-change pins of each port ...

Page 140

... PIC16(L)F1782/3 FIGURE 14-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx RBx IOCBPx Q4Q1 Q4Q1 DS41579C-page 140 Q4Q1 edge detect data bus write IOCBFx CK from all other IOCBFx individual pin detectors Q4Q1 ...

Page 141

... Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge Interrupt-on-Change disabled for the associated pin. For IOCEN register, bit 3 (IOCEN3) is the only implemented bit in the register. Note 1: 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 R/W-0/0 IOCxP4 IOCxP3 IOCxP2 U Unimplemented bit, read as ‘ ...

Page 142

... PIC16(L)F1782/3 REGISTER 14-3: IOCxF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCxF7 IOCxF6 IOCxF5 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 IOCxF<7:0>: Interrupt-on-Change Flag bits enabled change was detected on the associated pin. ...

Page 143

... Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the FVRCON register. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 15.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers ...

Page 144

... PIC16(L)F1782/3 FIGURE 15-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> HFINTOSC Enable FVREN Any peripheral requiring the Fixed Reference (See Table 15-1) TABLE 15-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral Conditions HFINTOSC FOSC<2:0> 100 and IRCF<3:0> 000x BOREN<1:0> BOR BOREN<1:0> and BORFS 1 BOREN< ...

Page 145

... Name Bit 7 Bit 6 FVRCON FVREN FVRRDY Legend: Shaded cells are not used with the Fixed Voltage Reference. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 R/W-0/0 TSRNG CDAFVR<1:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition ...

Page 146

... PIC16(L)F1782/3 NOTES: DS41579C-page 146 Preliminary 2011-2012 Microchip Technology Inc. ...

Page 147

... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 FIGURE 16-1: 16.2 Minimum Operating V Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications ...

Page 148

... PIC16(L)F1782/3 NOTES: DS41579C-page 148 Preliminary 2011-2012 Microchip Technology Inc. ...

Page 149

... When ADON 0, all multiplexer inputs are disconnected. Note 1: See ADCON0 register 2: analog channel selection per device. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of (ADC) allows a conversion ...

Page 150

... PIC16(L)F1782/3 17.1 ADC Configuration When configuring and using the ADC the following functions must be considered: Port configuration Channel selection - Single-ended - Differential ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 17.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...

Page 151

... sign b11 b10 Conversion starts Holding cap disconnected Set GO from input bit Input Sample 2011-2012 Microchip Technology Inc. PIC16(L)F1782 DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns 250 ns (2) (2) 0.5  ...

Page 152

... PIC16(L)F1782/3 17.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...

Page 153

... A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 17.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...

Page 154

... PIC16(L)F1782/3 17.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: Disable pin output driver (Refer to the TRIS register) Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: Select ADC conversion clock • ...

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... Section 19.0 Digital-to-Analog Converter (DAC) Module 2: See Section 15.0 Fixed Voltage Reference (FVR) See 3: Section 16.0 Temperature Indicator Module 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets (2) (1) (3) for more information ...

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... PIC16(L)F1782/3 REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 ADFM: A/D Result Format Select bit (see 1 2s complement format Sign-magnitude result format. bit 6-4 ADCS< ...

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... Reserved. No channel connected. 0110 Reserved. No channel connected. 0101 Reserved. No channel connected. 0100 AN4 0011 AN3 0010 AN2 0001 AN1 0000 AN0 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 R/W-0/0 CHSN<3:0> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 ...

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... PIC16(L)F1782/3 REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM 0 R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 AD<11:4> : ADC Result Register bits Upper 8 bits of 12-bit conversion result REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM 0 ...

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... Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7-0 AD<7:0> : ADC Result Register bits Least significant 8 bits of 12-bit conversion result 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-x/u R/W-x/u R/W-x/u AD<11:8> Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets R/W-x/u ...

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... PIC16(L)F1782/3 17.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The Analog Input model is shown in Figure 17-4. The source impedance (R ) and the internal sampling switch (R S impedance directly affect the time required to charge the capacitor C ...

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... Section 30.0 Electrical Specifications FIGURE 17-5: ADC TRANSFER FUNCTION FFFh FFEh FFDh FFCh FFBh 03h 02h 01h 00h 0.5 LSB Zero-Scale V - REF Transition 2011-2012 Microchip Technology Inc. PIC16(L)F1782 Sampling Switch 0.  Rss R IC LEAKAGE (1) I 0. ...

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... PIC16(L)F1782/3 TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Name Bit 7 Bit 6 ADCON0 ADCON1 ADFM ADCS<2:0> ADCON2 TRIGSEL<3:0> ADRESH A/D Result Register High ADRESL A/D Result Register Low ANSELA ANSA7 ANSELB INTCON GIE PEIE TMR1GIE PIE1 ADIE TMR1GIF PIR1 ADIF ...

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... External connections to I/O ports Selectable Gain Bandwidth Product Low leakage inputs Factory Calibrated Input Offset Voltage FIGURE 18-1: OPAx MODULE BLOCK DIAGRAM OPAxIN DAC_output FVR Buffer 2 OPAxNCH<1:0> 2011-2012 Microchip Technology Inc. PIC16(L)F1782 OPA OPAxIN- 11 Preliminary OPA EN X OPA ...

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... PIC16(L)F1782/3 18.1 Effects of Reset A device Reset forces all registers to their Reset state. This disables the OPA module. 18.2 OPA Module Performance Common AC and DC performance specifications for the OPA module: Common Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain • ...

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... TRISB6 TRISC TRISC7 TRISC6 Legend: unimplemented location, read as 0. Shaded cells are not used by op amps. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 U-0 U-0 — Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets q Value depends on condition ...

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... PIC16(L)F1782/3 NOTES: DS41579C-page 166 Preliminary 2011-2012 Microchip Technology Inc. ...

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... DACOUTx Figure 19-2 shows an example buffering technique. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 19.1 Output Voltage Selection The DAC has 256 voltage level ranges. The 256 levels are set with the DACR<7:0> bits of the DACCON1 register. The DAC output voltage is determined by  ...

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... PIC16(L)F1782/3 FIGURE 19-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACNSS V - REF V SS FIGURE 19-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41579C-page 168 Digital-to-Analog Converter (DAC) V SOURCE ...

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... Effects of a Reset A device Reset affects the following: DAC is disabled. DAC output voltage is removed from the DACOUT pin. The DACR<4:0> range select bits are cleared. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Preliminary DS41579C-page 169 ...

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... PIC16(L)F1782/3 19.6 Register Definitions: DAC Control REGISTER 19-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 DACEN DACOE1 bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 DACEN: DAC Enable bit 1 DAC is enabled 0 DAC is disabled bit 6 Unimplemented: Read as ‘ ...

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... the output of the comparator is a digital high level. IN The comparators available for this device are located in Table 20-1. TABLE 20-1: COMPARATOR AVAILABILITY PER DEVICE Device C1 PIC16(L)F1782 PIC16(L)F1783 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 FIGURE 20- Output ...

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... PIC16(L)F1782/3 FIGURE 20-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON 3 C IN0 IN1 MUX C IN2- X (2) C IN3 CxVN Reserved 4 - Reserved Reserved 6 CxVP 7 CxHYS AGND CxSP 0 C IN0 IN1 X MUX (2) 2 Reserved 3 Reserved 4 Reserved DAC_ utput ...

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... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 20.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by 20-1) contain setting the CxPOL bit of the CMxCON0 register ...

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... PIC16(L)F1782/3 20.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Section 30.0 Electrical Specifications more information. 20.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1 ...

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... T has expired so output change of ZLF is immediate based on ZLF comparator output change 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 20.9 Zero Latency Filter In high-speed operation, and under proper circuit conditions possible for the comparator output to oscillate. This oscillation can have adverse effects on the hardware and software relying on this signal ...

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... PIC16(L)F1782/3 20.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 20-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes analog input, therefore, must be between V If the input voltage deviates from this range by more than 0 ...

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... CxSYNC: Comparator Output Synchronous Mode bit 1 Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 R/W-1/1 CxPOL CxZLF CxSP U Unimplemented bit, read as ‘ ...

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... PIC16(L)F1782/3 REGISTER 20-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 CxINTP CxINTN bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit ...

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... TRISA TRISA7 TRISA6 TRISB TRISB7 TRISB6 TRISC TRISC7 TRISC6 Legend: unimplemented location, read as 0. Shaded cells are unused by the comparator module. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 ANSA5 ANSA4 ANSA3 ANSA2 ANSB5 ANSB4 ANSB3 ...

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... PIC16(L)F1782/3 NOTES: DS41579C-page 180 Preliminary 2011-2012 Microchip Technology Inc. ...

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... T0CKI 1 TMR0SE TMR0CS 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 21.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...

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... PIC16(L)F1782/3 21.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...

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... TRISA TRISA7 TRISA6 Legend: Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module. Page provides register information. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

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... PIC16(L)F1782/3 NOTES: DS41579C-page 184 Preliminary 2011-2012 Microchip Technology Inc. ...

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... Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 22 block diagram of the Timer1 module ...

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... PIC16(L)F1782/3 22.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...

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... When switching from asynchronous to synchronous operation possible to produce an additional increment. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 22.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...

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... PIC16(L)F1782/3 22.6.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 22-4: TIMER1 GATE SOURCES ...

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... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 22.9 CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

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... PIC16(L)F1782/3 FIGURE 22-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 22-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41579C-page 190 Preliminary 2011-2012 Microchip Technology Inc. ...

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... T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41579C-page 191 ...

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... PIC16(L)F1782/3 FIGURE 22-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41579C-page 192 Set by hardware on falling edge of T1GVAL Preliminary  ...

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... Synchronize asynchronous clock input with system clock (F bit 1 Unimplemented: Read as 0 bit 0 TMR1ON: Timer1 On bit 1 Enables Timer1 0 Stops Timer1 and clears Timer1 gate flip-flop 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets ...

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... PIC16(L)F1782/3 REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W Writable bit u Bit is unchanged x Bit is unknown 1 Bit is set 0 Bit is cleared bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON 0 : This bit is ignored If TMR1ON Timer1 counting is controlled by the Timer1 gate function ...

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... T1CON TMR1CS<1:0> T1GCON TMR1GE T1GPOL unimplemented location, read as 0. Shaded cells are not used by the Timer1 module. Legend: Page provides register information. 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 DC1B<1:0> DC2B<1:0> ...

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... PIC16(L)F1782/3 NOTES: DS41579C-page 196 Preliminary 2011-2012 Microchip Technology Inc. ...

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... Optional use as the shift clock for the MSSP mod- ule See Figure 23-1 for a block diagram of Timer2. FIGURE 23-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 Reset TMR2 TMR2 Output Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary Sets Flag bit TMR2IF DS41579C-page 197 ...

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... PIC16(L)F1782/3 23.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (F /4). OSC TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS< ...

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... TMR2ON: Timer2 On bit 1 Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 11 Prescaler Prescaler Prescaler Prescaler is 1 2011-2012 Microchip Technology Inc. PIC16(L)F1782/3 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U Unimplemented bit, read as 0 -n/n Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 T2CKPS< ...

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... PIC16(L)F1782/3 TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Name Bit 7 Bit 6 CCP2CON P2M<1:0> INTCON GIE PEIE PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF PR2 Timer2 Module Period Register T2CON TMR2 Holding Register for the 8-bit TMR2 Register Legend: unimplemented location, read as 0. Shaded cells are not used for Timer2 module. ...

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