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PIC12F529T48A Datasheet

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PIC12F529T48A
Data Sheet
14-Pin, 8-Bit Flash Microcontrollers
Preliminary
 2012 Microchip Technology Inc.
DS41634A

Summary of Contents

Page 1

... Flash Microcontrollers 2012 Microchip Technology Inc. PIC12F529T48A Data Sheet Preliminary DS41634A ...

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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2012, Microchip Technology Incorporated, Printed in the U ...

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... INTRC: 4 MHz or 8 MHz precision internal RC oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - LP: Power-saving, low-frequency crystal 2012 Microchip Technology Inc. PIC12F529T48A Low-Power Features/CMOS Technology: Standby Current: - 250 nA @ 2.0V, RF Sleep, typical Operating Current: - 170 µ MHz, 2.0V, RF Sleep, typical - 9. MHz, 2.0V dBm, typical - 16 ...

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... PIC12F529T48A FIGURE 1: 14-PIN DIAGRAM, PIC12F529T48A TSSOP GB5/OSC1/CLKIN GB4/OSC2 GB3/MCLR/V Program Data Memory Memory Device Flash SRAM (words) (bytes) PIC12F529T48A 1536 201 DS41634A-page 4 V Vss GB0/ICSPDAT 13 2 GB1/ICSPCLK 12 3 GB2/T0CKI XTAL V DDRF 10 5 CTRL 6 DATA 9 RF OUT SSRF I/O RF Transmitter Comparators Timers (8-bit) ...

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... Table of Contents 1.0 General Description ... 7 2.0 PIC12F529T48A Device Varieties ... 9 3.0 Architectural Overview ... 11 4.0 Memory Organization ... 15 5.0 Flash Data Memory ... 23 6.0 I/O Port ... 25 7.0 Timer0 Module and TMR0 Register ... 33 8.0 Special Features Of The CPU ... 39 9.0 RF Transmitter ... 51 10.0 Instruction Set Summary ... 55 11.0 Development Support ... 63 12.0 Electrical Characteristics ... 67 13.0 DC and AC Characteristics Graphs and Charts ... 79 14.0 Packaging Information ... 87 Index ...

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... PIC12F529T48A NOTES: DS41634A-page 6 Preliminary 2012 Microchip Technology Inc. ...

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... Packages Note 1: The PIC12F529T48A device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. 2: The PIC12F529T48A device uses serial programming with data pin GP0 and clock pin GP1. 2012 Microchip Technology Inc. PIC12F529T48A 1.1 Applications ...

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... PIC12F529T48A NOTES: DS41634A-page 8 Preliminary 2012 Microchip Technology Inc. ...

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... PIC12F529T48A DEVICE VARIETIES When placing orders, please use the PIC12F529T48A Product Identification System at the back of this data sheet to specify the correct part number. Depending on application and production requirements, the proper device option can be selected using the information in this section. 2.1 Quick Turn Programming (QTP) ...

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... PIC12F529T48A NOTES: DS41634A-page 10 Preliminary 2012 Microchip Technology Inc. ...

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... PIC12F529T48A device simple, yet efficient. In addition, the learning curve is reduced significantly. The PIC12F529T48A device contains an 8-bit ALU and working register. The ALU is a general purpose arith- metic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.  ...

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... Decode & Reset Control Watchdog Timer Timing OSC1/CLKIN Internal RC Generation OSC2 Clock MCLR Note 1: 201-byte GPR in PIC12F529T48A, including linear RAM. 2: FSR and direct addressing differs from standard baseline parts. DS41634A-page 12 8 Data Bus RAM 201 bytes GPR 8 RAM Addr Addr MUX Indirect ...

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... TABLE 3-2: PIC12F529T48A PINOUT DESCRIPTION Name Function Type GP0/ICSPDAT GP0 I/O ICSPDAT I/O GP1/ICSPCLK GP1 I/O ICSPCLK I GP2/T0CKI GP2 I/O T0CKI I GP3/MCLR/V GP3 I PP MCLR GP4/OSC2 GP4 I/O OSC2 O GP5/OSC1/ GP5 I/O CLKIN OSC1 I CLKIN DDRF DDRF CTRL CTRL ...

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... PIC12F529T48A 3.1 Clocking Scheme/Instruction Cycle The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4 decoded and executed during the following Q1 through Q4 ...

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... Data memory banks are accessed using the File Select Register (FSR). 4.1 Program Memory Organization for the PIC12F529T48A The PIC12F529T48A device has an 11-bit Program Counter (PC) capable of addressing program memory space. Only the first 1. (0000h-05FFh) are physically implemented (see Figure 4-1) ...

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... I/O register (port) and the File Select Register (FSR). In addition, the EECON, EEDATA and EEADR registers provide for interface with the Flash data memory. The PIC12F529T48A register file is composed of 10 Special Function Registers and 201 General Purpose Registers. 4.2.1 GENERAL PURPOSE REGISTER ...

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... Note 1: The upper byte of the Program Counter is not directly accessible. See access these bits. 2012 Microchip Technology Inc. PIC12F529T48A 4.2.3 LINEAR RAM The last four banks, addresses 0x80 to 0xFF, are general purpose RAM registers, unbroken by SFRs. This region is ideal for indirect access using the FSR and INDF registers ...

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... PIC12F529T48A 4.3 STATUS register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the bits, then the write to these three bits is disabled ...

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... Microchip Technology Inc. PIC12F529T48A By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION regis- ter. A Reset sets the OPTION<7:0> bits. Note: If the T0SC bit is set to 1, it will override the TRIS function on the T0CKI pin. ...

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... PIC12F529T48A 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the 8 MHz internal oscillator macro. It contains seven bits of calibration that uses a twos complement scheme for controlling the oscillator speed. See Register 4-3 for details. REGISTER 4-3: OSCCAL: OSCILLATOR CALIBRATION REGISTER R/W-1 R/W-1 R/W-1 CAL6 CAL5 ...

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... Stack The PIC12F529T48A device has a four-deep, 12-bit wide hardware PUSH/POP stack. A CALL instruction will PUSH the current value of Stack 1 into Stack 2 and then PUSH the current PC value, incremented by one, into Stack Level 1. If more than four sequential CALLs are executed, only the most recent four return addresses are stored ...

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... PIC12F529T48A 4.8 Indirect Data Addressing: INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. Reading INDF itself indirectly (FSR 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected) ...

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... If there is other information in that row that must be saved, copy those bytes from Flash data memory to RAM. 2012 Microchip Technology Inc. PIC12F529T48A 3. Perform a row erase of the row of interest. 4. Write the new byte of data and any saved bytes back to the appropriate addresses in Flash data memory ...

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... PIC12F529T48A 5.2.2 WRITING TO FLASH DATA MEMORY Once a cell is erased, new data can be written. Program execution is suspended during the write cycle. The following sequence must be performed for a single byte write. 1. Load EEADR with the address. 2. Load EEDATA with the data to write. 3. Set the WREN bit to enable write access to the array ...

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... If GP3/MCLR is configured as MCLR, weak pull always on and wake-up on change for this pin is not enabled. 2012 Microchip Technology Inc. PIC12F529T48A 6.2 TRIS Registers The Output Driver Control registers are loaded with the contents of the W register by executing the TRIS f instruction. A ‘ ...

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... PIC12F529T48A REGISTER 6-1: GPIO: GPIO REGISTER U-0 U-0 R/W-x GP5 bit 7 Legend Readable bit W Writable bit -n Value at POR 1 Bit is set bit 7-6 Unimplemented: Read as 0 bit 5-0 GP<5:0>: GPIO I/O Pin bits 1 GPIO pin is >V min GPIO pin is

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... TRISGPIO must be cleared ( 0). For use as an input, the corresponding TRISGPIO bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output. FIGURE 6-1: PIC12F529T48A EQUIVALENT CIRCUIT FOR I/O PINS GP0/GP1 GPPU Data D Data Latch WR ...

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... PIC12F529T48A FIGURE 6-2: GP2/TOCK1 General Purpose I/O A Clock Input for Timer0 D Data Data Latch WR CK WREG D TRIS Latch TRIS F CK TOCS RD Port To Timer0 DS41634A-page Preliminary V DD I/O Pin V SS 2012 Microchip Technology Inc. ...

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... FIGURE 6-3: GP4/OSC2 General Purpose I/O A crystal resonator connection DATA D BUS Data Latch WR CK PORT WREG D TRIS Latch CK TRIS F INTOSC RC RD PORT 2012 Microchip Technology Inc. PIC12F529T48A From OSC1 Oscillator Circuit Preliminary V DD I/O Pin V SS DS41634A-page 29 ...

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... PIC12F529T48A FIGURE 6-4: GP5/OSC1/CLKIN From OSC2 Q DATA D BUS Data Latch PORT Q WREG D TRIS Latch CK TRIS F’ PORT DS41634A-page 30 V Oscillator Circuit V General Purpose I/O A crystal resonator connection A clock input Preliminary 2012 Microchip Technology Inc. DD I/O Pin SS ...

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... STATUS GPWUF PA1 PA0 OPTION GPWU GPPU T0CS Legend unknown unchanged, unimplemented, read as 0, Shaded cells unimplemented, read as 0’ depends on the condition 2012 Microchip Technology Inc. PIC12F529T48A Weak (1) Input Pin Bit 4 Bit 3 Bit 2 GP4 GP3 GP2 ...

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... PIC12F529T48A 6.4 I/O Programming Considerations 6.4.1 BIDIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs ...

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... Timer0 Instruction Executed 2012 Microchip Technology Inc. PIC12F529T48A Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restric- tions on the external clock input are discussed in detail Section 7.1 “ ...

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... PIC12F529T48A FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1 (Program Counter) PC – Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch ...

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... Timer0 input ± External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the times at which sampling occurs. 2012 Microchip Technology Inc. PIC12F529T48A When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. ...

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... PIC12F529T48A 7.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module postscaler for the Watchdog Timer (WDT), respectively (see Section 8.6 Watch- dog Timer (WDT)). For simplicity, this counter is being referred to as prescaler throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both ...

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... BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER /4) CY OSC T0CKI Pin T0SE Watchdog Timer PSA WDT Enable bit Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2012 Microchip Technology Inc. PIC12F529T48A Sync Cycles T0CS PSA 8-bit Prescaler 8 8-to-1 MUX PS<2:0> 1 ...

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... PIC12F529T48A NOTES: DS41634A-page 38 Preliminary 2012 Microchip Technology Inc. ...

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... Sleep Code Protection ID Locations In-Circuit Serial Programming The PIC12F529T48A device has a Watchdog Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using selectable oscillator options, there is always (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable ...

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... XT oscillator with 18 ms DRT 10 INTRC with 1 ms DRT 11 EXTRC with 1 ms DRT Note 1: Refer to the PIC12F529T48A Memory Programming Specification, DS41619 to determine how to program/erase the Configuration Word. 2: DRT length ( ms function of clock mode selection the responsibility of the application designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in acceptable operation ...

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... Oscillator Configurations 8.2.1 OSCILLATOR TYPES The PIC12F529T48A device can be operated four different oscillator modes. The user can program using the Configuration bits (FOSC<1:0>), to select one of these modes: LP: Low-Power Crystal XT: Crystal/Resonator INTRC: Internal 4 MHz or 8 MHz Oscillator EXTRC: External Resistor/Capacitor 8 ...

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... C EXT account variation due to tolerance of external R and C components used. Figure 8-5 shows how the R/C combination is connected to the PIC12F529T48A device. For R values below 3.0 k, the oscillator operation may become unstable, or stop completely. For very high R values (e.g., 1 M), the oscillator becomes EXT sensitive to noise, humidity and leakage ...

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... If Reset was due to wake-up on pin change, then bit All other Resets will cause bit 2012 Microchip Technology Inc. PIC12F529T48A For the PIC12F529T48A device, only bits <7:1> of OSCCAL are used for calibration. See more information. Note: The bit 0 of the OSCCAL register is ...

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... MCLR SELECT GPPU GP3/MCLR/V MCLRE 8.4 Power-on Reset (POR) The PIC12F529T48A device incorporates an on-chip Power-on Reset (POR) circuitry, which provides an internal chip Reset for most power-up situations. The on-chip POR circuit holds the chip in Reset until V has reached a high enough level for proper DD operation ...

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... DRT Time-out Internal Reset FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V TIME V DD MCLR Internal POR DRT Time-out Internal Reset 2012 Microchip Technology Inc. PIC12F529T48A POR (Power-on Reset) MCLR Reset Start-up Timer (10 ms) TDRT Preliminary CHIP Reset ...

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... PIC12F529T48A FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V TIME V DD MCLR Internal POR DRT Time-out Internal Reset Note: When V rises slowly, the T DD value. In this example, the chip will reset properly if, and only if, V1 V DS41634A-page 46 V1 TDRT time-out expires long before V ...

Page 47

... Device Reset Timer (DRT) On the PIC12F529T48A device, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 8-5). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. ...

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... PIC12F529T48A FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure Watchdog Time WDT Enable Configuration Bit Note 1: PSA, PS<2:0> are bits in the OPTION register. TABLE 8-6: SUMMARY OF REGISTER ASSOCIATED WITH THE WATCHDOG TIMER Name Bit 7 Bit 6 OPTION GPWU GPPU Legend: Shaded boxes Not used by Watchdog Timer. ...

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... T0CKI input should GP3/MCLR/V pin must logic high level if PP MCLR is enabled. 2012 Microchip Technology Inc. PIC12F529T48A 8.8.2 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events external Reset input on GP3/MCLR/V when configured as MCLR. ...

Page 50

... This allows users to manufacture boards with unprogrammed PIC12F529T48A device and then program the PIC12F529T48A device just before shipping the product. This also allows the most recent firmware custom firmware programmed. ...

Page 51

... Preset Preset 434 MHz OOK Tx 868 MHz FSK Tx Advanced Mode User-defined Configuration 2012 Microchip Technology Inc. PIC12F529T48A 9.1.1 PRESET MODE In Preset mode, the transmitter is configured according to Table 9-1. One of the two configuration modes can be selected by changing the logical state of the CTRL pin at power-up. The timing of a typical transmit opera- tion in Preset mode is shown in edge on the DATA pin activates the transmitter ...

Page 52

... PIC12F529T48A 9.1.2 ADVANCED MODE Advanced mode allows full configuration of the trans- mitter by writing to the Configuration register. Writing and reading from this register is performed via a two-wire interface formed by the CTRL and DATA pins. Advanced mode is enabled by applying a rising signal on the CTRL pin while driving DATA low. Upon detec- tion of this rising edge, the data applied to the DATA pin is accepted as register configuration information ...

Page 53

... DATA CTRL t WAKE RF OUT T ENABLE X 2012 Microchip Technology Inc. PIC12F529T48A t START Valid Logic Level Sleep With TX mode (D12) set, the transmitter is placed directly in Transmit mode. It will remain in Transmit mode until a second register write operation clears the TX mode bit. Refer to Note 1: Once in Sleep mode, activity on the DATA ...

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... PIC12F529T48A TABLE 9-2: CONFIGURATION REGISTER Bit Name Value D12 Tx Mode 0 Forced Transmit 1 D(11:9) Frequency 000 001 010 011 100 101 110 111 D8 Modulation 0 1 D(7:5) Freq. Deviation 000 001 010 011 100 101 110 111 D4 RF Power Timer D(2:0) Fine Tuning PLL Step ...

Page 55

... INSTRUCTION SET SUMMARY The PIC12F529T48A instruction set is highly orthogo- nal and is comprised of three basic categories. Byte-oriented operations Bit-oriented operations Literal and control operations Each PIC12F529T48A instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction ...

Page 56

... PIC12F529T48A TABLE 10-2: INSTRUCTION SET SUMMARY Mnemonic, Description Operands ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 IORWF ...

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... The contents of the W register are ANDed with register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 2012 Microchip Technology Inc. PIC12F529T48A BCF Bit Clear f Syntax: [ label ] BCF 0 f 31 Operands: 0  ...

Page 58

... PIC12F529T48A BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b 0 f 31 Operands: 0 b < 7 Operation: skip if (f

Page 59

... Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a two- cycle instruction. 2012 Microchip Technology Inc. PIC12F529T48A INCF Increment f [ label ] Syntax: 0 f 31 Operands: d [0,1] ( (dest) ...

Page 60

... PIC12F529T48A IORWF Inclusive OR W with f [ label ] Syntax: IORWF f,d 0 f 31 Operands: d [0,1] (W).OR. (f) (dest) Operation: Status Affected: Z Description: Inclusive OR the W register with register f. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register ‘ ...

Page 61

... Carry flag. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. register f C 2012 Microchip Technology Inc. PIC12F529T48A SLEEP Syntax: Operands: Operation: Status Affected: TO, PD, GPWUF Description: ...

Page 62

... PIC12F529T48A TRIS Load TRIS Register Syntax: [ label ] TRIS f Operands (W) TRIS register f Operation: Status Affected: None Description: TRIS register f’ loaded with the contents of the W register. XORLW Exclusive OR literal with W Syntax: [label ] XORLW k 0 k 255 Operands: (W) .XOR. k  ...

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... PICkit 3 Debug Express Device Programmers - PICkit 2 Programmer - MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 2012 Microchip Technology Inc. PIC12F529T48A 11.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

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... PIC12F529T48A 11.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchips PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...

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... Microchip Technology Inc. PIC12F529T48A 11.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...

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... PIC12F529T48A 11.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchips Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), ...

Page 67

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2012 Microchip Technology Inc. PIC12F529T48A ...0 to 3.9V ... -0. ) ...

Page 68

... PIC12F529T48A PIC12F529T48A VOLTAGE-FREQUENCY GRAPH, -40C T FIGURE 12-1: 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 2.0 0 FIGURE 12-2: MAXIMUM OSCILLATOR FREQUENCY TABLE LP XT EXTRC INTOSC 0 DS41634A-page 68 INTOSC ONLY Frequency (MHz) 200 kHz 4 MHz Frequency (MHz) Preliminary 85 MHz 2012 Microchip Technology Inc. ...

Page 69

... DC Characteristics TABLE 12-1: DC CHARACTERISTICS: PIC12F529T48A (INDUSTRIAL) DC CHARACTERISTICS Param Sym. Characteristic No. Supply Voltage D001 V DD D002 V RAM Data Retention Voltage DR D003 V V Start Voltage to ensure POR DD Power-on Reset D004 S V Rise Rate to ensure VDD DD Power-on Reset Supply Current During Prog/ D005 I DDP Erase. ...

Page 70

... PIC12F529T48A 12.2 RF Transmitter Electrical Specifications Symbol Description Current Consumption IDDSL Supply current in Sleep mode IDDT Supply current in Transmit mode with appropriate exter- nal matching RF and Baseband Specifications FDA_D Frequency deviation, FSK FDA Frequency deviation, FSK BRF Bit rate, FSK BRO Bit rate, OOK ...

Page 71

... Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended that the PIC12F529T48A be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions ...

Page 72

... PIC12F529T48A TABLE 12-3: PULL-UP RESISTOR RANGES Temperature V (Volts) DD (C) GP0/GP1 2.0 GP3 2.0 DS41634A-page 72 Min. Typ. 73K 105K 73K 113K 82K 123K 63K 81K 77K 93K 82K 96K Preliminary Max. Units 186K 187K 190K 96K ...

Page 73

... Timing Parameter Symbology and Load Conditions PIC12F529T48A The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings CLKOUT cy Cycle time drt Device Reset Timer io I/O port Uppercase letters and their meanings: ...

Page 74

... PIC12F529T48A 12.4 AC Characteristics TABLE 12-4: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym. Characteristic No External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period OSC (2) Oscillator Period 2 T Instruction Cycle Time CY 3 TosL, Clock in (OSC1) Low or High TosH Time 4 TosR, Clock in (OSC1) Rise or Fall ...

Page 75

... Data in the Typical (Typ) column is at 3.7V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 12-3 for loading conditions. 2012 Microchip Technology Inc. PIC12F529T48A 20, 21 -40C T 85C (industrial) ...

Page 76

... Timer Reset (1) I/O pin Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT Reset only in XT and LP. TABLE 12-7: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER PIC12F529T48A AC CHARACTERISTICS Param Sym. Characteristic No MCLR Pulse Width (low) ...

Page 77

... These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 3.7V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2012 Microchip Technology Inc. PIC12F529T48A Standard Operating Conditions (unless otherwise specified) Operating Temperature -40 ...

Page 78

... PIC12F529T48A NOTES: DS41634A-page 78 Preliminary 2012 Microchip Technology Inc. ...

Page 79

... Microchip Technology Inc. vs. F OVER V (XT, EXTRC mode) OSC (MHz) OSC vs. F OVER V (XT, EXTRC mode) OSC (MHz) OSC Preliminary PIC12F529T48A DS41634A-page 79 DD ...

Page 80

... PIC12F529T48A FIGURE 13-3: I vs. V OVER 120 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp (-40°C to 85°C) 100 DS41634A-page 80 (LP MODE) OSC 32 kHz Maximum Industrial 32 kHz Typical (V) DD Preliminary 6 5 2012 Microchip Technology Inc. ...

Page 81

... FIGURE 13-5: MAXIMUM I PD 18.0 Typical: Statistical Mean @25°C 16.0 Maximum: Mean (Worst-Case Temp) 3 (-40°C to 85°C) 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 2012 Microchip Technology Inc. PIC12F529T48A vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD 3.0 3.5 4.0 V (V) DD vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Max. 85°C 3.0 3.5 4.0 V (V) DD Preliminary 4.5 5.0 5.5 4.5 5.0 5.5 DS41634A-page 81 ...

Page 82

... PIC12F529T48A FIGURE 13-6: TYPICAL WDT Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) 3 7 (-40°C to 85° 2.0 2.5 FIGURE 13-7: MAXIMUM WDT I 25.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) 3 (-40°C to 85°C) 20.0 15.0 10.0 5.0 0.0 2.0 2.5 DS41634A-page 82 vs 3.0 3.5 4 ...

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... Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) 3 (-40°C to 85°C) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5.0 5.5 6.0 2012 Microchip Technology Inc. PIC12F529T48A OVER TEMPERATURE (NO PRESCALER) DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) 3 (-40°C to 85°C) 3.0 3.5 4 3.0V) DD Max. 85°C Typical 25°C Min. -40°C 6 ...

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... PIC12F529T48A FIGURE 13-10: V vs. I OVER TEMPERATURE ( 3.5 3.0 2.5 2.0 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) 3 1.0 (-40°C to 85°C) 0.5 0.0 0.0 -0.5 -1.0 FIGURE 13-11: TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) 3 (-40°C to 85°C) 1.3 1.1 0.9 0.7 0.5 2.0 2.5 DS41634A-page 84 3.0V) DD -1.5 -2.0 -2.5 I (mA Max. -40°C Typ. 25° ...

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... Maximum: Mean (Worst-Case Temp) 3 (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 2.0 2.5 FIGURE 13-13: DEVICE RESET TIMER (XT AND LP) vs 2.0 2.5 2012 Microchip Technology Inc. PIC12F529T48A vs Max. 125° Min. -40° Max. -40°C IL 3.0 3.5 4 Max. 85°C Typical 25°C Min. -40°C 3.0 3.5 4.0 ...

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... PIC12F529T48A NOTES: DS41634A-page 86 Preliminary 2012 Microchip Technology Inc. ...

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... Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2012 Microchip Technology Inc. PIC12F529T48A Example 529T48A Preliminary ...

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... PIC12F529T48A 14.2 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41634A-page 88 Preliminary 2012 Microchip Technology Inc. ...

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... For the most current package drawings, please see the Microchip Packaging Specification located at Note: http://www.microchip.com/packaging 2012 Microchip Technology Inc. PIC12F529T48A Preliminary DS41634A-page 89 ...

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... PIC12F529T48A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41634A-page 90 Preliminary 2012 Microchip Technology Inc. ...

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... APPENDIX A: DATA SHEET REVISION HISTORY Revision A (04/2012) Initial release of this data sheet. 2012 Microchip Technology Inc. PIC12F529T48A Preliminary DS41634A-page 91 ...

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... PIC12F529T48A NOTES: DS41634A-page 92 Preliminary 2012 Microchip Technology Inc. ...

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... MPLINK Object Linker/MPLIB Object Librarian ... 64 O OPTION Register... 19 OSC selection... 39 OSCCAL Register... 20 Oscillator Configurations... 41 Oscillator Types HS... 41 LP ... 41 RC ... 41 XT ... 41 P Packaging PDIP Details ... 88 PIC12F529T48A Device Varieties ... 9 POR Device Reset Timer (DRT) ... 39, 47 PD... 49 TO... 49 Power-down Mode... 49 Prescaler ... 36 Program Counter ... cycles ... Oscillator... 42 Reader Response... 96 Read-Modify-Write... 32 Registers CONFIG1 (Configuration Word Register 1) ...

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... PIC12F529T48A W Wake-up from Sleep ... 49 Watchdog Timer (WDT) ... 39, 47 Period... 47 Programming Considerations ... 47 WWW Address... 95 WWW, On-Line Support... 5 Z Zero bit ... 11 DS41634A-page 94 Preliminary 2012 Microchip Technology Inc. ...

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... To register, access the Microchip web site at www.microchip.com. Under Support, Customer Change Notification and follow the registration instructions. 2012 Microchip Technology Inc. PIC12F529T48A CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: Distributor or Representative Local Sales Office the following • ...

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... Telephone: (___) ___ - ___ Application (optional): Would you like a reply? Y Device: PIC12F529T48A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...

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... Range: Package 14-pin TSSOP Pattern: Special Requirements Note: Tape and Reel available for only the following packages: TSSOP. 2012 Microchip Technology Inc. PIC12F529T48A X /XX XXX Examples: Package Pattern a) Range (1) Preliminary . PIC12F529T48A-I/P Industrial temp., TSSOP package (Pb-free) DS41634A-page 97 ...

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... Tel: 886-7-536-4818 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary 2012 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...

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