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MAX9263 Datasheet

Download or read online Maxim Integrated MAX9263 GMSL Serializer with HDCP pdf datasheet.



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19-5644; Rev 1; 3/11
General Description
The MAX9263/MAX9264 chipset extends Maxim’s gigabit
multimedia serial link (GMSL) technology to include high-
bandwidth digital content protection (HDCP) encryption
for content protection of DVD and Blu-ray™ video and
audio data. The MAX9263 serializer, or any HDCP-GMSL
serializer, pairs with the MAX9264 deserializer, or any
HDCP-GMSL deserializer, to form a digital serial link for
the transmission of control data and HDCP encrypted
video and audio data. GMSL is an HDCP technology
approved protocol by Digital Content Protection (DCP),
LLC.
The parallel interface is programmable for 24-bit or
32-bit width and operates with a pixel clock of 8.33MHz
to 104MHz (24 bit) or 6.25MHz to 78MHz (32 bit). When
programmed for 24-bit or 32-bit width, three inputs are
2
for I
S audio, supporting a sampling frequency from
8kHz to 192kHz and a sample depth of 4 bits to 32
bits. The embedded control channel forms a full-duplex
differential 9.6kbps to 1Mbps UART link between the
serializer and deserializer. An electronic control unit
(ECU), or microcontroller (FC), can be located on the
serializer side of the link (typical for video display), on the
deserializer side of the link (typical for image sensing), or
on both sides (typical for HDCP video display repeaters).
The control channel enables ECU/FC control of peripher-
als on the remote side, such as backlight control, touch
screen, and perform HDCP-related operations.
The serial link signaling is AC-coupled CML with 8b/10b
coding. For driving longer cables, the serializer has pro-
grammable pre/deemphasis, and the deserializer has a
programmable channel equalizer. The GMSL devices
have programmable spread spectrum on the serial
(serializer) and parallel (deserializer) output. The serial
link input and output meet ISO 10605 and IEC 61000-
4-2 ESD standards. The serializer core supply is 1.8V
and the deserializer core supply is 3.3V. The I/O supply
is 1.8V to 3.3V. Both devices are available in a 64-pin
TQFP package with an exposed pad and are specified
over the -40NC to +105NC automotive temperature range.
High-Resolution Automotive Navigation
Rear-Seat Infotainment
Megapixel Camera Systems
Blu-ray is a trademark of Blu-ray Disc Association.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
HDCP Encryption Enable/Disable Programmable
S
Through Control Channel
Control Channel Handles All HDCP Protocol
S
Transactions—Separate Control Bus Not Required
HDCP Keys Preprogrammed in Secure Nonvolatile
S
Memory
2.5Gbps Payload Data Rate (3.125Gbps with
S
Overhead)
AC-Coupled Serial Link with 8b/10b Line Coding
S
8.33MHz to 104MHz (24-Bit Mode) or 6.25MHz to
S
78MHz (32-Bit Mode) Pixel Clock
4-Bit to 32-Bit Word Length, 8kHz to 192kHz I
S
Audio Channel Supports High-Definition Audio
Embedded Half-/Full-Duplex Bidirectional Control
S
Channel
Base Mode: 9.6kbps to 1Mbps
Bypass Mode: 9.6kbps to 1Mbps
Interrupt Supports Touch-Screen Displays
S
Remote-End I
S
Programmable Pre/Deemphasis and Channel
S
Equalizer for 15m Cable Drive at 3.125Gbps
Programmable Spread Spectrum on Serial or
S
Parallel Output Reduces EMI
Deserializer Serial-Data Clock Recovery
S
Eliminates External Reference Clock
Auto Data-Rate Detection Allows On-The-Fly
S
Data-Rate Change
Bypassable PLL on Serializer Pixel Clock Input for
S
Jitter Attenuation
Built-In PRBS Generator/Checker for BER Testing
S
of the Serial Link
Fault Detection of Serial Link Shorted Together, to
S
Ground, to Battery, or Open
ISO 10605 and IEC 61000-4-2 ESD Tolerance
S
Applications
PART
MAX9263GCB/V+
MAX9263GCB/V+T
MAX9264GCB/V+
MAX9264GCB/V+T
/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Features
2
2
C Master for Peripherals
Ordering Information
TEMP RANGE
PIN-PACKAGE
-40NC to +105NC
64 TQFP-EP*
-40NC to +105NC
64 TQFP-EP*
-40NC to +105NC
64 TQFP-EP*
-40NC to +105NC
64 TQFP-EP*
S
1

Summary of Contents

Page 1

... DVD and Blu-ray video and audio data. The MAX9263 serializer, or any HDCP-GMSL serializer, pairs with the MAX9264 deserializer, or any HDCP-GMSL deserializer, to form a digital serial link for the transmission of control data and HDCP encrypted video and audio data ...

Page 2

... High-Level Input Voltage Low-Level Input Voltage 2 LMN_ to AGND (MAX9263) (15mA current limit) ...-0.5V to 3.9V All Other Pins to GND (MAX9263) ... -0. All Other Pins to IOGND (MAX9264) ... -0. Continuous Power Dissipation (T 64-Pin TQFP (derate 31.3mW/NC above 70NC) ...2507.8mW Operating Temperature Range ... -40NC to 105NC Junction Temperature ...150NC Storage Temperature Range ...

Page 3

... MAX9263 DC ELECTRICAL CHARACTERISTICS (continued 1.7V to 1.9V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL Input Current Low-Level Output Voltage DIFFERENTIAL OUTPUT (OUT, OUT-) Differential Output Voltage Change in V Between OD Complementary Output States Output Offset Voltage (V OUT ...

Page 4

... HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 DC ELECTRICAL CHARACTERISTICS (continued 1.7V to 1.9V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL ESD PROTECTION OUT, OUT- All Other Pins MAX9263 AC ELECTRICAL CHARACTERISTICS ( 1.7V to 1.9V, V DVDD AVDD IOVDD Typical values are at V ...

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... MAX9263 AC ELECTRICAL CHARACTERISTICS ( 1.7V to 1.9V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL Deterministic Serial Output Jitter t Parallel Data Input Setup Time Parallel Data Input Hold Time t Serializer Delay (Notes 6, 7) (Figure 1) Link Start Time t Power-Up Time ...

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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL OUTPUT Short-Circuit Current C/UART, I/O, AND OPEN-DRAIN ...

Page 7

MAX9264 DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL POWER SUPPLY Worst-Case Supply Current (Figure 15, Note 3) Sleep Mode ...

Page 8

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 AC ELECTRICAL CHARACTERISTICS ( 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL PARALLEL CLOCK OUTPUT (PCLKOUT) Clock Frequency f PCLKOUT ...

Page 9

MAX9264 AC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL Lock Time Power-Up Time OUTPUT TIMING (NOTE 6) ...

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... HDCP Gigabit Multimedia Serial Link Serializer/Deserializer ( 1.8V (MAX9263), V AVDD DVDD IOVDD MAX9263 SUPPLY CURRENT vs. PCLK FREQUENCY (24-BIT MODE) 160 PRBS ON, HDCP ON 150 PREEMPHASIS 0x0B TO 0x0F 140 130 120 PREEMPHASIS 0x01 TO 0x04 110 PREEMPHASIS 0x00 100 PCLK FREQUENCY (MHz) MAX9264 SUPPLY CURRENT vs ...

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... FREQUENCY (VARIOUS MAX9263 SPREAD) 0 -10 0% SPREAD -20 -30 -40 -50 -60 -70 -80 2% SPREAD 4% SPREAD - PCLK FREQUENCY (MHz) OUTPUT POWER SPECTRUM vs. PCLK FREQUENCY (VARIOUS MAX9263 SPREAD) 0 -10 0% SPREAD -20 -30 -40 -50 -60 -70 -80 2% SPREAD 4% SPREAD - PCLK FREQUENCY (MHz) MAXIMUM PCLK FREQUENCY vs. STP CABLE LENGTH (BER < ...

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... DIN4 55 DIN5 56 DIN6 57 DIN7 58 DIN8 59 DIN9 60 GND 61 DVDD 62 DIN10 63 DIN11 MAX9263 TQFP CONNECT EXPOSED PAD TO AGND Pin Configurations GND 30 IOVDD 29 AUTOS SCK SD 26 DIN28 ...

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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer TOP VIEW DOUT8 49 IOGND 50 IOVDD 51 DOUT7 52 DOUT6 53 DOUT5 54 DOUT4 55 DOUT3 56 MAX9264 DOUT2 57 DOUT1 58 DOUT0 59 ...

Page 14

... Control Direction Selection. Control link direct selection input requires external pulldown or 33 CDS pullup resistor. Set CDS low for UART connection control master. Set CDS high for peripheral connection as a control-channel I 14 MAX9263 Pin Description FUNCTION use additional UART slave. ...

Page 15

... Exposed Pad internally connected to AGND. MUST externally connect EP to the AGND EP plane for proper thermal and electrical performance. Link Serializer/Deserializer MAX9263 Pin Description (continued) FUNCTION 2 C serial-data input/output with internal 30kI pullup master. RX/SDA has an open-drain ...

Page 16

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PIN NAME Active-Low Parallel Output-Enable Input. Requires an external pulldown or pullup resistor. Set ENABLE low to enable PCLKOUT, SD, SCK, WS, and DOUT_. Set ENABLE high to put ENABLE 1 PCLKOUT, ...

Page 17

PIN NAME 19 PWDN Active-Low, Power-Down Input. PWDN requires an external pulldown or pullup resistor. Active-Low Open-Drain Video Data Error Output with Internal 60kI Pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceed ...

Page 18

... SSPLL PLL CLKDIV RGB HDCP ENCRYPT SCRAMBLE/ HDCP HDCP PARITY/ KEYS CONTROL 8b/10b ENCODE DIN[28:27] (4-CH) ACB HDCP ENCRYPT FCC WS Functional Diagrams LEFT LMN0 LINE FAULT LMN1 DETECT OUT PARALLEL TO SERIAL OUT- CML Tx Rx REVERSE CONTROL CHANNEL MAX9263 2 UART/I C TX/SCL RX/SDA ...

Page 19

HDCP Gigabit Multimedia Serial PCLKOUT SSPLL RGB[17:0] RGB DOUT[17:0] HS DOUT18/ DOUT19/VS VIDEO DOUT20 DE DE RGB[23:18] DOUT[26:21] (4-CH) (4-CH) DOUT27 FIFO (4-CH) DIN[28:27] (4-CH) DOUT28/MCLK (4-CH) ACB AUDIO FCC SD SCK WS Link Serializer/Deserializer Functional Diagrams ...

Page 20

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer OUT- V OS(-) OUT V OD(-) (OUT) - (OUT-) Figure 1. Serializer Serial-Output Parameters OUT OUT- Figure 2. Serializer Output Waveforms at OUT, OUT OUT OUT- ...

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... OUTPUT LOGIC (OUT) LFLT OUTPUT LOGIC (OUT-) Figure 3. Line-Fault Detector Circuit NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE. Figure 4. Serializer Worst-Case Pattern Input HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 45kI LMN0 LMN1 5kI OUT OUT- REFERENCE VOLTAGE GENERATOR Q1% TOLERANCE PCLKIN DIN_ 1 ...

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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PCLKIN t F Figure 5. Serializer Parallel Input Clock Requirements t R TX/ SCL RX/ SDA Figure Timing Parameters 800mV P-P Figure 7. Serializer Differential Output Template 22 ...

Page 23

PCLKIN DIN_ Figure 8. Serializer Input Setup and Hold Times DIN_ N N1 PCLKIN OUT/- Figure 9. Serializer Delay HDCP Gigabit Multimedia Serial Link Serializer/Deserializer V IH MIN V IL MAX t SET V IH MIN V IL MAX NOTE: ...

Page 24

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PCLKIN REVERSE CONTROL CHANNEL Figure 10. Serializer Link Startup Time PCLKIN PWDN POWERED DOWN REVERSE CONTROL CHANNEL DISABLED Figure 11. Serializer Power-Up Delay 24 t LOCK 350Fs SERIAL LINK INACTIVE SERIAL LINK ACTIVE CHANNEL ...

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WS SCK SD 2 Figure 12. Input I S Timing Parameters IN V CMR IN- V ROH 0 ROH 0 ROH (IN) - (IN Figure 13. Reverse Control-Channel Output Parameters HDCP Gigabit Multimedia Serial ...

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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer IN IN- _ Figure 14. Test Circuit for Differential Input Measurement PCLKOUT Figure 16. Deserializer Clock Output High and Low Times ...

Page 27

SERIAL-WORD LENGTH SERIAL WORD N IN/- FIRST BIT LAST BIT DOUT_ PARALLEL WORD N-2 PCLKOUT NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE. Figure 18. Deserializer Delay IN - IN- t LOCK LOCK PWDN MUST BE HIGH Figure 19. Deserializer Lock ...

Page 28

... HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Detailed Description The MAX9263/MAX9264 serializer/deserializer chipset utilizes Maxims GMSL technology and HDCP. When HDCP is enabled, the serializer/deserializer encrypt video and audio data on the serial link. The serializer/ deserializer are backward compatible with the MAX9259/ MAX9260 serializer/deserializer ...

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Table 1. Power-Up Default Register Map (see Tables 22 and 24) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x05 0x70 0x06 0x40 0x07 0x22 0x0A 0x08 (read only) 0x0C 0x70 0x0D 0x0F 0x05 0x1E (read only) 0x1X 0x1F (read only) ...

Page 30

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 1. Power-Up Default Register Map (see Tables 22 and 24) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x98 to 0x9C 0x0000000000 0x9D to 0x9F 0x000000 0xA0 to 0xA3 0x00000000 0xA4 to 0xA7 0x00000000 ...

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Table 2. Power-Up Default Register Map (see Tables 23 and 25) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x05 0x24 or 0x29 0x06 0x0F 0x07 0x54 0x08 0x30 0x09 0xC8 0x0A 0x12 0x0B 0x20 0x0C 0x00 0x00 0x0D (read only) ...

Page 32

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 2. Power-Up Default Register Map (see Tables 23 and 25) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0xXX 0x87 (read only) 0x00000000 0x88 to 0x8F 00000000 0x00000000 0x90 to 0x94 00000000 0x95 0x00 ...

Page 33

HDCP Bitmapping and Bus-Width Selection The parallel input/outputs have two selectable modes, 24-bit mode and 32-bit mode. In 24-bit mode, DIN[28:21] are not available. For both modes, the SD, SCK, and WS 2 pins are for I S audio. The ...

Page 34

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer DIN0 DIN1 DIN17 RGB DATA NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE ACCORDINGLY ON BOTH SIDES OF THE LINK. ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION. Figure 23. 32-Bit ...

Page 35

PCLKIN frequencies. Spread-spectrum settings do not affect 2 the I S data rate or WS clock frequency. Additional MCLK Output for Audio Applications Some audio DACs, such as the MAX9850, do not require ...

Page 36

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer 1Mbps in both directions. The serializer and deserial- izer automatically detect the control-channel bit rate in base mode. Packet bit rates can vary up to 3.5x from the previous bit rate. See the Changing ...

Page 37

UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD 0) SERIALIZER/DESERIALIZER SYNC FRAME DEVICE REGISTER ADDRESS SERIALIZER/DESERIALIZER PERIPHERAL UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD 0) SERIALIZER/DESERIALIZER ...

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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer 2 UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD 1) SERIALIZER/DESERIALIZER SYNC FRAME DEVICE REGISTER ADDRESS SERIALIZER/DESERIALIZER PERIPHERAL UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD ...

Page 39

Table 6. Serializer CML Driver Strength (Default Level, CMLLVL 11) PREEMPHASIS SETTING PREEMPHASIS LEVEL (dB) -6.0 -4.1 -2.5 -1.2 0 1.1 2.2 3.3 4.4 6.0 8.0 10.5 14.0 Negative preemphasis levels denote deemphasis. Table 7. Deserializer Cable Equalizer Boost ...

Page 40

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Spread Spectrum To reduce the EMI generated by the transitions on the serial link and parallel outputs, both the serial- izer and deserializer support spread spectrum. Turning on spread spectrum on the deserializer spreads ...

Page 41

Manual Programming of the Spread-Spectrum Divider The modulation rate for the serializer/deserializer relates to the PCLK_ frequency as follows: f PCLK_ f (1 DRS) M × MOD SDIV where Modulation frequency M DRS DRS pin ...

Page 42

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer outputs of the device remain high impedance. Entering power-down mode resets the internal registers of the device. In addition, upon exiting power-down mode, the serializer/deserializer relatch the state of external pins SSEN, DRS, AUTOS, ...

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Case 3: Remote Side Autostart Mode After power-up or when PWDN transitions from low to high, the remote device (deserializer) starts up and tries to lock to an incoming serial signal with sufficient power. The host side (serializer ...

Page 44

... SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER FC SETS SLEEP 1 INT CHANGES FROM LOW TO HIGH OR SEND INT TO HIGH TO LOW ALL STATES MAX9263 Figure 31. Deserializer State Diagram, CDS Low (LCD Application) Table 14. Start Mode Selection for Image-Sensing Application (CDS High) AUTOS SERIALIZER CASE POWER-UP STATE ...

Page 45

POWER-UP VALUE AUTOS PIN SETTING SEREN SLEEP LOW 1 HIGH 0 SLEEP 1 FOR > 8ms SLEEP REVERSE LINK WAKE-UP SIGNAL PWDN HIGH, POWER-ON, SLEEP 1 AUTOS HIGH POWER-DOWN PWDN LOW OR ALL STATES OR ...

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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer then reads the deserializer KSV (BKSV) and writes it to the serializer. The FC begins checking BKSV against the revocation list. Using the cipher, the serializer and dese- rializer calculate a 16-bit response value, ...

Page 47

Force Video/Force Audio Data The serializer masks audio and video data through two control bits: FORCE_AUDIO and FORCE_VIDEO. Set FORCE_VIDEO 1 to transmit the 24-bit data word in the DFORCE register instead of the video data received at the ...

Page 48

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is not a Repeater)First Part of the HDCP Authentication Protocol (continued) NO. µC Reads the BKSV and REPEATER bit from the deserializer 8 and writes ...

Page 49

Table 16. Link Integrity Check (Normal)Performed Every 128 Frames After Encryption is Enabled (continued) NO. µ does not match RI, link integrity check fails. After the detection of failure of link integrity check, the FC ensures that A/V ...

Page 50

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Example Repeater NetworkTwo µCs The following example has one repeater and two FCs (Figure 34). Table 18 summarizes the authentication operation. BD-DRIVE TX_B1 µC_B MEMORY WITH SRM Figure 34. Example Network with One Repeater ...

Page 51

Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B Makes sure that the A/V data not requiring protection (low-value content) is available at the TX_B1 inputs (such ...

Page 52

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B Waits for the VSYNC falling edge and then enables encryption on the ...

Page 53

Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B Reads the KSV list and BINFO from RX_R1 and writes them to TX_B1. If any of the MAX_DEVS_EXCEEDED ...

Page 54

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Applications Information The deserializer checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register DECERR (0x0D large number of 8b/10b decoding or parity errors ...

Page 55

Jitter-Filtering PLL In some applications, the parallel bus input clock to the serializer (PCLKIN) includes noise, which reduces link reliability. The serializer has a narrowband jitter-filtering PLL to attenuate frequency components outside the PLLs bandwidth (< 100kHz typ). Enable the ...

Page 56

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer required external resistor connections. LFLT low when a line fault is detected and LFLT goes high when the line returns to normal. The line-fault type is stored in 0x08, D[3:0] of the serializer. ...

Page 57

AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor. Four capacitorstwo at the serializer output and two at the deserializer input are needed for proper link operation and to provide protection if either end ...

Page 58

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer R D 330I CHARGE-CURRENT- DISCHARGE LIMIT RESISTOR RESISTANCE HIGH- C STORAGE S VOLTAGE 150pF CAPACITOR DC SOURCE Figure 36. IEC 61000-4-2 Contact Discharge ESD Test Circuit Table 22. Serializer GMSL Core Register Table (See ...

Page 59

Table 22. Serializer GMSL Core Register Table (See Table 1) (continued) REGISTER BITS NAME ADDRESS D[7:6] AUTOFM 0x03 D[5:0] SDIV D7 SEREN D6 CLINKEN D5 PRBSEN 0x04 D4 SLEEP D[3:2] INTTYPE D1 REVCCEN D0 FWDCCEN HDCP Gigabit Multimedia Serial Link ...

Page 60

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 22. Serializer GMSL Core Register Table (See Table 1) (continued) REGISTER BITS NAME ADDRESS D7 I2CMETHOD D6 DISFPLL D[5:4] CMLLVL 0x05 D[3:0] PREEMP 0x06 D[7:0] 0x07 D[7:0] D[7:4] D[3:2] LFNEG ...

Page 61

... Set INT high when SETINT transitions from Serializer does not invert DIN19/VS. 1 Serializer inverts DIN19/VS. 0 Serializer does not invert DIN18/HS. 1 Serializer inverts DIN18/HS. 00000 Reserved. 00000101 Device identifier (MAX9263 0x05). 000 Reserved. 0 Not HDCP capable. 1 HDCP capable. XXXX Device revision. VALUE FUNCTION XXXXXXX Serializer device address ...

Page 62

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued) REGISTER BITS NAME ADDRESS D[7:6] AUTOFM 0x03 D5 D[4:0] SDIV D7 LOCKED D6 OUTENB D5 PRBSEN D4 SLEEP 0x04 D[3:2] INTTYPE D1 ...

Page 63

Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued) REGISTER BITS NAME ADDRESS D7 I2CMETHOD D[6:5] HPFTUNE D4 PDHF 0x05 D[3:0] EQTUNE D7 DISSTAG D7 D6 AUTORST D5 DISINT 0x06 D4 INT D3 GPIO1OUT D2 GPIO1 D1 ...

Page 64

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued) REGISTER BITS NAME ADDRESS 0x07 D[7:0] D[7:2] D1 DISVSFILT 0x08 D0 DISHSFILT 0x09 D[7:0] 0x0A D[7:0] 0x0B D[7:0] ...

Page 65

Table 24. Serializer HDCP Register Table (See Table 1) REGISTER SIZE NAME ADDRESS (Bytes) 0x80 to 0x84 5 BKSV 0x85 to 0x86 2 RI/RI 0x87 1 PJ/PJ 0x88 to 0x8F 8 AN 0x90 to 0x94 5 AKSV 0x95 1 ACTRL ...

Page 66

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 24. Serializer HDCP Register Table (See Table 1) (continued) REGISTER SIZE NAME ADDRESS (Bytes) 0x96 1 ASTATUS 0x97 1 BCAPS 0x98 to 0x9C 5 ASEED 0x9D to 0x9F 3 DFORCE V.H0, 0xA0 to ...

Page 67

Table 24. Serializer HDCP Register Table (See Table 1) (continued) REGISTER SIZE NAME ADDRESS (Bytes) V.H4, 0xB0 to 0xB3 4 V.H4 0xB4 to 0xB5 2 BINFO 0xB6 1 GPMEM 0xB7 to 0xB9 3 0xBA to 0xFF 70 KSV_LIST HDCP ...

Page 68

HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 25. Deserializer HDCP Register Table (See Table 2) REGISTER SIZE NAME ADDRESS (Bytes) 0x80 to 0x84 5 BKSV 0x85 to 0x86 2 RI 0x87 1 PJ 0x88 to 0x8F 8 AN 0x90 to ...

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Table 25. Deserializer HDCP Register Table (See Table 2) (continued) REGISTER SIZE NAME ADDRESS (Bytes) 0xB4 to 0xB5 2 BINFO 0xB6 1 GPMEM 0xB7 to 0xB9 3 0xBA to 0xFF 70 KSV_LIST HDCP Gigabit Multimedia Serial Link Serializer/Deserializer READ/ ...

Page 70

... HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PCLKIN PCLK DIN[17:0] RGB DIN18/HS HS DIN19/VS VS DIN20 DE GPU CDS AUTOS ECU MAX9263 TX RX/SDA UART RX TX/SCL LFLT LFLT INT INT SCK SCK AUDIO SD SD NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS. ...

Page 71

... Updated the MAX9263 SCK and WS pin descriptions Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...

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