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DS34T102 Datasheet - Page 7

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Figure 14-19. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=1) ............... 337
Figure 14-20. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=1, Rx_sample=0) ............... 337
Figure 14-21. MII Management Interface Timing ................................................................................................... 338
Figure 14-22. MII Interface Output Signal Timing................................................................................................... 338
Figure 14-23. MII Interface Input Signal Timing ..................................................................................................... 339
Figure 14-24. RMII Interface Output Signal Timing ................................................................................................ 339
Figure 14-25. RMII Interface Input Signal Timing................................................................................................... 339
Figure 14-26. SSMII Interface Output Signal Timing.............................................................................................. 340
Figure 14-27. SSMII Interface Input Signal Timing................................................................................................. 340
Figure 14-28. JTAG Interface Timing Diagram....................................................................................................... 341
Figure 15-1. Connecting Port 1 to a Serial Transceiver ......................................................................................... 342
Figure 15-2. Connecting the Ethernet Port to a PHY in MII Mode ......................................................................... 343
Figure 15-3. Connecting the Ethernet Port to a MAC in MII Mode......................................................................... 343
Figure 15-4. Connecting the Ethernet Port to a PHY in RMII Mode....................................................................... 343
Figure 15-5. Connecting the Ethernet Port to a MAC in RMII Mode ...................................................................... 344
Figure 15-6. Connecting the Ethernet Port to a PHY in SSMII Mode..................................................................... 344
Figure 15-7. Connecting the Ethernet Port to a MAC in SSMII Mode .................................................................... 344
Figure 15-8. External Clock Multiplier for High Speed Applications ....................................................................... 345
Figure 15-9. 32-Bit CPU Bus Connections ............................................................................................................. 346
Figure 15-10. 16-Bit CPU Bus Connections ........................................................................................................... 347
Figure 15-11. Connecting the H_READY_N Signal to the MPC860 TA Pin ......................................................... 348
Figure 15-12. Internal CPLD Logic to Synchronize H_READY_N to the MPC860 Clock ...................................... 348
Figure 16-1. DS34T101 Pin Assignment (TE-CSBGA Package) ........................................................................... 361
Figure 16-2. DS34T102 Pin Assignment (TE-CSBGA Package) ........................................................................... 362
Figure 16-3. DS34T104 Pin Assignment (TE-CSBGA Package) ........................................................................... 363
Figure 16-4. DS34T108 Pin Assignment (HSBGA Package)................................................................................. 364
List of Tables
Table 3-1. Applicable Standards............................................................................................................................... 13
Table 9-1. Short Pin Descriptions ............................................................................................................................. 28
Table 9-2. Internal E1/T1 LIU Line Interface Pins .................................................................................................... 30
Table 9-3. External E1/T1 LIU Line Interface Pins ................................................................................................... 31
Table 9-4. Framer TDM Interface Pins ..................................................................................................................... 32
Table 9-5. TDM-over-Packet Engine TDM Interface Pins ........................................................................................ 34
Table 9-6. SDRAM Interface Pins............................................................................................................................. 36
Table 9-7. Ethernet PHY Interface Pins (MII/RMII/SSMII)........................................................................................ 37
Table 9-8. Global Clock Pins .................................................................................................................................... 39
Table 9-9. CPU Interface Pins .................................................................................................................................. 40
Table 9-10. JTAG Interface Pins .............................................................................................................................. 42
Table 9-11. Reset and Factory Test Pins ................................................................................................................. 42
Table 9-12. Power and Ground Pins ........................................................................................................................ 43
Table 10-1. CPU Data Bus Widths ........................................................................................................................... 45
Table 10-2. SPI Write Command Sequence ............................................................................................................ 50
Table 10-3. SPI_ Read Command Sequence .......................................................................................................... 51
Table 10-4. SPI Status Command Sequence........................................................................................................... 52
Table 10-5. Reset Functions..................................................................................................................................... 53
Table 10-6. Ethernet Frame Fields ........................................................................................................................... 55
Table 10-7. IPv4 Header Fields (UDP) ..................................................................................................................... 57
Table 10-8. UDP Header Fields................................................................................................................................ 57
Table 10-9. IPv6 Header Fields (UDP) ..................................................................................................................... 58
Table 10-10. MPLS Header Fields ........................................................................................................................... 58
Table 10-11. MEF Header Fields.............................................................................................................................. 58
Table 10-12. IPv4 Header Fields (L2TPv3) .............................................................................................................. 59
Table 10-13. L2TPv3 Header Fields......................................................................................................................... 59
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