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DS34T102 Datasheet - Page 39

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Table 9-8. Global Clock Pins
(1)
(2)
PIN NAME
TYPE
PIN DESCRIPTION
CLK_SYS_S
Ipd
System Clock Selection Input
This pin specifies the frequency of the clock applied to the
section 10.4.
0 = 50 or 75 MHz
1 = 25 MHz
CLK_SYS
I
System Clock Input
A 25 MHz, 50 MHz or 75 MHz clock (50 ppm or better) must be applied to this pin
to clock TDM-over-Packet internal circuitry and the SDRAM interface (SD_CLK).
When a 25MHz clock is applied, it is internally multiplied by the CLAD2 block to
50MHz or 75MHz as specified by GCR1.SYSCLKS. The
whether the CLK_SYS signal is 25MHz (and therefore needs to multiplied up) or
50/75MHz (and therefore is used as-is). See section 10.4.
CLK_CMN
I
Common Clock Input
When the TDMoP engine is configured for common clock mode (also known as
differential mode), the common clock is applied to this pin. This clock signal has to
be a multiple of 8kHz and in the range of 1MHz to 25MHz. The frequency should
not be too close to an integer multiple of the service clock frequency. Based on
these criteria, the following frequencies are suggested:
For systems with access to a common SONET/SDH network, a frequency of 19.44
MHz (2430*8 kHz).
For systems with access to a common ATM network, 9.72 MHz (1215*8 kHz) or
19.44 MHz (2430*8 kHz).
For systems using GPS, 8.184 MHz (1023*8 kHz).
For systems connected by a single hop of 100 Mbit/s Ethernet where it is possible
to lock the physical layer clock, 25 MHz (3125*8 kHz).
For systems connected by a single hop of Gigabit Ethernet where it is possible to
lock to the physical layer clock, 10MHz (1250*8 kHz).
When a clock is not needed on this pin, pull it high or low. See section 10.4.
CLK_HIGH
I
Clock High Input
A 10, 19.44, 38.88 or 77.76MHz clock can be applied to this pin. From the
CLK_HIGH signal, an on-chip frequency converter block (called a clock adapter or
CLAD, in this case CLAD1) produces the 38.88MHz reference clock required by
the clock recovery machines in the TDMoP block. In addition, CLAD1 also
produces from the CLK_HIGH signal the 1.544MHz master clock (T1CLK) and the
2.048MHz master clock (E1CLK) required by the LIUs and framers.
GCR1.FREQSEL specifies the frequency of the clock applied to CLK_HIGH.
When GCR1.CLK_HIGHD=1, the CLAD disables the 38.88MHz reference clock to
the clock recovery machines.
When clock recovery is not required (i.e. when none of the recovered clock outputs
TDMn_ACLK
When a clock is not applied to CLK_HIGH, GCR1.MCLKE must be set to 1 and a
clock must be applied to the MCLK pin to give the CLAD a reference clock from
which to produce T1CLK and E1CLK for the LIUs and framers. See section 10.4.
The required quality of the CLK_HIGH signal is discussed in section 10.6.3.
MCLK
I
Master Clock Input
When the
clock must be applied to the MCLK pin, and GCR1.MCLKE must be set to 1. From
the MCLK signal, an on-chip frequency converter block (called a clock adapter or
CLAD) produces the 1.544MHz master clock (T1CLK) and the 2.048MHz master
clock (E1CLK) required by the LIUs and framers.
When a clock is present on the
and E1CLK from the
setting GCR1.MCLKE=0.
GCR1.MCLKS specifies whether the signal on MCLK is 1.544MHz or 2.048MHz.
See section 10.4.
are used), CLK_HIGH can be held low.
CLK_HIGH
pin is not used, a 2.048MHz ±50ppm or 1.544MHz ±32ppm
CLK_HIGH
CLK_HIGH
signal, and therefore MCLK can be disabled by
CLK_SYS
pin. See
CLK_SYS_S
pin specifies
pin, the CLAD can synthesize T1CLK
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