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DS34T102 Datasheet - Page 330

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Figure 14-6. Transmit Formatter Timing, Elastic Store Enabled
TSYSCLK
TSER
1 1
TSYNC
NOTES:
1.
TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Figure 14-7. Transmit Formatter Timing, Line Side with LIU Not Used
TCLKO
TDATF
14.3 CPU Interface Timing
Table 14-5. CPU Interface AC characteristics
PARAMETER
RST_SYS_N Active Low Pulse Width
H_CS_N Deasserted or H_R_W_N Low to H_D[31:0]
High-Z
H_READY_N Active Pull-Up Pulse Width
Latest of H_WR_BEx_N Asserted or H_CS_N Asserted
to H_D[31:0] Valid
H_CS_N Deasserted to H_D[31:0] Not Valid
H_CS_N Asserted to H_AD[24:1] Valid
H_CS_N Deasserted to H_AD[24:1] Not Valid
H_CS_N Asserted to H_R_W_N Valid
H_CS_N Deasserted to H_R_W_N Not Valid
H_CS_N Deasserted to H_READY_N High
H_CS_N Deasserted to H_WR_BEx_N[3:0] Not Valid
Delay Between Two Successive Accesses
H_D[31:0] Valid before H_READY_N Active Low
NOTE: The output timing specified assumes 50 pF load.
Figure 14-8. RST_SYS_N Timing
RST_SYS_N
t
SP
t
t
SL
SH
t
HD
t
SU
t
Hd
t
SU
t
CP
t
CL
t
D3
SYMBOL
MIN
T5
50
T22
T26
2.9
T31
T32
T33
T34
T35
T36
T37
T40
T43
1.5
T44
1.5
T5
t
CH
TYP
MAX
UNITS
s
16.2
ns
6.8
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
12
ns
0
ns
Internal
CLK_SYS
cycles
ns
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