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DS34T102 Datasheet - Page 302

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Register Name:
TBCS1, TBCS2, TBCS3, TBCS4
Register Description:
Transmit Blank Channel Select Registers
Register Address:
base address + 0x700, 0x704, 0x708, 0x70C
Bit #
7
TBCS1
CH8
CH7
TBCS2
CH16
CH15
TBCS3
CH24
CH23
TBCS4
CH32
CH31
Bits 7 to 0 (x4): Transmit Blank Channel Select for Channels 1 to 32 (CH1 to CH32). Reset defaults: CH1 to
C24 default to 0 while CH25 to CH32 default to 1. See section 10.10.
0 = Transmit data from the formatter’s TSER input for this channel
1 = Ignore data from the formatter’s TSER input for this channel
Note that when two or more sequential channels are chosen to be ignored, the transmit slip zone select bit
(TESCR.TSZS) should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29) then
the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications.
Register Name:
THSCS1, THSCS2, THSCS3, THSCS4
Register Description:
Transmit Hardware Signaling Channel Select Registers
Register Address:
base address + 0x720, 0x724, 0x728, 0x72C
Bit #
7
THSCS1
CH8
CH7
THSCS2
CH16
CH15
THSCS3
CH24
CH23
THSCS4*
CH32
CH31
Bits 7 to 0 (x4): Transmit Hardware Signaling Select for Channels 1 to 32 (CH1 to CH32). These bits
determine which channels have signaling data inserted from the formatter’s TSIG input.
0 = Do not source signaling data for this channel from the TSIG input
1 = Source signaling data for this channel from the TSIG input
*Note that THSCS4 is only used in applications where the system TDM interface is configured for 2.048MHz..
Register Name:
PCL1, PCL2, PCL3, PCL4
Register Description:
Per-Channel Loopback Enable Registers
Register Address:
base address + 0x740, 0x744, 0x748, 0x74C
Bit #
7
PCL1
CH8
CH7
PCL2
CH16
CH15
PCL3
CH24
CH23
PCL4
CH32
CH31
Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH1 to CH32). See section 10.11.11.
0 = Loopback disabled
1 = Enable loopback. Source data for the channel from the corresponding channel in the receive framer.
6
5
4
CH6
CH5
CH14
CH13
CH22
CH21
CH30
CH29
6
5
4
CH6
CH5
CH14
CH13
CH22
CH21
CH30
CH29
6
5
4
CH6
CH5
CH14
CH13
CH22
CH21
CH30
CH29
3
2
1
CH4
CH3
CH2
CH12
CH11
CH10
CH20
CH19
CH18
CH28
CH27
CH26
3
2
1
CH4
CH3
CH2
CH12
CH11
CH10
CH20
CH19
CH18
CH28
CH27
CH26
3
2
1
CH4
CH3
CH2
CH12
CH11
CH10
CH20
CH19
CH18
CH28
CH27
CH26
0
CH1
CH9
CH17
CH25
0
CH1
CH9
CH17
CH25
0
CH1
CH9
CH17
CH25
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