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DS34T102 Datasheet - Page 29

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
(1)
PIN NAME
TYPE
CLK_MII_RX
MII_RXD[3:0]
MII_RX_DV
MII_RX_ERR
MII_COL
MII_CRS
MDC
MDIO
IOpu
Global Clocks
CLK_SYS_S
CLK_SYS
CLK_CMN
CLK_HIGH
MCLK
CPU Interface
H_CPU_SPI_N
DAT_32_16_N
H_D[31:1]
H_D[0]
/
SPI_MISO
H_AD[24:1]
H_CS_N
H_R_W_N
/
SPI_CP
H_WR_BE0_N
/
SPI_CLK
H_WR_BE1_N
/
SPI_MOSI
H_WR_BE2_N
/
SPI_SEL_N
H_WR_BE3_N
/
SPI_CI
H_READY_N
H_INT[1:0]
JTAG Interface
JTRST_N
JTCLK
JTMS
JTDI
JTDO
Reset and Factory Test Pins
RST_SYS_N
HIZ_N
SCEN
STMD
MBIST_EN
MBIST_DONE
MBIST_FAIL
TEST_CLK
TST_CLD
TST_Tm, TST_Rm
Power and Ground
DVDDC
DVDDIO
DVSS
DVDDLIU
DVSSLIU
ATVDDn
ATVSSn
ARVDDn
ARVSSn
ACVDD1, ACVDD2
ACVSS1, ACVSS2
(2)
PIN DESCRIPTION
I
MII Receive Clock Input
I
MII Receive Data Inputs
I
MII Receive Data Valid Input
I
MII Receive Error Input
I
MII Collision Input
I
MII Carrier Sense Input
O
PHY Management Clock Output
PHY Management Data Input/Output
I
System Clock Selection Input
I
System Clock Input: 25, 50 or 75MHz
I
Common Clock Input (for common clock mode also known as differential mode)
I
Clock High Input (for adaptive clock recovery machines and E1/T1 master clocks)
I
Master Clock Input (for E1/T1 master clocks)
Ipu
Host Bus Interface (1=Parallel Bus, 0=SPI Bus)
Ipu
Data Bus Width (1=32-bit , 0=16-bit)
IO
Host Data Bus
IO
Host Data LSb or SPI Data Output
I
Host Address Bus
I
Host Chip Select (Active Low)
I
Host Read/Write Control or SPI Clock Phase
I
Host Write Enable Byte 0 (Active Low) or SPI Clock
I
Host Write Enable Byte 1 (Active Low) or SPI Data Input
I
Host Write Enable Byte 2 or SPI Chip Select (Active Low)
I
Host Write Enable Byte 3 (Active Low) or SPI Clock Invert
Oz
Host Ready Output (Active Low)
O
Host Interrupt Outputs. H_INT[0] for TDMoP. H_INT[1] for LIU and Framer
Ipu
JTAG Test Reset
Ipd
JTAG Test Clock
Ipu
JTAG Test Mode Select
Ipu
JTAG Test Data Input
Oz
JTAG Test Data Output
Ipu
System Reset (Active Low)
I
High Impedance Enable (Active Low)
Ipd
Used for factory tests.
Ipd
Used for factory tests.
I
Used for factory tests.
O
Used for factory tests.
O
Used for factory tests
O
Used for factory tests.
I
Used for factory tests.
O
m = A , B or C. Used for factory tests. DS34T104 only.
P
1.8V Core Voltage for Framers and TDM-over-Packet Digital Logic (17 pins)
P
3.3V for I/O Pins (16 pins)
P
Ground for Framers, TDM-over-Packet and I/O Pins (31 pins)
P
3.3V for LIU Digital Logic (2 pins)
P
Ground for LIU Digital Logic (2 pins)
P
3.3 V for LIU Transmitter Analog Circuits (8pins)
P
Ground for LIU Transmitter Analog Circuits (8 pins)
P
3.3 V for LIU Receiver Analog Circuits (8 pins)
P
Ground for LIU Receiver Analog Circuits (8 pins)
P
1.8V for CLAD Analog Circuits
P
Ground for CLAD Analog Circuits
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