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DS34T102 Datasheet - Page 262

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Bit 2: Spare Code Detected Condition Detect (LSPD).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Loop Down Code Detected Condition Detect (LDND).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Loop Up Code Detected Condition Detect (LUPD).
0 = interrupt masked
1 = interrupt enabled
Register Name:
RIM3-E1
Register Description:
Receive Interrupt Mask Register 3 (E1 Mode)
Register Address:
base address + 0x288
Bit #
7
6
Name
LORCC
-
Default
0
0
Note: This register has an alternate definition for T1 mode. See RIM3-T1.
The bits in the register are interrupt mask/enable bits for corresponding latched status bits in RLS3-E1.
Bit 7: Loss of Receive Clock Clear (LORCC).
0 = interrupt masked
1 = interrupt enabled
Bit 5: V5.2 Link Detected Clear (V52LNKC).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive Distant MF Alarm Clear (RDMAC).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Loss of Receive Clock Detect (LORCD).
0 = interrupt masked
1 = interrupt enabled
Bit 1: V5.2 Link Detect (V52LNKD).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Distant MF Alarm Detect (RDMAD).
0 = interrupt masked
1 = interrupt enabled
5
4
3
V52LNKC
RDMAC
LORCD
0
0
0
2
1
0
-
V52LNKD
RDMAD
0
0
0
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