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DS34T102 Datasheet - Page 259

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Register Name:
RSS1, RSS2, RSS3, RSS4
Register Description:
Receive Signaling Status Registers
Register Address:
base address + 0x260, 0x264, 0x268, 0x26C
Bit #
7
6
RSS1
CH8
CH7
RSS2
CH16
CH15
RSS3
CH24
CH23
RSS4
CH32
CH31
Bits 7 to 0 (x4): Receive Signaling Change Latched Status for Channels 1 to 32 (CH1 to CH32). When a
channel’s signaling data changes state, the latched status bit for that channel is set to 1 in these registers. The
RLS4.RSCOS bit is also set if the channel is enabled by the corresponding bit in the
of RLS4.RSCOS generates an interrupt request if enabled by RIM4.RSCOS. Each bit in these registers is cleared
when written with a 1. See Section 10.11.3.2.
*Note that in E1CAS mode, the LSb of RSS1 typically represents the CAS alignment bits, and the LSB of RSS3
represents reserved bits and the distant multiframe alarm.
Register Name:
RSCD1
Register Description:
Receive Spare Code Definition Register 1 (T1 Mode Only)
Register Address:
base address + 0x270
Bit #
7
6
Name
C7
C6
Default
0
0
Note: Writing this register resets the detector’s integration period. See Section 10.11.14.
Bit 7: Receive Spare Code Definition Bit 7 (C7). First bit of the repeating pattern.
Bit 6: Receive Spare Code Definition Bit 6 (C6). Ignored if a 1-bit length is selected.
Bit 5: Receive Spare Code Definition Bit 5 (C5). Ignored if a 1 or 2 bit length is selected.
Bit 4: Receive Spare Code Definition Bit 4 (C4). Ignored if a 1 to 3 bit length is selected.
Bit 3: Receive Spare Code Definition Bit 3 (C3). Ignored if a 1 to 4 bit length is selected.
Bit 2: Receive Spare Code Definition Bit 2 (C2). Ignored if a 1 to 5 bit length is selected.
Bit 1: Receive Spare Code Definition Bit 1 (C1). Ignored if a 1 to 6 bit length is selected.
Bit 0: Receive Spare Code Definition Bit 0 (C0). Ignored if a 1 to 7 bit length is selected.
Register Name:
RSCD2
Register Description:
Receive Spare Code Definition Register 2 (T1 Mode Only)
Register Address:
base address + 0x274
Bit #
7
6
Name
C15
C14
Default
0
0
Bit 7: Receive Spare Code Definition Bit 15 (C15). Ignored if a 1 to 7 bit length is selected.
Bit 6: Receive Spare Code Definition Bit 14 (C14). Ignored if a 1 to 7 bit length is selected.
Bit 5: Receive Spare Code Definition Bit 13 (C13). Ignored if a 1 to 7 bit length is selected.
Bit 4: Receive Spare Code Definition Bit 12 (C12). Ignored if a 1 to 7 bit length is selected.
Bit 3: Receive Spare Code Definition Bit 11 (C11). Ignored if a 1 to 7 bit length is selected.
Bit 2: Receive Spare Code Definition Bit 10 (C10). Ignored if a 1 to 7 bit length is selected.
Bit 1: Receive Spare Code Definition Bit 9 (C9). Ignored if a 1 to 7 bit length is selected.
Bit 0: Receive Spare Code Definition Bit 8 (C8). Ignored if a 1 to 7 bit length is selected.
5
4
3
CH6
CH5
CH4
CH14
CH13
CH12
CH22
CH21
CH20
CH30
CH29
CH28
5
4
3
C5
C4
C3
0
0
0
5
4
3
C13
C12
C11
0
0
0
2
1
0
CH3
CH2
CH1*
CH11
CH10
CH9
CH19
CH18
CH17*
CH27
CH26
CH25
RSCSE
registers. The setting
2
1
0
C2
C1
C0
0
0
0
2
1
0
C10
C0
C8
0
0
0
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