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DS34T102 Datasheet - Page 255

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
It is cleared when written with a 1. When RSA1 is set it can cause an interrupt request if the RSA1 interrupt enable
bit is set in the
RIM2
register.
Bit 2: Receive Signaling All Zeros Event (RSA0). This latched status bit is set to 1 when, over a full MF, timeslot
16 contains all zeros. It is cleared when written with a 1. When RSA0 is set it can cause an interrupt request if the
RSA0 interrupt enable bit is set in the
Bit 1: Receive CRC-4 Multiframe Event (RCMF). This latched status bit is set to 1 on CRC-4 multiframe
boundaries. It continues to be set every 2 ms on an arbitrary boundary if CRC-4 is disabled. It is cleared when
written with a 1. When RCMF is set it can cause an interrupt request if the RCMF interrupt enable bit is set in the
RIM2
register.
Bit 0: Receive Align Frame Event (RAF). This latched status bit is set to 1 approximately every 250  s to alert the
CPU that Si and Sa bits are available in the
RAF is set it can cause an interrupt request if the RAF interrupt enable bit is set in the
Register Name:
RLS3-T1
Register Description:
Receive Latched Status Register 3 (T1 Mode)
Register Address:
base address + 0x248
Bit #
7
6
Name
LORCC
LSPC
Default
0
0
Note: This register has an alternate definition for E1 mode. See RLS3-E1.
Bit 7: Loss of Receive Clock Condition Clear (LORCC). This latched status bit is set to 1 when
T1.LORC changes state from high to low. LORCC is cleared when written with a 1. When LORCC is set it can
cause an interrupt request if the LORCC interrupt enable bit is set in the
Bit 6: Spare Code Detected Condition Clear (LSPC). This latched status bit is set to 1 when RRTS3-T1.LSP
changes state from high to low. LSPC is cleared when written with a 1. When LSPC is set it can cause an interrupt
request if the LSPC interrupt enable bit is set in the
Bit 5: Loop Down Code Detected Condition Clear (LDNC). This latched status bit is set to 1 when
T1.LDN changes state from high to low. LDNC is cleared when written with a 1. When LDNC is set it can cause an
interrupt request if the LDNC interrupt enable bit is set in the
Bit 4: Loop Up Code Detected Condition Clear (LUPC). This latched status bit is set to 1 when RRTS3-T1.LUP
changes state from high to low. LUPC is cleared when written with a 1. When LUPC is set it can cause an interrupt
request if the LUPC interrupt enable bit is set in the
Bit 3: Loss of Receive Clock Condition Detect (LORCD). This latched status bit is set to 1 when
T1.LORC changes state from low to high. LORCD is cleared when written with a 1. When LORCD is set it can
cause an interrupt request if the LORCD interrupt enable bit is set in the
Bit 2: Spare Code Detected Condition Detect (LSPD). This latched status bit is set to 1 when RRTS3-T1.LSP
changes state from low to high. LSPD is cleared when written with a 1. When LSPD is set it can cause an interrupt
request if the LSPD interrupt enable bit is set in the
Bit 1: Loop Down Code Detected Condition Detect (LDND). This latched status bit is set to 1 when
T1.LDN changes state from low to high. LDND is cleared when written with a 1. When LDND is set it can cause an
interrupt request if the LDND interrupt enable bit is set in the
Bit 0: Loop Up Code Detected Condition Detect (LUPD). This latched status bit is set to 1 when RRTS3-T1.LUP
changes state from low to high. LUPD is cleared when written with a 1. When LUPD is set it can cause an interrupt
request if the LUPD interrupt enable bit is set in the
RIM2
register.
RAF
and
RNAF
registers. It is cleared when written with a 1. When
5
4
3
LDNC
LUPC
LORCD
0
0
0
RIM3-T1
register. See Section 10.11.14.2.
RIM3-T1
RIM3-T1
register. See Section 10.11.14.2.
RIM3-T1
register. See Section 10.11.14.2.
RIM3-T1
RIM3-T1
register. See Section 10.11.14.2.
RIM2
register.
2
1
LSPD
LDND
0
0
RIM3-T1
register.
register. See Section 10.11.14.2.
RIM3-T1
register.
register. See Section 10.11.14.2.
0
LUPD
0
RRTS3-
RRTS3-
RRTS3-
RRTS3-
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