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DS34T102 Datasheet - Page 253

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Register Name:
RBPBS
Register Description:
Receive BERT Port Bit Suppress Register
Register Address:
base address + 0x22C
Bit #
7
6
Name
RBPBS8
RBPBS7
Default
0
0
Bit 7: Receive BERT Port Bit Suppress (RBPBS[8:1]). When one of these bits is set, the corresponding bit in the
64kbps channel is ignored (suppressed) by the Rx BERT when looking at the incoming pattern. RBPBS8
corresponds to the MSb of the channel. See section 10.14.3.
Register Name:
RLS1
Register Description:
Receive Latched Status Register 1
Register Address:
base address + 0x240
Bit #
7
6
Name
RRAIC
RAISC
Default
0
0
Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC). This latched status bit is set to 1 when
RRTS1.RRAI changes state from high to low. RRAIC is cleared when written with a 1. When RRAIC is set it can
cause an interrupt request if the RRAIC interrupt enable bit is set in the
Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC). This latched status bit is set to 1 when
RRTS1.RAIS changes state from high to low. RAISC is cleared when written with a 1. When RAISC is set it can
cause an interrupt request if the RAISC interrupt enable bit is set in the
Bit 5: Receive Loss of Signal Condition Clear (RLOSC). This latched status bit is set to 1 when RRTS1.RLOS
changes state from high to low. RLOSC is cleared when written with a 1. When RLOSC is set it can cause an
interrupt request if the RLOSC interrupt enable bit is set in the
Bit 4: Receive Loss of Frame Condition Clear (RLOFC). This latched status bit is set to 1 when RRTS1.RLOF
changes state from high to low. RLOFC is cleared when written with a 1. When RLOFC is set it can cause an
interrupt request if the RLOFC interrupt enable bit is set in the
Bit 3: Receive Remote Alarm Indication Condition Detect (RRAID). This latched status bit is set to 1 when
RRTS1.RRAI changes state from low to high. RRAID is cleared when written with a 1. When RRAID is set it can
cause an interrupt request if the RRAID interrupt enable bit is set in the
Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD). This latched status bit is set to 1 when
RRTS1.RAIS changes state from low to high. RAISD is cleared when written with a 1. When RAISD is set it can
cause an interrupt request if the RAISD interrupt enable bit is set in the
Bit 1: Receive Loss of Signal Condition Detect (RLOSD). This latched status bit is set to 1 when RRTS1.RLOS
changes state from low to high. RLOSD is cleared when written with a 1. When RLOSD is set it can cause an
interrupt request if the RLOSD interrupt enable bit is set in the
Bit 0: Receive Loss of Frame Condition Detect (RLOFD). This latched status bit is set to 1 when RRTS1.RLOF
changes state from low to high. RLOFD is cleared when written with a 1. When RLOFD is set it can cause an
interrupt request if the RLOFD interrupt enable bit is set in the
5
4
3
RBPBS6
RBPBS5
RBPBS4
0
0
0
5
4
3
RLOSC
RLOFC
RRAID
0
0
0
RIM1
register. See Section 10.11.6.
RIM1
register. See Section 10.11.6.
RIM1
register. See Section 10.11.6.
RIM1
register. See Section 10.11.6.
2
1
RBPBS3
RBPBS2
0
0
2
1
RAISD
RLOSD
0
0
RIM1
register. See Section 10.11.6.
RIM1
register. See Section 10.11.6.
RIM1
register. See Section 10.11.6.
RIM1
register. See Section 10.11.6.
0
RBPBS1
0
0
RLOFD
0
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