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DS34T102 Datasheet - Page 250

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Register Name:
RESCR
Register Description:
Receive Elastic Store Control Register
Register Address:
base address + 0x214
Bit #
7
6
Name
RDATFMT
Reserved
Default
0
0
Bit 7: Receive Channel Data Format (RDATFMT).
0 = 64KBps (data contained in all 8 bits)
1 = 56KBps (data contained in 7 out of the 8 bits)
Bit 6: Reserved
Bit 4: Receive Slip Zone Select (RSZS). This bit determines the minimum distance allowed between the elastic
store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1
conversion applications. See section 10.10.
0 = Force a slip at 9 bytes or less of separation (used for clustered blank channels)
1 = Force a slip at 2 bytes or less of separation (used for distributed blank channels and minimum delay
mode)
Bit 3: Receive Elastic Store Align (RESALGN). Changing this bit from zero to one forces the receive elastic
store’s write and read pointers to a minimum separation of half a frame. No action is taken if the pointer separation
is already greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed
and the data is disrupted. This bit should be toggled during start-up after RSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See section 10.10.1.
Bit 2: Receive Elastic Store Reset (RESR). Changing this bit from zero to one forces the read pointer into the
same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should
place the pointers within the slip zone (specified by RSZS above), then a slip immediately occurs and the pointers
move back to opposite frames. This bit should be toggled after RSYSCLK has been applied and is stable. Do not
leave this bit set high. See section 10.10.1.
Bit 1: Receive Elastic Store Minimum Delay Mode (RESMDM). See section 10.10.2.
0 = Elastic store operates at full two-frame depth
1 = Elastic store operates at 32–bit depth
Bit 0: Receive Elastic Store Enable (RESE). See section 10.10.
0 = Elastic store is bypassed
1 = Elastic store is enabled
Register Name:
ERCNT
Register Description:
Error Counter Configuration Register
Register Address:
base address + 0x218
Bit #
7
6
Name
Reserved
MCUS
Default
0
0
Bit 7: Reserved. This bit must be set to zero.
Bit 6: Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS=1, this bit can
be used to allow a zero-to-one transition on GCR1.GFCLE to load the error counter registers with the latest counts
and reset the counters. Useful for synchronously updating counter registers of multiple framers at the same time.
See section 10.11.8.
5
4
3
-
RSZS
RESALGN
0
0
0
5
4
3
MECU
ECUS
EAMS
0
0
0
2
1
0
RESR
RESMDM
RESE
0
0
0
2
1
0
MOSCRF
FSBE
LCVCRF
0
0
0
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