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DS34T102 Datasheet - Page 238

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Bit 2: CRC-4 MF Sync Active (CRC4SA). This real-time status bit is set while the synchronizer is searching for the
CRC-4 MF alignment word.
Bit 1: CAS MF Sync Active (CASSA). This real-time status bit is set while the synchronizer is searching for the
CAS MF alignment word.
Bit 0: FAS Sync Active (FASSA). This real-time status bit is set while the synchronizer is searching for alignment
at the FAS level.
Register Name:
RBOC
Register Description:
Receive Bit-Oriented Code Register (T1 Mode Only)
Register Address:
base address + 0x18C
Bit #
7
6
Name
-
-
Default
0
0
Bits 5 to 0: Rx Bit-Oriented Code (RBOC[5:0]). T1 ESF mode only. After a BOC has been validated per the
criteria specified by RBOCC.RBF, the BOC is stored in this field where it can be read by software. The device
notifies software that a valid BOC is available by setting the BD bit in RLS7. Setting BD can optionally drive an
interrupt request. Bit 0 is the first bit received. See section 10.11.4.2.
Register Name :
RSLC1, RSLC2, RSLC3
Register Description:
Receive SLC96 Data Link Registers (T1 Mode)
Register Address:
base address + 0x190, 0x194, 0x198
Bit #
7
6
RSLC1
C8
C7
RSLC2
M2
M1
RSLC3
S=1
S4
Note: These registers have an alternate definition for E1 mode. See RAF, RNAF, and RSiAF.
See section 10.11.16.
Register Name:
RAF
Register Description:
Receive Align Frame Register (E1 Mode)
Register Address:
base address + 0x190
Bit #
7
6
Name
Si
FAS6
Default
0
0
Note: This register has an alternate definition for T1 mode. See RSLC1.
The align frame is the E1 frame containing the frame alignment signal (FAS). The bits of this register indicate the
first eight bits received in the most recent align frame. The bits are latched into this register at the start of the align
frame. The start of the align frame is indicated by the RAF status bit in RLS2-E1. See Section 10.11.5.1.
Bit 7: International Bit (Si).
Bits 6 to 0: Frame Alignment Signal (FAS[6:0]). When a normal E1 signal is being received, FAS[6:0]=0011011.
5
4
3
RBOC5
RBOC4
RBOC3
0
0
0
5
4
3
C6
C5
C4
S=0
S=1
S=0
S3
S2
S1
5
4
3
FAS5
FAS4
FAS3
0
0
0
2
1
0
RBOC2
RBOC1
RBOC0
0
0
0
2
1
0
C3
C2
C1
C11
C10
C9
A2
A1
M3
2
1
0
FAS2
FAS1
FAS0
0
0
0
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