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DS34T102 Datasheet - Page 218

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
The
MAC_PHY_maintenance
register below enables the MAC to communicate with a PHY by means of the
interface. It is used during auto negotiation to ensure that the MAC and the PHY are configured for the same speed
and duplex configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation
which is signaled as complete when the
(about 2000
CLK_SYS
cycles later). An interrupt is generated as this bit is set. During this time, the MSB of the
register is output on the
MDIO
pin and the LSB is updated from the
PHY management packet is transmitted on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading
during the shift operation (not recommended) returns the current contents of the shift register.
At the end of the shift operation, the bits have shifted back to their original locations. For a read operation, the data
bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a
valid PHY management packet is produced.
MAC_PHY_maintenance 0x034
Bits
Data Element Name
[31:30]
Start_of_packet
[29:28]
Operation
[27:23]
PHY_address
[22:18]
Register_address
[17:16]
Must_be_written_to_10
[15:0]
PHY_data
MAC_pause_time 0x038
Bits
Data Element Name
[31:16]
Reserved
[15:0]
Pause time
MAC_specific_address_lower 0x098
Bits
Data Element Name
[31:0]
MAC Specific Address [31:0]
MAC_specific_address_upper 0x09C
Bits
Data Element Name
[31:16]
Reserved
[15:0]
MAC Specific Address [47:32]
PHY_access_has_completed
bit is set in the
MDIO
Reset
R/W
Value
R/W
0x0
Must be written 01 for a valid packet
R/W
0x0
00 = Reserved
01 = Write
10 = Read
11 = Reserved
R/W
0x0
Specifies the PHY to access
R/W
0x0
Specifies the register in the PHY to access
R/W
0x0
Read as written
R/W
0x0000
For a write operation this field is the data to be written to
the PHY. After a read operation this field contains the data
read from the PHY
Reset
R/W
Value
RO
0x0000
Read 0, ignored on write
RO
0x0000
Stores the current value of the pause time register, which
is decremented every 512 bit times.
Reset
R/W
Value
R/W
0x0
Least significant bits of the MAC specific address, i.e. bits
31:0. This field is used for transmission of pause packets
as described in section 10.6.12.2.
Reset
R/W
Value
RO
0x0000
Read 0, ignored on write
R/W
0x0000
Most significant bits of the MAC specific address, i.e. bits
47:32. See
MAC_specific_address_lower
M AC_network_status
register
3
pin with each
MDC
cycle. In this way a
Description
Description
Description
Description
for details.
218 of 366
MDIO

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