Datasheets»Maxim Integrated»DS34T102 Datasheet

DS34T102 Datasheet - Page 191

Download or read online Maxim Integrated DS34T102 Dual TDM-Over-Packet Chip pdf datasheet.



Page
191 of 366
prevnext
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
11.4.6 CPU Queues
The pools and queue referred to in this section are shown in the block diagram in
or pool level exceeds the associated threshold register, a latched status bit is set in the
register which generates an interrupt unless masked by the associated mask bit in the
register.
In this section the address offsets in parentheses apply when the CPU data bus is 16 bits wide (pin
). The base address for the TDMoP CPU queues is 0x20,000.
DAT_32_16_N=0
Table 11-7. CPU Queues
Addr
Register Name
Offset
0x00 (0x02)
T DM_to_CPU_pool_insert
3
0x04 (0x06)
T DM_to_CPU_pool_level
3
0x08 (0x0A)
TDM_to_CPU_pool_thresh
0x0C (0x0E)
T DM_to_CPU_q_read
3
0x10 (0x12)
T DM_to_CPU_q_level
3
0x14 (0x16)
T DM_to_CPU_q_thresh
3
0x18 (0x1A)
C PU_to_ETH_q_insert
3
0x1C (0x1E)
C PU_to_ETH_q_level
3
0x20 (0x22)
C PU_to_ETH_q_thresh
3
0x24 (0x26)
E TH_to_CPU_pool_insert
3
0x28 (0x2A)
E TH_to_CPU_pool_level
3
0x2C (0x2E)
E TH_to_CPU_pool_thresh
3
0x30 (0x32)
E TH_to_CPU_q_read
3
0x34 (0x36)
E TH_to_CPU_q_level
3
0x38 (0x3A)
E TH_to_CPU_q_thresh
3
Error! Reference source
0x54 (0x56)
not found.
0x58 (0x5A)
Error! Reference source
not found.
0x5C (0x5E)
C PU_to_TDM_q_thresh
3
0x60 (0x62)
T x_return_q_read
3
0x64 (0x66)
T x_return _q _level
3
0x68 (0x6A)
T x_return_q_thresh
3
0x6C (0x6E)
R x_return_q_read
3
0x70 (0x72)
R x_return_q_level
3
0x74 (0x76)
R x_return_q_thresh
3
11.4.6.1 TDM-to-CPU Pool
TDM_to_CPU_pool_insert 0x00 (0x02)
Bits
Data Element Name
[31:13]
Reserved
[12:0]
Buffer ID
Description
Write to insert a buffer ID into the TDM-to-CPU Pool
Number of buffers stored in the TDM-to-CPU Pool
TDM-to-CPU Pool interrupt threshold
Read to get a buffer ID from the TDM-to-CPU Queue
Number of buffers in the TDM-to-CPU Queue
TDM-to-CPU Queue interrupt threshold
Write to insert a buffer ID into the CPU-to-ETH Queue
Number of buffers in the CPU-to-ETH Queue
CPU-to-ETH Queue interrupt threshold
Write to insert a buffer ID into the ETH-to-CPU Pool
Number of buffers stored in the ETH-to-CPU Pool
ETH-to-CPU Queue interrupt threshold.
Read to get a buffer ID from the ETH-to-CPU Queue
Number of buffers in the ETH-to-CPU Queue.
ETH-to-CPU Queue interrupt threshold
Write to insert a buffer ID into the CPU-to-TDM Queue
Number of buffers stored in the CPU-to-TDM Queue
CPU-to-TDM Queue interrupt threshold
Read to get a buffer ID from the CPU-Tx-return Queue
Number of buffers stored in the CPU-Tx-return Queue
CPU-Tx-return Queue interrupt threshold
Read to get a buffer ID from the CPU-Rx-return Queue
Number of buffers stored in the CPU-Rx-return Queue
CPU-Rx-return Queue interrupt threshold
Reset
R/W
Value
-
0x0
Must be set to zero
WO
None
Writing to this address causes a single 13-bit buffer ID to
be inserted to the TDM-to-CPU pool. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[23:11]
out of the 24 SDRAM address bits).
Figure
10-49. Whenever a queue
CPU_Queues_change
CPU_Queues_mask
Page
191
192
1 92
3
192
192
192
192
193
193
193
193
193
194
194
194
Error!
Bookmark
not defined.
Error!
Bookmark
not defined.
194
195
195
195
195
196
196
Description
191 of 366

Comments to this Datasheet