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DS34T102 Datasheet - Page 179

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
HDLC_Bundle[n]_cfg[127:96] 0x300+n*4
Bits
Data Element Name
[7:4]
Port_num
[3:2]
Tx_VLAN_stack
[1]
Rx_Bundle_Identifier_valid
[0]
Reserved
HDLC_Bundle[n]_cfg[159:128] 0x400+n*4
Bits
Data Element Name
[31:22]
Reserved
[21:20]
Rx_L2TPV3_cookies
[19:16]
Reserved
[15:0]
Tx_IP_checksum
Reset
R/W
Value
00 = No cookies in the TX L2TPv3 header
01 = One cookie in the TX L2TPv3 header
10 = Two cookies in the TX L2TPv3 header
11 = Reserved
The port number which the bundle is assigned to:
None
R/W
0000 = Port 1, 0111=Port 8
00 = No VLAN tag in header
01 = One VLAN tag exists in header
10 = Two VLAN tags exist in header
None
R/W
11 = Reserved
Not valid for Rx. Not used by Tx AAL1 but by Ethernet
MAC transmit block
0 =
Rx_bundle_identifier
frame bundle identifier isn't found in the whole packet
classifier table, the incoming frame is handled
None
R/W
according to discard switches in
(Packet_classifier_cfg_reg3)
1 = Rx_Bundle_Identifier entry is valid
None
Must be set to zero
R/W
Reset
R/W
Value
Must be set to zero
0x000
For MPLS:
00 = Reserved
01 = One label in the received MPLS stack
10 = Two label in the received MPLS stack
11 = Three label in the received MPLS stack
None
R/W
For L2TPv3:
00 = No cookies in the received L2TPv3 header
01 = One cookie in the received L2TPv3 header
10 = Two cookies in the received L2TPv3 header
11 = Reserved
None
R/W
IP header checksum for IP total length equal to zero
None
R/W
Explain more. Also, why isn’t this in AAL1?
Description
entry isn't valid: If the incoming
Description
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