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DS34T102 Datasheet - Page 166

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
Rst_reg 0x2C
Bits
Data Element Name
[31:28]
Reserved
[27:24]
Rst_tx_port_num
[23:18]
Rst_tx_internal_bundle_num
[17]
Rst_tx_open/close
[16]
Rst_tx
[15:7]
Reserved
[6:1]
Rst_rx_internal_bundle_num
[0]
Rst_rx
Reset
R/W
Value
-
0x0
Must be set to zero
Port number associated with
0000 = Port 1
0001 = Port 2
0010 = Port 3
R/W
0x0
0011 = Port 4
0100 = Port 5
0101 = Port 6
0110 = Port 7
0111 = Port 8
R/W
0x00
Bundle number associated with
Valid when
Rst_tx
0 = When Rst_tx is done during bundle close procedure
R/W
0x0
1 = When Rst_tx is done during bundle open procedure
This bit is also used in high-speed mode.
If set, the relevant transmit payload type machine resets
its variables (should be given with bundle number and a
R/W
0x0
proper value of the RST_tx_open/close bit). The CPU
should poll this bit until it is 0 meaning, “reset
acknowledged”. This bit is also used in high-speed mode.
R/W
0x0
Must be set to zero
R/W
0x00
Bundle number associated with Rst_rx
1 = Packet classifier generates a reset frame
Reference source not found.
R/
0x0
Rst_rx_internal_bundle_num
set
poll this bit until it finds 0; this means “reset
acknowledged”.
Description
Rst_tx
field (below).
Rst_tx
field (below)
is set
(Error!
and
are valid). The CPU should
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