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DS34T102 Datasheet - Page 132

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
10.12.2 Transmit HDLC Controller
The transmit HDLC controller is enabled when THC2.THCE=1. A low-to-high transition on THC1.THR resets the
transmit HDLC controller and flushes the transmit HDLC FIFO. In T1 ESF mode, the transmit HDLC controller can
be connected to the FDL (THC1.THMS=1) or to any DS0 channel (THMS=0). In E1 mode, it can be connected to
an Sa bit channel (THMS=1) or to any DS0 channel (THMS=0). The THC2.THCS field specifies the DS0 channel
when THMS=0. When THC1.TCRCD=0, the transmit HDLC controller automatically generates the CRC-16 (the
frame check sequence or FCS) and transmits it after the last byte of the packet. When TCRCD=1, this automatic
CRC generation is disabled. When the transmit HDLC controller is connected to a DS0 channel, it can be
configured to fill or ignore individual bit positions of the DS0 channel by setting the bit fields of the
THBSE
register
appropriately.
The CPU can write the transmit HDLC FIFO one byte at a time by writing the
THF
register. When the transmit
FIFO’s fill status transitions from full to not-full, TLS2.TNFS is set to one to inform the CPU that space is available
in the transmit FIFO for additional data. The lower seven bits of the
TFBA
register (TFBA[6:0]) are a real-time field
that indicates the number of bytes of space available transmit FIFO for additional data. The CPU must take into
account the value of the TFBA.TFBA field when writing the FIFO to prevent FIFO overrun. There is no overrun
indication available from the Tx HDLC controller. Just before writing the last byte of a message to the Tx HDLC
FIFO, the CPU must set THC1.TEOM to delineate the message.
If software writes the FIFO more slowly than the Tx HDLC controller reads it, the fill level of the FIFO falls. When
the HDLC empties below the transmit low watermark set in THFC.TFLWM, the TLS2.TLWMS latched status bit is
set. If the FIFO underruns, the Tx HDLC controller automatically transmits an abort, and the latched status bit
TLS2.TUDR is set to indicate the underrun.
The real-time status bits in
TRTS2
and the latched status bits in
TLS2
provide plus the message status bit (MS) in
RHPBA
provide FIFO empty/full status and message progress status to the system. In TLS2, the TMEND latched
status bit indicates when the Tx HDLC controller has finished sending a message. The latched status bits in
TLS2
cause interrupt requests if enabled by the associated interrupt enable bits in TIM2.
A variety of configuration settings are available using the bits in
THC1
and THC2. THC1.NOFS specifies whether
one or two flags (0x7E) are sent between consecutive messages. THC1.TFS specifies whether the inter-message
fill character between closing flags and opening flags is 0x7E or 0xFF. THC1.TZSD=1 disables the Tx bit stuffer
logic. This logic normally inserts a zero into the message bit stream after 5 consecutive ones to prevent the
emulation of a flag or abort sequence by the data pattern. When THC1.TEOML=1, the last message written into
the Tx FIFO is send repeatedly until the Tx HDLC controller is told to stop. Finally the CPU can abort the message
currently being sent by setting THC2.TABT=1.
10.12.2.1 Transmit HDLC Controller Example
The transmit HDLC controller status and control fields provide flexibility to support various software
implementations for transmit HDLC servicing. Polling, interrupt-driven or combination approaches are all feasible. A
flowchart of an example receive HDLC servicing routine is shown in
Figure 10-66
above.
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