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DS34T102 Datasheet - Page 118

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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 Receive Signaling Reinsertion at RSER
In this mode, the system provides a multiframe sync at the framer’s RSYNC input, and the signaling data is
reinserted based on this alignment. In T1 mode, this results in two versions of the signaling data: the original
signaling data based on the Fs/ESF frame positions, and the realigned data based on the system-supplied
multiframe sync applied at RSYNC. In voice channels this extra copy of signaling data is of little consequence.
Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion,
the elastic store must be enabled, and for T1, the system TDM interface clock (RSYSCLK) can be either 1.544MHz
or 2.048MHz. E1 signaling information cannot be reinserted into a 1.544MHz system TDM interface.
Signaling reinsertion mode is enabled on a per-channel basis by setting the appropriate bits in the
registers. In E1 mode, the CPU would generally select all channels or none for reinsertion. Force Receive Signaling All Ones
In T1 mode only, when RSIGC.RFSA1=1, the CPU can, on a per-channel basis, force the robbed bit signaling bit
positions to one by setting the appropriate bit(s) in the Receive Signaling Freeze
When RSIGC.RSFE=1 the signaling data in the four-multiframe signaling buffers is automatically frozen when any
of these events occurs: loss of signal (receive carrier loss), loss of frame (OOF event) or change of frame
alignment). In T1 mode, this action meets the requirements of Bellcore TR-TSY-000170 for signaling freezing. In
addition to automatic signaling freeze, the CPU can force a signaling freeze by setting the RSIGC.RSFF control bit
high. The RSIG output provides a hardware indication that a freeze is in effect. The four-multiframe buffer provides
a three multiframe delay in the signaling information provided at the RSIG signal (and at RSER if receive signaling
reinsertion is enabled). When freezing is enabled, the signaling data is held in the last known good state until the
corrupting error condition subsides. When the error condition subsides, the signaling data is held in the old state for
at least an additional 9ms (4.5ms in SF framing mode, 6ms for E1 mode) before being updated with new signaling
10.11.4 T1 Datalink T1 ESF Transmit Bit-Oriented Code (BOC) Controller
The transmit formatter contains a BOC generator that can insert codes into the facilities data link (FDL) of the T1
ESF. This function is only available in T1 ESF mode. The registers related to transmitting bit oriented codes are
shown in the following table.
Table 10-42. Registers Related to T1 Transmit BOC
Register Name
Transmit Bit-Oriented Code Register
Transmit HDLC Control Register 2
Transmit Control Register
The lower six bits of
specify the BOC message to be transmitted. Setting THC2.SBOC=1 causes the
transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit positions. The transmit
BOC controller automatically provides the abort sequence. BOC messages are transmitted as long as SBOC is set.
Note that the TCR1-T1.TFPT must be set to zero for the BOC message to overwrite F-bit information being
sampled on TSER. T1 ESF Receive Bit-Oriented Code (BOC) Controller
The receive framer contains a BOC detector that can detects and reports codes in the facilities data link (FDL) of
the T1 ESF. This function is only available in T1 ESF mode. The registers related to receiving bit oriented codes
are shown in the following table.
BOC message to be transmitted
SBOC bit enables Tx of BOC
TFPT bit specifies F-bit source
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