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DS34T102 Datasheet

Download or read online Maxim Integrated DS34T102 Dual TDM-Over-Packet Chip pdf datasheet.



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19-4835; 8/09
DS34T101, DS34T102, DS34T104, DS34T108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. With built-in full-
featured E1/T1 framers and LIUs. These ICs
encapsulate the TDM-over-packet solution from
analog E1/T1 signal to Ethernet MII while preserving
options to make use of TDM streams at key
intermediate points. The high level of integration
available with the DS34T10x devices minimizes cost,
board space, and time to market.
TDM Circuit Extension Over PSN
Leased-Line Services Over PSN
o
TDM Over GPON/EPON
o
TDM Over Cable
o
TDM Over Wireless
o
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
Functional Diagram
DS34T108
Octal
Circuit
E1/T1/J1
Emulation
Transceiver
Engine
Framers
E1/T1
BERT
Interfaces
& CAS
Buffer
LIUs
Manager
SDRAM
TDM
Access
Interface
________________________________________________________
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Applications
See detailed feature list in Section 7.
CPU
Bus
DS34T101GN
DS34T101GN+
DS34T102GN
10/100
Ethernet
DS34T102GN+
xMII
MAC
DS34T104GN
DS34T104GN+
Clock
Adapters
DS34T108GN
DS34T108GN+ 8
Clock Inputs
+Denotes lead(Pb)-free/RoHS-compliant package (explanation).
Full-Featured IC Includes E1/T1 LIUs and
Framers, TDMoP Engine, and 10/100 MAC
Transport of E1, T1, E3, T3 or STS-1 TDM or
Other CBR Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP AAL1, HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
Ordering Information
PART
PORTS TEMP RANGE PIN-PACKAGE
1
-40C to +85C 484 TEBGA
1
-40C to +85C 484 TEBGA
2
-40C to +85C 484 TEBGA
2
-40C to +85C 484 TEBGA
4
-40C to +85C 484 TEBGA
4
-40C to +85C 484 TEBGA
8
-40C to +85C 484 HSBGA
-40C to +85C 484 HSBGA
Maxim Integrated Products
Features
1

Summary of Contents

Page 1

... DS34T101, DS34T102, DS34T104, DS34T108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1 serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications ...

Page 2

... DS34T101, DS34T102, DS34T104, DS34T108 1 INTRODUCTION ...10 2 ACRONYMS AND GLOSSARY...10 3 APPLICABLE STANDARDS ...13 4 DETAILED DESCRIPTION ...14 5 APPLICATION EXAMPLES ...16 6 BLOCK DIAGRAM...18 7 FEATURES ...20 8 OVERVIEW OF MAJOR OPERATIONAL MODES ...25 8 ...25 NTERNAL ODE 8.1.1 Internal One-Clock Mode... 26 8.1.2 Internal Two-Clock Mode... 26 8 ...27 ...

Page 3

... DS34T101, DS34T102, DS34T104, DS34T108 10.9.1 TDMoP Interrupts ... 104 10.9.2 LIU, Framer and BERT Interrupts ... 106 10. LASTIC TORES AND 10.10.1 Elastic Store Initialization... 108 10.10.2 Minimum Delay Mode... 109 10.10.3 Additional Elastic Store Information ... 109 10.11 F ...111 RAMERS 10.11.1 T1 and E1 Framing Formats ... 111 10.11.2 T1 Transmit Frame Synchronizer... 115 10 ...

Page 4

... DS34T101, DS34T102, DS34T104, DS34T108 11.4.13 Receive SW CAS ... 206 11.4.14 Interrupt Controller... 207 11.4.15 Packet Classifier... 213 11.4.16 Ethernet MAC ... 214 11 LIU BERT R RAMER AND 11.5.1 Receive Framer Registers... 224 11.5.2 Transmit Formatter Registers... 272 11.5.3 LIU Registers... 303 11.5.4 BERT Registers... 312 12 JTAG INFORMATION...320 13 DC ELECTRICAL CHARACTERISTICS ...325 14 AC TIMING CHARACTERISTICS ...

Page 5

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ... 16 Figure 5-2. TDMoP in Cellular Backhaul ... 17 Figure 6-1. Top-Level Block Diagram ... 18 Figure 6-2. TDM Cross-Connection Block Diagram ... 19 Figure 8-1. Internal Mode Block Diagram... 25 Figure 8-2. Internal One-Clock Mode ... 26 Figure 8-3. Internal Two Clock Mode (Framed)... 27 Figure 8-4. Internal Two Clock Mode (Unframed) ... 27 Figure 10-1 ...

Page 6

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-48. Jitter Buffer Parameters ... 82 Figure 10-49. TDM-over-Packet Data Flow Diagram ... 84 Figure 10-50. Free Buffer Pool Operation ... 88 Figure 10-51. TDM-to-Ethernet Flow ... 89 Figure 10-52. Ethernet-to-TDM Flow ... 90 Figure 10-53. TDM-to-TDM Flow... 91 Figure 10-54. TDM-to-CPU Flow ... 92 Figure 10-55. CPU-to-TDM Flow ... 93 Figure 10-56. CPU-to-Ethernet Flow ... 94 Figure 10-57 ...

Page 7

... Figure 15-11. Connecting the H_READY_N Signal to the MPC860 TA Pin ... 348 Figure 15-12. Internal CPLD Logic to Synchronize H_READY_N to the MPC860 Clock ... 348 Figure 16-1. DS34T101 Pin Assignment (TE-CSBGA Package) ... 361 Figure 16-2. DS34T102 Pin Assignment (TE-CSBGA Package) ... 362 Figure 16-3. DS34T104 Pin Assignment (TE-CSBGA Package) ... 363 Figure 16-4. DS34T108 Pin Assignment (HSBGA Package)... 364 Table 3-1 ...

Page 8

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-14. IPv6 Header Fields (L2TPv3) ... 60 Table 10-15. Control Word Fields... 60 Table 10-16. RTP Header Fields ... 61 Table 10-17. VCCV OAM Payload Fields... 62 Table 10-18. UDP/IP-Specific OAM Payload Fields... 63 Table 10-19. CAS Supported Interface Connections for AAL1 and CESoPSN ... 68 Table 10-20. CAS Handler Selector Decision Logic... 69 Table 10-21 ...

Page 9

... DS34T101, DS34T102, DS34T104, DS34T108 Table 11-10. Transmit Software CAS Registers... 201 Table 11-11. Receive Line CAS Registers ... 203 Table 11-12. Clock Recovery Registers ... 204 Table 11-13. Receive SW Conditioning Octet Select Registers... 205 Table 11-14. Receive SW CAS Registers ... 206 Table 11-15. Interrupt Controller Registers ... 207 Table 11-16. Packet Classifier OAM Identification Registers... 213 Table 11-17 ...

Page 10

... DS34T101, DS34T102, DS34T104, DS34T108 1 Introduction The DS34T101/2/4/8 family of products combine E1/T1 LIUs and framers and TDM-over-packet circuit emulation circuitry into one die. Dedicated payload-type engines are included for TDMoIP (AAL1), CESoPSN, SAToP, and HDLC. Products in the DS34T10x family provide the mapping/demapping capability to enable the transport of TDM data (Nx64kbps, E1, T1, J1, E3, T3, STS-1) or other constant bit-rate data over IP, MPLS or Ethernet networks ...

Page 11

... DS34T101, DS34T102, DS34T104, DS34T108 LIU Line Interface Unit LOF Loss of Frame (i.e. loss of frame alignment) LOS Loss of Signal MAC Media Access Control MEF Metro Ethernet Forum MFA MPLS / Frame Relay Alliance (Now called IP/MPLS Forum) MII Medium Independent Interface MPLS MULTI PROTOCOL LABEL SWITCHING ...

Page 12

... DS34T101, DS34T102, DS34T104, DS34T108 Glossary BERT Bit Error Rate Tester, a function used to test the integrity of a data link. A two-block set consisting BERT that generates pseudo-random or repetitive patterns and optionally inserts bit errors into the sequence, and an Rx BERT that synchronizes to an incoming pattern and count bit errors. ...

Page 13

... DS34T101, DS34T102, DS34T104, DS34T108 3 Applicable Standards Table 3-1. Applicable Standards SPECIFICATION ANSI T1.102 Digital HierarchyElectrical Interfaces, 1993 T1.107 Digital HierarchyFormats Specification, 1995 T1.231.02 Digital HierarchyLayer 1 In-Service Digital Transmission Performance Monitoring, 2003 T1.403 Network and Customer Installation InterfacesDS1 Electrical Interface, 1999 AT& ...

Page 14

... Detailed Description The DS34T108 is an 8-port device integrating a sophisticated multiport TDM-over-Packet (TDMoP) core and eight full-featured, independent, software-configurable E1/T1 transceivers. The DS34T104, DS34T102 and DS34T101 have the same functionality as the DS34T108, except they have only ports and transceivers, respectively. Each E1/T1 transceiver is composed of a line interface unit (LIU), a framer, an elastic store, an HDLC controller and a bit error rate tester (BERT) block ...

Page 15

... DS34T101, DS34T102, DS34T104, DS34T108 MEF 8, MFA 8.0.0 and the IETF RFC 5086 (CESoPSN). It supports E1/T1/E3/T3 while taking into account the TDM structure. The level of structure must be chosen for proper payload conversion such as the framing type (i.e. frame or multiframe). This method is less sensitive to PSN impairments but lost packets could still cause service interruption ...

Page 16

... DS34T101, DS34T102, DS34T104, DS34T108 5 Application Examples In Figure 5-1, a DS34T10x device is used in each TDMoP gateway to map TDM services into a packet-switched metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, etc. Figure 5-1. TDMoP in a Metropolitan Packet Switched Network 16 of 366 ...

Page 17

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 5-2. TDMoP in Cellular Backhaul Other Possible Applications Point-to-Multipoint TDM Connectivity over IP/Ethernet The DS34T10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel Associated Signaling). There is no need for an external TDM cross-connect, since the packet domain can be used as a virtual cross-connect ...

Page 18

... DS34T101, DS34T102, DS34T104, DS34T108 6 Block Diagram Figure 6-1. Top-Level Block Diagram RESREF RCLKn (out)/RCLKFn (in) RDATFn RLOFn/RLOSn RSERn RFSYNCn/RMSYNCn RSYSCLKn RSYNCn TDMn_RCLK TDMn_RX TDMn_RX_SYNC TDMn_RSIG_RTS H_CPU_SPI_N DATA_31_16_N H_D[31:1] H_D[0] / SPI_MISO H_AD[24:1] H_CS_N H_R_W_N H_WR_BE[0]_N / SPI_CLK H_WR_BE[1]_N / SPI_MOSI H_WR_BE[2]_N / SPI_SEL_N H_WR_BE[3]_N / SPI_CI ...

Page 19

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 6-2. TDM Cross-Connection Block Diagram 1 per Port Port n shown Framer TX Interface MODE TCLKFn pin 1 Framer n TCLK 0 Clock MODE TSYSCLKn/ECLKn pin 1 Framer n TSYSCLK 0 MODE Data TSERn pin 1 Framer n TSER (Data) 0 SYNCNTLn[2:0] Framer 1 TSYNC out tsync_ref[n] Framer 8 TSYNC out ...

Page 20

... DS34T101, DS34T102, DS34T104, DS34T108 7 FEATURES Global Features TDMoP Interfaces DS34T101: 1 E1/T1 LIU/Framer/TDMoP interface o DS34T102: 2 E1/T1 LIUs/Framers/TDMoP interfaces o DS34T104: 4 E1/T1 LIUs/Framers/TDMoP interfaces o DS34T108: 8 E1/T1 LIUs/Framers/TDMoP interfaces o All four devices: optionally 1 high-speed E3/DS3/STS-1 TDMoP interface o All four devices: each interface optionally configurable for serial operation for V.35 and RS530 o  ...

Page 21

... DS34T101, DS34T102, DS34T104, DS34T108 T1 DSX-1 line build-outs T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75 coax and 120 twisted-pair cables Several local and remote loopback options including simultaneous local and remote  ...

Page 22

... Frame Relay), according to IETF RFC 4618. TDMoP TDM Interfaces Supports single high-speed E3 STS-1 interface on port 1 or one (DS34T101), two (DS34T102), four (DS34T104) or eight (DS34T108) E1 serial interfaces For single high-speed E3 STS-1 interface, AAL1 or SAToP payload type is used  ...

Page 23

... DS34T101, DS34T102, DS34T104, DS34T108 Each bundle carries a data stream from one TDM interface over IP/MPLS/Ethernet PSN from TDMoP source device to TDMoP destination device Each bundle may be for N x 64kbps, an entire E1, T1, E3 STS- arbitrary serial data stream  ...

Page 24

... DS34T101, DS34T102, DS34T104, DS34T108 Test and Diagnostics IEEE 1149.1 JTAG support Per-channel programmable on-chip bit error-rate testing (BERT) Pseudorandom patterns including QRSS User-defined repetitive patterns Error insertion single and continuous Total-bit and errored-bit counts  ...

Page 25

... DS34T101, DS34T102, DS34T104, DS34T108 8 Overview of Major Operational Modes 8.1 Internal Mode The default mode of the device is internal one-clock mode. Internal mode is used to internally connect the framers to the TDMoP block. Internal mode additionally configures many unused TDM interface output pins to drive low. ...

Page 26

... DS34T101, DS34T102, DS34T104, DS34T108 8.1.1 Internal One-Clock Mode In internal one-clock mode (GCR1.CLKMODE0) the receive direction of each TDM port uses the same clock as the transmit direction of that port. The transmit formatter and the receive framer are therefore synchronized together. Since the data received from the LIU receiver or the clock recovered by the LIU or the difference between clock frequencies is handled by control slips in the elastic store ...

Page 27

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 8-3. Internal Two Clock Mode (Framed) Framer port n Connected to LIU TCLKOn TPOSn TNEGn RCLKn RCLKn RPOSn RF/MSYNCn RNEGn Figure 8-4. Internal Two Clock Mode (Unframed) Framer port n Connected to LIU TCLKOn TPOSn TNEGn RCLKn RCLKn RPOSn RNEGn 8.2 External Mode External mode activates all the port interface pins for applications where the connections between the framer and the TDMoP block must be custom-wired externally ...

Page 28

... DS34T101, DS34T102, DS34T104, DS34T108 9 PIN DESCRIPTIONS 9.1 Short Pin Descriptions Table 9-1. Short Pin Descriptions (1) TYPE PIN NAME Internal E1/T1 LIU Line Interface TXENABLE TTIPn, TRINGn RTIPn, RRINGn RXTSEL RESREF External E1/T1 LIU Interface TCLKOn TDATFn RCLKFn / RCLKn RDATFn Framer TDM Interface TCLKFn TSYSCLKn ...

Page 29

... DS34T101, DS34T102, DS34T104, DS34T108 (1) PIN NAME TYPE CLK_MII_RX MII_RXD[3:0] MII_RX_DV MII_RX_ERR MII_COL MII_CRS MDC MDIO IOpu Global Clocks CLK_SYS_S CLK_SYS CLK_CMN CLK_HIGH MCLK CPU Interface H_CPU_SPI_N DAT_32_16_N H_D[31:1] H_D[0] / SPI_MISO H_AD[24:1] H_CS_N H_R_W_N / SPI_CP H_WR_BE0_N / SPI_CLK H_WR_BE1_N / SPI_MOSI H_WR_BE2_N / SPI_SEL_N ...

Page 30

... DS34T101, DS34T102, DS34T104, DS34T108 Note 1: In pin names, the suffix n stands for port number: n for DS34T108; n for DS34T104; n2 for DS34T102; n1 for DS34T101. All pin names ending in _N are active low. Note 2: All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description. ...

Page 31

... DS34T101, DS34T102, DS34T104, DS34T108 Table 9-3. External E1/T1 LIU Line Interface Pins (1) (2) PIN NAME TYPE PIN DESCRIPTION TCLKOn O Transmit Clock Output 8mA TCLKOn: This signal is normally synchronous with TCLKFn. However, when framer loopback or payload loopback is enabled (RCR3.FLB1, PLB1) it becomes synchronous with RCLKFn/RCLKn. When the internal LIU is disabled (GCR2 ...

Page 32

... DS34T101, DS34T102, DS34T104, DS34T108 Table 9-4. Framer TDM Interface Pins (1) (2) PIN NAME TYPE PIN DESCRIPTION TCLKFn I Transmit Clock Input to Formatter This pin is only active in external mode (GCR1.MODE1). In this mode, TCLKFn is the 1.544MHz or 2.048MHz clock that clocks the transmit formatter. When the transmit elastic store is disabled (TESCR ...

Page 33

... DS34T101, DS34T102, DS34T104, DS34T108 (1) (2) PIN NAME TYPE PIN DESCRIPTION RSYSCLKn I Receive System Clock Input This pin is only active in external mode (GCR1.MODE1). When the receive elastic store is enabled (RESCR.RESE1), RSERn, RFSYNCn/ RSYNCn cross-connect side) of the receive elastic store on the rising edge of RSYSCLKn. ...

Page 34

... DS34T101, DS34T102, DS34T104, DS34T108 (1) (2) PIN NAME TYPE PIN DESCRIPTION the cross-connect side) side of the elastic store mode, RIOCR.RSMS2 specifies whether RMSYNCn pulses on CAS (0) or CRC-4 (1) multiframe boundaries. RLOFn/RLOSn O GCR1.LOSS0 configures this pin to be RLOFn while LOSS1 configures 8mA RLOSn ...

Page 35

... DS34T101, DS34T102, DS34T104, DS34T108 (1) (2) PIN NAME TYPE PIN DESCRIPTION positive integer (example: if N16, it pulses every 2ms). Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0). This pin is only active in external mode (GCR1.MODE1). See the timing diagrams in TDMn_TX_MF_CD IOpd TDMoP Transmit Multiframe Sync Input When the interface type is configured for E1 or T1, multiframe sync is provided to the TDMoP engine from this pin ...

Page 36

... DS34T101, DS34T102, DS34T104, DS34T108 (1) (2) PIN NAME TYPE PIN DESCRIPTION present on the positive integer (example: if N16, it pulses every 2ms). In one-clock mode, this signal is ignored and alignment for both the transmit and receive interfaces of the TDMoP engine. Port[n]_cfg_reg.Two_clocks specifies two-clock mode (1) or one-clock mode (0). ...

Page 37

... DS34T101, DS34T102, DS34T104, DS34T108 Table 9-7. Ethernet PHY Interface Pins (MII/RMII/SSMII) The PHY interface type is configured by General_cfg_reg0.MII_mode_select[1:0]. 00MII, 01Reduced MII (RMII), 11Source Synchronous Serial MII (SSMII). The MII interface is described in IEEE 802.3-2005 Section 22. The RMII interface is described in this document: http://www.national.com/appinfo/networks/files/rmii_1_2.pdf. The Source Synchronous Serial MII is described in this document: ftp://ftp-eng ...

Page 38

... DS34T101, DS34T102, DS34T104, DS34T108 (1) (2) PIN NAME TYPE PIN DESCRIPTION MII_RXD[3:0] I MII Receive Data Inputs In MII mode, receive data comes from the PHY four bits at a time on MII_RXD[3:0], on the rising edge of CLK_MII_RX. See the timing diagram in In RMII mode, receive data comes from the PHY two bits at a time on MII_RXD[3:2] and is latched on the rising edge of CLK_MII_TX ...

Page 39

... DS34T101, DS34T102, DS34T104, DS34T108 Table 9-8. Global Clock Pins (1) (2) PIN NAME TYPE PIN DESCRIPTION CLK_SYS_S Ipd System Clock Selection Input This pin specifies the frequency of the clock applied to the section 10. MHz MHz CLK_SYS I System Clock Input A 25 MHz, 50 MHz or 75 MHz clock (50 ppm or better) must be applied to this pin to clock TDM-over-Packet internal circuitry and the SDRAM interface (SD_CLK) ...

Page 40

... DS34T101, DS34T102, DS34T104, DS34T108 Table 9-9. CPU Interface Pins See the parallel interface timing diagrams in (1) (2) PIN NAME TYPE PIN DESCRIPTION H_CPU_SPI_N Ipu Host Bus Interface 0 SPI serial interface 1 Parallel interface DAT_32_16_N Ipu Data Bus Width 0 16-bit 1 32-bit In SPI bus mode this pin is ignored. ...

Page 41

... DS34T101, DS34T102, DS34T104, DS34T108 (1) (2) PIN NAME TYPE PIN DESCRIPTION H_WR_BE2_N / I H_WR_BE2_N: Host Write Enable Byte 2 (Active Low) SPI_SEL_N In 32-bit parallel interface mode during a write access this pin specifies whether or not byte 2 (H_D[15:8]) should be written to the device. In 16-bit parallel interface mode this pin is ignored and should be pulled high or low ...

Page 42

... DS34T101, DS34T102, DS34T104, DS34T108 Table 9-10. JTAG Interface Pins See the JTAG interface timing diagram in (1) (2) PIN NAME TYPE PIN DESCRIPTION JTRST_N Ipu JTAG Test Reset (Active Low) This signal is used to asynchronously reset the test access port controller. After power up, JTRST_N must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode ...

Page 43

... DS34T101, DS34T102, DS34T104, DS34T108 Table 9-12. Power and Ground Pins (1) (2) PIN NAME TYPE PIN DESCRIPTION DVDDC P 1.8V Core Voltage for Framers and TDM-over-Packet Digital Logic (17 pins) DVDDIO P 3.3V for I/O Pins (16 pins) DVSS P Ground for Framers, TDM-over-Packet and I/O Pins (31 pins) DVDDLIU P 3.3V for LIU Digital Logic (2 pins) ...

Page 44

... DS34T101, DS34T102, DS34T104, DS34T108 10 Functional Description 10.1 Power-Supply Considerations Due to the dual-power-supply nature of the device, some I/Os have parasitic diodes between a 1.8V supply and a 3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes because it could cause latchup. Two methods are available to prevent this. The first method is to place a Schottky diode external to the device between the 1.8V supply and the 3.3V supply to force the 3.3V supply to be within one parasitic diode drop below the 1.8V supply (i.e. VDD3.3 > ...

Page 45

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-1. CPU Data Bus Widths DAT_32_16_N Data Bus Value Width 1 32 bits 0 16 bits Burst accesses are not supported. The device uses the big-endian byte order, as explained in section 11.1. The CPU starts an access to the device by asserting the read/write state on H_R_W_N, address on H_AD[24:1], write byte enables on the (for a write access) on the H_D[31:0] pins ...

Page 46

... DS34T101, DS34T102, DS34T104, DS34T108 The write access to the SDRAM is different than the write access to the chip. The SDRAM can be written with byte resolution using the four byte write enables. In contrast, internal chip resources are always written at full CPU data bus width (32 bits in Figure 10-2) ...

Page 47

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-5. Write Access to the SDRAM, 16-Bit Bus DAT_32_16_N[0] H_CS_N[0] H_AD[24:1] H_R_W_N[0] H_READY_N[0] [0] H_D[15:8] H_D[7:0] H_WR_BE1_N[0] H_WR_BE0_N[0] In 16-bit bus mode, read accesses to SDRAM are always 16 bits Figure 10-6. Read Access to the SDRAM, 16-Bit Bus DAT_32_16_N[0] H_CS_N[0] H_AD[24:1] ...

Page 48

... DS34T101, DS34T102, DS34T104, DS34T108 SPI_MISO is master data input, slave data output. SPI_SEL_N is the slave chip select. The master initiates a data transfer by asserting accompanied by serial data on SPI_MOSI. During read cycles the slave outputs data on SPI_MISO. Each additional slave requires an additional slave chip-select wire. ...

Page 49

... DS34T101, DS34T102, DS34T104, DS34T108 10.3.3 SPI Signals In SPI mode, the following CPU bus pins change their functionality and operate as SPI signals. Inputs SPI_CLK is shared with o SPI_MOSI is shared with o SPI_SEL_N is shared with H_WR_BE2_N. o Outputs SPI_MISO is shared with H_D[0]. o The SPI configuration is supplied on two external pins as follows:  ...

Page 50

... DS34T101, DS34T102, DS34T104, DS34T108 signals in CPU bus mode (including being active low). At the same time, the slave transmits the byte enable values of the previous access on SPI_MISO. The next bit on SPI_MOSI The next 24 bits the master transmits on with A1 (LSB). At the same time, the slave transmits the address bits of the previous access on SPI_MISO. ...

Page 51

... DS34T101, DS34T102, DS34T104, DS34T108 signals in CPU bus mode (including being active low). For a read access, all four of these bits should the same time, the slave transmits the byte enable values of the previous access on SPI_MISO. The next bit on SPI_MOSI  ...

Page 52

... DS34T101, DS34T102, DS34T104, DS34T108 The first bit on SPI_MOSI The master then transmits two opcode bits on SPI_MOSI. These bits specify a read, write or status command. The value 00b represents a status command. At the same time, the slave transmits the opcode bits of the previous command on SPI_MISO. ...

Page 53

... DS34T101, DS34T102, DS34T104, DS34T108 In addition to producing 38.88 MHz for the adaptive clock recovery machines, CLAD1 also make E1 and T1 master clocks for the LIUs and Framers. CLAD1 can make these E1 and T1 master clocks from the available. This is not affected by the state of the GCR1.CLK_HIGHD bit clock is not applied to the pin because clock recovery is disabled, CLAD1 must have a 2 ...

Page 54

... DS34T101, DS34T102, DS34T104, DS34T108 RESET FUNCTION HDLC Receive Reset HDLC Transmit Reset Elastic Store Receive Reset Elastic Store Transmit Reset Bit Oriented Code Receive Reset Loop Code Integration Reset Spare Code Integration Reset The device has several features included to reduce power consumption. The individual LIU transmitters can be powered down by setting the TPDE bit in the LIU maintenance control register (LMCR) ...

Page 55

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-10. TDM-over-Packet Encapsulation Formats Table 10-6. Ethernet Frame Fields Field Preamble A sequence of 56 bits (alternating 1 and 0 values) Gives components in the network time to detect the presence of a signal and synchronize to the incoming bit stream. Start of Frame A sequence of 8 bits (10101011) that indicates the start of the frame. ...

Page 56

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.1.1 VLAN Tag As specified in IEEE Standard 802.1q, the twelve-bit VLAN identifiers enable the construction of a maximum of 4,096 distinct VLANs. For cases where this VLAN limit is inadequate VLAN stacking provides a two-level VLAN tag structure, which extends the VLAN ID space to over 16 million VLANs. Each packet may be sent without VLAN tags, with a single VLAN tag or with two VLAN tags (VLAN stacking) ...

Page 57

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-7. IPv4 Header Fields (UDP) Field IPVER IP version number. IPv4 IPVER4 IHL Length in 32-bit words of the IP header, IHL5 IP TOS IP type of service Total Length Length in octets of IP header and data Identification IP fragmentation identification Flags IP control flags; must be set to 010 to avoid fragmentation Fragment Offset Indicates where in the datagram the fragment belongs ...

Page 58

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-9. IPv6 Header Fields (UDP) Field IPVER IP version number, for IPv6 IPVER 6 Traffic Class An 8-bit field similar to the type of service (ToS) field in IPv4. Flow Label The 20-bit Flow Label field can be used to tag packets of a specific flow to differentiate the packets at the network layer ...

Page 59

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.1.6 L2TPv3/IPv4 Header Figure 10-17. L2TPv3/IPv4 Header Format Table 10-12. IPv4 Header Fields (L2TPv3) Field IPVER IHL IP TOS Total Length See Table Identification Flags Fragment Offset Time To Live Protocol Must be set to 0x73 to signify L2TPv3 IP Header Checksum Source IP Address See ...

Page 60

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.1.7 L2TPv3/IPv6 Header Figure 10-18. L2TPv3/IPv6 Header Format Table 10-14. IPv6 Header Fields (L2TPv3) Field IPVER Traffic Class See Table 10-9. Flow Label Payload Length Next Header Must be set to 0x73 to signify LTPv3 Hop Limit See Table 10-9. Source Address Destination Address 10 ...

Page 61

... DS34T101, DS34T102, DS34T104, DS34T108 Field there is a failure of that direction of the bi-directional connection. This indication can be used to signal congestion or other network related faults. Receiving remote failure indication may trigger fall-back mechanisms for congestion avoidance. The R bit must be set after a preconfigured number of consecutive packets are not received, and must be cleared once packets are once again received ...

Page 62

... DS34T101, DS34T102, DS34T104, DS34T108 Field SSRC Identifies the synchronization source. This identifier should be chosen randomly, with the intent that no two synchronization sources within the same RTP session have the same SSRC identifier. 10.6.1.10 TDM-over-Packet Payload This field can contain the following payload types:  ...

Page 63

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-22. UDP/IP-Specific OAM Packet Format Table 10-18. UDP/IP-Specific OAM Payload Fields Field Identical to those of the bundle being tested Length OAM message packet length (in bytes) OAM Sequence Number Uniquely identifies the message. Its value is unrelated to the sequence number of the TDM data packets for the bundle in question ...

Page 64

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-23. TDM Connectivity over a PSN Figure 10-24. TDMoP Packet Format in a Typical Application DA SA VLAN Tag 1 Optional DA SA VLAN Tag 2 Optional DA SA VLAN Tag 3 Optional DA SA VLAN Tag 4 Optional Figure 10-25. TDMoMPLS Packet Format in a Typical Application DA SA VLAN Tag ...

Page 65

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.3 Clock Recovery The TDM-over-Packet blocks innovative clock recovery process is divided into two successive phases. In the acquisition phase, rapid frequency lock is attained. In the tracking phase, frequency lock is sustained and phase is also tracked. During the tracking phase, jitter is attenuated to comply with the relevant telecom standards even for packet-switched networks with relatively large packet delay variation ...

Page 66

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.4 Timeslot Assigner (TSA) The TDM-over-Packet block contains one Timeslot Assigner for each E1/T1 port (framed or multiframed) using a PCM interface. The TSA is bypassed in high-speed mode (i.e. when High_speed1 in TSA tables are described in section 11.4.5. The TSA assigns 2 8-bit wide timeslots to a specific bundle and a specific receive queue. 2-bit timeslots are used for delivering 16K HDLC channels ...

Page 67

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.5 CAS Handler 10.6.5.1 CAS Handler, TDM-to-Ethernet Direction In the TDM-to-Ethernet direction, the CAS handler receives the CAS bits (for structured-with-CAS AAL1 or CESoPSN bundles) on the TDMn_RSIG_RTS signal. Depending on the value of the per-bundle configuration bit in the Bundle Configuration corresponding TDMn_RSIG_RTS signal or the values from the transmit SW CAS tables (section 11 ...

Page 68

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces 31 ABCD ABCD (TS7) (TS6) ABCD .. (TS15) ABCD .. (TS23) ABCD .. (TS31) Figure 10-28. Transmit SW CAS Table Format for T1-SF Interfaces 31 ABAB ABAB (TS7) (TS6) ABAB .. (TS15) ABAB .. (TS23) Table 10-19. CAS Supported Interface Connections for AAL1 and CESoPSN ...

Page 69

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks0) TDMn_TCLK TDMn_RX_SYNC TDMn_RSIG Figure 10-31 Interface RSIG (two_clocks0) Timing Diagram TDMn_TCLK TDMn_RX_SYNC TDMn_RSIG TDMn_RX_SYNC can be left unconnected or connected to ground if the framer cannot drive it. The TDMoP block has an internal free running counter that generates this signal internally when not driven by an external source. ...

Page 70

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-32. CAS Transmitted in the Ethernet-to-TDM Direction R The Receive SW CAS tables contain CAS bits written by CPU software. Each ports Receive Line CAS table (section 11.4.10) is updated with the CAS bits stored in the Receive Line (Next MF) CAS table when the TDMn_TX_MF_CD signal is asserted to indicate the multiframe boundary. For E1 ports, CAS bits are updated every 2 milliseconds ...

Page 71

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-33 Interface TSIG Timing Diagram TDMn_TCLK TDMn_TX_MF_CD TDMn_TSIG Figure 10-34. T1 ESF Interface TSIG Timing Diagram TDMn_TCLK TDMn_TX_MF_CD TDMn_TSIG Figure 10-35 Interface TSIG Timing Diagram TDMn_TCLK TDMn_TX_MF_CD TDMn_TSIG TDMn_TX_MF_CD can be left unconnected or connected to ground if the framer cannot drive it. The TDMoP block has an internal free running counter that generates this signal internally when not driven by external source ...

Page 72

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-36. AAL1 Mapping, General The structure of the AAL1 header is shown in Table 10-21. AAL1 Header Fields Length Field Description (bits Indicates if there is a pointer in the second octet of the AAL1 SAR PDU. When set, a pointer exists AAL1 SAR PDU sequence number ...

Page 73

... DS34T101, DS34T102, DS34T104, DS34T108 SAR PDU payload contains 47 octets (376 bits) of TDM data without regard to frame alignment or timeslot byte alignment. All AAL1 SAR PDUs are non-P format for unstructured bundles. Structured-without-CAS bundles, for E1/T1 interfaces, support rates of N 64 kbps, where N is the number of timeslots configured to be assigned to a bundle ...

Page 74

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.7 HDLC Payload Type Machine Handling HDLC in TDM-over-Packet ensures efficient transport of CCS (common channel signaling, such as SS7), embedded in the TDM stream or other HDLC-based traffic, such as Frame Relay, according to IETF RFC 4618 (excluding clause 5.3 PPP) and RFC 5087 (TDMoIP). ...

Page 75

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.8 RAW Payload Type Machine The RAW payload type machine support the following bundle types: Unstructured According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553 (SAToP). Structured without CAS According to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086 (CESoPSN). ...

Page 76

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-40. CESoPSN Structured-Without-CAS Mapping The packetization delay of a CESoPSN structured-without-CAS bundle is 125 s (i. the frame rate) The minimum packetization time of an Ethernet packet for a structured (with or without CAS) bundle is 125 s. 10.6.8.3 Structured with CAS (without Fragmentation structured-with-CAS bundle, the packet payload is comprised of the assigned timeslots from all the TDM frames in a multiframe (e ...

Page 77

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-42. CESoPSN Structured-With-CAS Mapping (No Frag, T1-ESF Example SF, the multiframe structure is composed of 2 superframes resulting total of 24 TDM frames. The CAS info at the end of the structure contains the CAS info of the 2 corresponding superframes as well. Figure 10-43. CESoPSN Structured-With-CAS Mapping (No Frag, T1-SF Example) ...

Page 78

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-44. CESoPSN Structured-With-CAS Mapping (Frag, E1 Example) L2/L3 Control Header Word FRG bits 01 Frame (first fragment) L2/L3 Control Header Word FRG bits 11 Frame (intermediate fragment L2/L3 Control Header Word FRG bits 10 Frame (last fragment Frame 1 ...

Page 79

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.9 SDRAM and SDRAM Controller The device requires an external SDRAM for its operation. The following describes how the TDMoP block and the CPU use the SDRAM: The TDMoP block accesses these sections of the SDRAM: Transmit buffers section This area stores outgoing packets created by the payload-type machines ...

Page 80

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-45. SDRAM Access through the SDRAM Controller TDMoPacket 10.6.10 Jitter Buffer Control (JBC) 10.6.10.1 Jitter Buffer Application Routinely in TDM networks, destination TDM devices derive a clock from the incoming TDM signal and use it for transmitting data as depicted in Figure Figure 10-46. Loop Timing in TDM Networks ...

Page 81

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-47. Timing in TDM-over-Packet The jitter buffer, located in the SDRAM, has two main roles: Compensate for packet delay variation Provide fill level information as the independent variable used by the clock recovery machines to reconstruct the TDM clock on a slave TDMoP device. ...

Page 82

... DS34T101, DS34T102, DS34T104, DS34T108 For T1 structured-with-CAS, multiply the above formula by 0.75. The jitter buffer depth is defined by the When the jitter buffer level reaches the value of Rx_max_buff_size, an overrun situation is declared. The Rx_PDVT parameter (also found in the in the jitter buffer to compensate for network delay variation. This parameter has two implications:  ...

Page 83

... DS34T101, DS34T102, DS34T104, DS34T108 For AAL1/HDLC/RAW structured bundles: the timeslot in the bundle. For example, if the bundle consists of timeslots port 3, Jitter_buffer_index0x2. For unstructured bundles the 10.6.10.3 Jitter Buffer Status and Statistics The CPU accesses the Jitter Buffer Status Table contains the current jitter buffer status (such as, the current jitter buffer level and its current state (OK, underrun or overrun) ...

Page 84

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-49. TDM-over-Packet Data Flow Diagram 10.6.11.1 Buffer Descriptor Data is transferred between the Ethernet MAC, internal payload-type machines and the external CPU by means of buffers in the SDRAM. Payload data is stored SDRAM buffers along with a buffer descriptor located in the buffer’ ...

Page 85

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.2 Buffer Descriptor First Dword Used for all paths. Located at offset 0x0 from the start of the buffer. Table 10-24. Buffer Descriptor First Dword Fields (Used for all Paths) Bits Data Element [31] MPLS/MEF/L2TIPV3 or UDP/IP-specific OAM [30] RST [29:27] Buffer contents ...

Page 86

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.3 Buffer Descriptor Second Dword Located at offset 0x4 from the start of the buffer. 10.6.11.3.1 TDM ETH and CPU ETH Packets Table 10-25. Buffer Descriptor Second Dword Fields (TDM ETH and CPU ETH) Bits Data Element ...

Page 87

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.4 Buffer Descriptor Third Dword Used for ETH CPU packets. Located at offset 0x8 from start of the buffer. Table 10-27. Buffer Descriptor Third Dword Fields (ETH CPU) Bits Data Element 31:0 Timestamp 10.6.11.5 RX Arbiter The RX arbiter constantly checks for available packets in the Rx FIFO, the CPU-to-TDM queue and the cross- connect queue. It can do one of the following:  ...

Page 88

... DS34T101, DS34T102, DS34T104, DS34T108 The CPU must define the number of buffers for each bundle by initializing the linked list for the bundle. Software prepares these buffers by writing the Ethernet, IP/MPLS/L2TPv3/MEF headers in advance, so that the payload- type machines need only to write the packet payload. Since the headers contain bundle-specific data (e.g., destination address), the same buffers are used for the same bundle until the bundle is closed by CPU software ...

Page 89

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.8 TDM to Ethernet Flow Each payload-type machine receives the data of specific bundle timeslots and maps it into packets. To store a new packet in preparation, the machine extracts a pointer from the free buffer pool (section 10.6.11.7) and fills the associated buffer with TDM timeslot data, one by one. When a packet is completed in a buffer, the payload-type machine places the buffer pointer in the Ethernet Tx queue ...

Page 90

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.9 Ethernet to TDM Flow A packet arriving from the Ethernet port passes through the Ethernet MAC block. The MAC block does not store the packet, but it does calculate the CRC to verify packet data integrity. If the packet is bad, the MAC signals this to the packet classifier on the last word of the packet, and the packet classifier discards it ...

Page 91

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.10 TDM to TDM (Cross-Connect) Flow Each payload-type machine receives the data of bundle-specific TDM timeslots and maps the data into Ethernet packets. To store a packet, the payload-type machine needs an SDRAM buffer which it gets by extracting a buffer pointer from the free buffer pool. It then fills the buffer as it processes the TDM timeslots. When a packet is completed in a buffer, the machine places the buffer pointer in the cross-connect queue ...

Page 92

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.11 TDM to CPU Flow The payload-type machines identify the destination of their packets according to the per-bundle configuration. Upon getting the first byte of a packet in a bundle destined to the CPU, the machine needs a buffer to store the packet. It therefore checks whether a buffer is available in the TDM-to-CPU pool. If the pool is empty, the machine discards the current data ...

Page 93

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.12 CPU to TDM Flow The Rx arbiter polls the CPU-to-TDM queue for new packets waiting in the SDRAM to be processed. If the queue level is greater than zero and there are no buffers pending in the Rx FIFO or the cross-connect queue, the Rx arbiter extracts the pointer and copies the relevant data from the SDRAM buffer to the appropriate payload-type machine ...

Page 94

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.13 CPU to Ethernet Flow The Tx Ethernet interface polls the CPU-to-Ethernet queue for new packets waiting in the SDRAM to be processed. If the queue level is greater than zero and no buffers from the payload-type machines are waiting in the Ethernet Tx queue, the Tx Ethernet interface extracts the pointer and copies the relevant data from the SDRAM buffer to the Ethernet MAC block ...

Page 95

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.11.14 Ethernet to CPU Flow Ethernet packets enter the chip via the Ethernet MAC block and the packet classifier into the Rx arbiter. When the Rx arbiter identifies that a packet is destined to the CPU, it extracts a pointer from the Ethernet-to-CPU pool (if the pool is empty, the Rx arbiter discards the packet) and stores the packet data into the SDRAM in the buffer indicated by the pointer ...

Page 96

... DS34T101, DS34T102, DS34T104, DS34T108 In half-duplex mode the start of transmission is deferred if becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random back off. MII_CRS and MII_COL Figure 10-58. Ethernet MAC TDMoPacket TX ETHERNET MII_CRS have no effect in full-duplex mode. INTERFACE ETHERNET ...

Page 97

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.12.2 Pause Packet Support Ethernet transmission pause in response to a received pause packet is enabled when Pause_enable1 in the M AC_network_configuration register. 2 When a valid pause packet is received, the regardless of its current contents and regardless of the state of Rxd interrupt in the MAC_interrupt_status If Pause_enable1 and the value of the ...

Page 98

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.13 Packet Classifier The Packet Classifier is part of the receive path, immediately following the Ethernet MAC block. It analyzes the header of each incoming packet, by comparing the header fields to the chips configured parameters, and then decides whether to discard the packet or add a buffer descriptor and forward the packet to the CPU or one of the payload-type machines ...

Page 99

... DS34T101, DS34T102, DS34T104, DS34T108 assigned to the chips internal bundles, is discarded if Discard_Switch_6 is set. Otherwise it is transferred to the CPU. Discard_Switch_7: A packet recognized as OAM packet (see section 10.6.13.3) is discarded if Discard_Switch_7 is set. Otherwise it is transferred to the CPU. Discard_Switch_8: A packet with Ethertype equal to when Discard_Switch_8 is set. Otherwise it is transferred to the CPU. ...

Page 100

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.13.1 TDMoIP Port Number The TDMoIP_port_num1 and TDMoIP_port_num2 TDMoIP packets. Although the chip has two of these fields, in most cases both fields should have the default value (0x085E) as assigned by IANA for TDM-over-Packet. The UDP source Both values are compared against the UDP_SRC_PORT_NUM or the UDP_DST_PORT_NUM of incoming ...

Page 101

... DS34T101, DS34T102, DS34T104, DS34T108 10.6.13.5 Known Ethertypes The block considers the following Ethertypes as known Ethertypes: IPv4 (0x800) IPv6 (0x86DD) MPLS unicast (0x8847) MPLS multicast (0x8848) ARP (0x806) MEF Ethertype as configured in MEF OAM Ethertype as configured in  ...

Page 102

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-62. Structure of Packets with Trailer The CRC is calculated over all packet bytes including over the trailer bytes. The transmitted bytes counter and the received bytes counter (section 11.4.3.3) do not count the trailer bytes. 10.6.15 Counters and Status Registers For information about counters and registers in the TDMoP block, see section 11 ...

Page 103

... DS34T101, DS34T102, DS34T104, DS34T108 The destination MAC/IP (and/or VLAN) of the duplicated packets can be different as the chip supports more than one MAC/IP address in the packet classifier. 10.6.17 OAM Signaling TDMoP bundles require a signaling mechanism to provide feedback regarding problems in the communications environment. In addition, such signaling can be used to collect statistics related to the performance of the underlying PSN ...

Page 104

... DS34T101, DS34T102, DS34T104, DS34T108 10.7 Global Resources See the top-level block diagram in Interface block, and the TDM Cross-Connection and External Interfaces block. These resources are configured in the global registers described in section 11.3. These registers also handle device identification, top-level mode configuration, I/O pin configuration, global resets, and top-level interrupts. ...

Page 105

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-63. Interrupt Pin Logic The TDMoP interrupts indicated in the generated by a single source. The second type consists of interrupts that can originate from any of several possible interrupt sources including the ETH_MAC, CW_bits_change, Rx_CAS_change, Tx_CAS_Change, and JB_underrun interrupts. ...

Page 106

... DS34T101, DS34T102, DS34T104, DS34T108 Interrupt Type CW_bits_change JB_underrun_Pn ETH_MAC If a bit in the Intpend register is set and that interrupt is then masked, the device generates an interrupt immediately after the CPU clears the corresponding mask bit. To avoid this behavior, the CPU should clear the interrupt from ...

Page 107

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-64. LIU, Framer and BERT Interrupt Information Flow Diagram Read corresponding LLSR register. Interrupts Allowed No Interrupt Condition Exists? Yes Read GTISR status register. What FRAMER, LIU or BERT set an interrupt condition? LIUn FRAMERn Read corresponding RIIR & TIIR Framer status register ...

Page 108

... DS34T101, DS34T102, DS34T104, DS34T108 10.10 Elastic Stores and Framer System Interface The framer and formatter provide versatile system interfaces with the following capabilities: Elastic stores can be enabled in the Tx path, the Rx path or both to support controlled slips T1 channels can be mapped/demapped to/from a 2.048MHz TDM data stream  ...

Page 109

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-33. Elastic Store Delay After Initialization INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align Note for RSZS for RSZS 1 10.10.2 Minimum Delay Mode Elastic store minimum delay mode may be used when the elastic stores system clock is frequency locked to its line clock (i ...

Page 110

... DS34T101, DS34T102, DS34T104, DS34T108 For example, if the desired configuration is to transmit channels 2-16 and 18-26 from the 2.048MHz TSER data stream, the TBCS registers should be programmed as follows: TBCS1 0x01 :: ignore TSER channel 1 :: TBCS2 0x00 TBCS3 0x01 :: ignore TSER channel 17 :: TBCS4 0xFC :: ignore TSER channels 27- ...

Page 111

... DS34T101, DS34T102, DS34T104, DS34T108 For example, if the desired configuration is to ignore E1 timeslot 0 (channel 1) and timeslot 16 (channel 17), the RBCS registers should be programmed as follows: RBCS1 0x01 :: ignore E1 channel 1 :: RBCS2 0x00 :: ignore E1 channel 17 :: RBCS3 0x01 RBCS4 0xFC :: ignore E1 channels 27-32 :: 10.11 Framers The framer cores are software selectable for E1 J1. ( variant of T1 used in Japan.) A framer, as used the term is commonly used the telecom industry and in this document, consists of two separate pieces: the receive framer and the transmit formatter. The receive side framer decodes AMI, HDB3 and B8ZS line coding ...

Page 112

... DS34T101, DS34T102, DS34T104, DS34T108 FRAME Ft NUMBER Table 10-35. T1-ESF Framing Pattern and Signaling Bits FRAME FRAMING FDL NUMBER Table 10-36. SLC-96 Framing Pattern and Signaling Bits ...

Page 113

... DS34T101, DS34T102, DS34T104, DS34T108 FRAME Ft NUMBER (concentrator bit (concentrator bit (concentrator bit (concentrator bit (concentrator bit (concentrator bit (concentrator bit (concentrator bit) ...

Page 114

... DS34T101, DS34T102, DS34T104, DS34T108 10.11.1.2 E1 Framing Formats E1 frames contain 32 8-bit channels. The first DS0 of each frame is used to carry overhead bits for frame alignment, alarm indication and node-to-node communication. The other 31 DS0 channels are available to carry voice and data. In many applications the 17 and other overhead ...

Page 115

... DS34T101, DS34T102, DS34T104, DS34T108 Register Name TCR2-E1 Transmit Control Register 2 (E1 Mode) TCR3 Transmit Control Register 3 TSLC Transmit SLC96 Control Register 1,2,3 TAF Transmit Align Frame TNAF Transmit Non-Align Frame RMMR Receive Master Mode Register RCR1-T1 Receive Control Register 1 (T1 Mode) ...

Page 116

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-40. Registers Related to Signaling Register Name TS1 - TS16 Tx Signaling Registers TSSIE1 - TSSIE4 Tx Signaling Insertion Enable Registers THSCS1 - THSCS4 Tx Hardware Signaling Channel Select RSIGC Rx Signaling Control Register RSAOI1 - RSAOI3 Rx Signaling All-Ones Insertion Registers ...

Page 117

... DS34T101, DS34T102, DS34T104, DS34T108 10.11.3.1.2 Hardware Signaling In the hardware signaling method, signaling data is provided to the transmit formatter using the TSIG input. The signaling information on TSIG is buffered and inserted into the outgoing framed signal. In both T1 and E1 modes, signaling data can be sourced from TSIG on a per-channel basis by using the ...

Page 118

... DS34T101, DS34T102, DS34T104, DS34T108 10.11.3.2.4 Receive Signaling Reinsertion at RSER In this mode, the system provides a multiframe sync at the framers RSYNC input, and the signaling data is reinserted based on this alignment mode, this results in two versions of the signaling data: the original signaling data based on the Fs/ESF frame positions, and the realigned data based on the system-supplied multiframe sync applied at RSYNC ...

Page 119

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-43. Registers Related to T1 Receive BOC Register Name RBOCC Receive BOC Control Register RBOC Receive Bit Oriented Code Register RLS7-T1 Receive Latched Status Register 7 RIM7-T1 Receive Interrupt Mask Register ESF mode, the receive framer continuously monitors the FDL bits for a valid BOC message. The BOC detect status bit RLS7-T1 ...

Page 120

... DS34T101, DS34T102, DS34T104, DS34T108 in RIM7-T1. The CPU has 2ms ( 125s) to read the data from no zero stuffing is applied to the FDL data strongly suggested that the HDLC controller be used for FDL messaging applications. In the SF framing mode, the framer writes the received Fs framing pattern into the lower six bits of the register, and RLS7-T1.RFDLF is set every 1.5ms (12 125 ...

Page 121

... DS34T101, DS34T102, DS34T104, DS34T108 10.11.5.3 Sa Bit Monitoring and Reporting In addition to the registers outlined above, the framer provides status and interrupt capability in order to detect changes in the state of selected Sa bits. The for a change of state. When a change of state is detected in one of the enabled Sa bit positions, the E1 ...

Page 122

... DS34T101, DS34T102, DS34T104, DS34T108 10.11.6.1 Real-Time Status, Latched Status, and Interrupt Mask Bits The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1 value ...

Page 123

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-48. E1 Alarm Criteria ALARM SET CRITERIA 255 or 2048 consecutive zeros LOS received (determined by RLS1.RLOSC) LOF Fewer than three zeros in two AIS frames (512 bits) Bit 3 of non-FAS frame set to one RAI three consecutive occasions Table 10-49. E1 LOF Sync and Resync Criteria ...

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... DS34T101, DS34T102, DS34T104, DS34T108 When automatic remote alarm (RAI) generation is enabled (TCR2-E1.ARA1), if the receive framer detects any of the following conditions then the transmit formatter automatically transmits RAI: Rx loss of signal, Rx loss of frame synchronization, Rx AIS alarm or CRC-4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC-4 is enabled) ...

Page 125

... DS34T101, DS34T102, DS34T104, DS34T108 In E1 operation, CRC-4 errors are counted and reported in the count in a one second period is 1000, this counter cannot saturate in that length of time. The counter stops counting during loss of frame at either the FAS or CRC-4 level, but it continues to count if only CAS multiframe sync is lost ...

Page 126

... DS34T101, DS34T102, DS34T104, DS34T108 Register Name TDS0M Transmit DS0 Monitor Register RDS0SEL Rx DS0 Monitor Select Register RDS0M Rx DS0 Monitor Register In the transmit direction TCM[4:0] field in RCM[4:0] field in RDS0SEL specifies the channel to be monitored. Data from the specified channel is available to be read from the ...

Page 127

... DS34T101, DS34T102, DS34T104, DS34T108 specify the 8-bit idle code for each channel and the basis. 10.11.13 Digital Milliwatt Code Generation The Rx digital milliwatt registers (RDMWE) specify which of the Rx E1/T1 channels should be overwritten with a digital milliwatt code. The digital milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E) ...

Page 128

... DS34T101, DS34T102, DS34T104, DS34T108 Table 10-57. Registers Related to T1 In-Band Loop Code Detection Register Field RIBCC Rx In-Band Code Control Register RUPCD1 Rx Up Code Definition Register 1 RUPCD2 Rx Up Code Definition Register 1 RDNCD1 Rx Down Code Definition Register 1 RDNCD2 Rx Down Code Definition Register 2 RSCC ...

Page 129

... DS34T101, DS34T102, DS34T104, DS34T108 Register Name TLS1 Transmit Latched Status Register 1 RCR2-T1 Receive Control Register 2 RSLC Receive SLC-96 Data Link Registers RLS7 Receive Latched Status Register 7 10.11.16.1 Transmit SLC96 The TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the register, the system should configure the transmit formatter as follows:  ...

Page 130

... DS34T101, DS34T102, DS34T104, DS34T108 Register Name RHPBA Rx HDLC Packet Bytes Available Register RHF Rx HDLC FIFO Register RRTS5 Rx Real-Time Status Register 5 RLS5 Rx Latched Status Register 5 RIM5 Rx Interrupt Mask 5 THC1 Transmit HDLC Control 1 THBSE Transmit HDLC Bit Suppress THC2 Transmit HDLC Control 2 ...

Page 131

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-66. Receive HDLC Servicing Example Start New Start New Message Buffer Message Buffer Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.RHR) Start New Start New Message Buffer Message Buffer Enable Interrupts RPE and RHWM ...

Page 132

... DS34T101, DS34T102, DS34T104, DS34T108 10.12.2 Transmit HDLC Controller The transmit HDLC controller is enabled when THC2.THCE1. A low-to-high transition on THC1.THR resets the transmit HDLC controller and flushes the transmit HDLC FIFO ESF mode, the transmit HDLC controller can be connected to the FDL (THC1.THMS any DS0 channel (THMS0 mode, it can be connected bit channel (THMS any DS0 channel (THMS0) ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-67. Transmit HDLC Servicing Example Loop Action Required Work Another Process Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC1.THR) Enable TLWM Interrupt and Verify TLWM Clear Read TFBA N TFBA[6:0] Push Message Byte into Tx HDLC FIFO ...

Page 134

... DS34T101, DS34T102, DS34T104, DS34T108 10.13 Line Interface Units (LIU) Each TDM port of the device has an on-chip line interface unit (LIU). The LIU contains three sections: the transmitter, which drives pulses with standards-compliant waveshapes onto the outbound cable; the receiver, which recovers clock and data from the inbound cable; and the jitter attenuator. The LIU can switch between T1 and E1 operation without changing any external components on either the transmit or Rx side ...

Page 135

... DS34T101, DS34T102, DS34T104, DS34T108 Note 6: The 1F capacitor in series with TTIPn is only necessary in G.703 2048kHz mode (LTISR.TXG7031). Note 7: The 560pF on TTIPn/TRINGn must be tuned for your application. Note 8: Resistor R is not necessary if receiver termination is internal. See LRISMR.RIMPM[2:0]. T Table 10-60. Transformer Specifications Specification Turns Ratio, 3 ...

Page 136

... DS34T101, DS34T102, DS34T104, DS34T108 10.13.2 LIU Transmitter The LIU is configured for E1 or T1/J1 mode by setting the LTRCR.T1J1E1S bit appropriately. 10.13.2.1 Waveshaping The LIU transmitter uses a sequencer and a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the outbound cable. The waveforms meet the latest ANSI, ETSI, ITU and Telcordia ...

Page 137

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-69. T1/J1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -500 Figure 10-70. E1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 MAXIMUM CURVE UI -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template -400 -300 -200 -100 0 100 200 300 TIME (ns) 194ns 219ns -200 -150 -100 - TIME (ns) MINIMUM CURVE Time Amp ...

Page 138

... DS34T101, DS34T102, DS34T104, DS34T108 10.13.3 LIU Receiver The LIU is configured for E1 or T1/J1 mode by setting the LTRCR.T1J1E1S bit appropriately. 10.13.3.1 Interfacing to the Line The LIU receiver accepts incoming T1, E1 and J1 physical layer signals on the receiver is designed to be fully software-selectable for E1 without changing any external components. ...

Page 139

... DS34T101, DS34T102, DS34T104, DS34T108 incoming signal to recover clock and data. The receiver has excellent jitter tolerance as shown in Figure 10-73. Figure 10-72. Jitter Tolerance, T1 Mode 1K 100 10 1 0.1 1 Figure 10-73. Jitter Tolerance, E1 and 2048kHz Modes 1k 100 0.1 1 Normally, the clock that is output at the RCLK pin is the recovered clock from the signal on the RTIP/RRING inputs ...

Page 140

... DS34T101, DS34T102, DS34T104, DS34T108 10.13.3.6 Loss-of-Signal Detection In T1 mode, LOS is declared when no pulses are detected (i.e., when the signal level is 3dB below the Rx sensitivity level set by LRISMR.RSMS[1:0 window of 192 consecutive pulse intervals. When LOS occurs, the receiver sets the real-time LOS status bit in cause and interrupt request if enabled by LSIMR ...

Page 141

... DS34T101, DS34T102, DS34T104, DS34T108 It is acceptable to provide a gapped/bursty clock at the side. If the incoming jitter exceeds 120UI then the device sets the jitter attenuator limit trip (LLSR.JALTS). Figure 10-74. Jitter Attenuation 0dB -20dB -40dB -60dB 1 Note: Curve B applies only in T1 mode. 10.13.5 LIU Loopbacks The LIU block provides four loopback paths for diagnostic purposes: analog loopback, local loopback, remote loopback and dual loopback ...

Page 142

... DS34T101, DS34T102, DS34T104, DS34T108 10.13.5.2 Local Loopback In local loopback the AMI-, HDB3- or B8ZS-encoded transmit signal from the transmit formatter is looped back toward the Rx framer. The data is transmitted normally on recovered clock and data from the LIU receiver is ignored. This loopback is shown in Figure 10-76. Local Loopback ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-78. Dual Loopback TCLK Transmit TSER Framer RCLK Receive RSER Framer Optional Transmit Transmit Jitter Digital Analog Attenuator Optional Receive Receive Jitter Analog Digital Attenuator TTIP Line Driver TRING RTIP RRING 143 of 366 ...

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... DS34T101, DS34T102, DS34T104, DS34T108 10.14 Bit Error Rate Test Functions (BERTs) 10.14.1 BERT General Description The BERT (Bit Error Rate Tester software-programmable test-pattern generator and monitor capable of meeting most error performance monitoring requirements for digital transmission equipment used to test and stress communication links ...

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... DS34T101, DS34T102, DS34T104, DS34T108 The BERT function must be enabled and configured for each port (see the can be assigned to any combination of 64kbps channels within the E1/T1 signal using the bits in the RBPCS registers. Individual bit positions within the channels can be suppressed (i.e. not used for patterns) using ...

Page 146

... DS34T101, DS34T102, DS34T104, DS34T108 programmable (1 to 32, y < the QRSS is enabled (BPCR.QRSS1) is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. For PRBS and QRSS patterns, the feedback is forced to one if bits 1 through 31 are all zeros ...

Page 147

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 10-80. Repetitive Pattern Synchronization State Diagram 32 bits without errors Verify 10.14.4.3 Rx Pattern Monitoring Rx pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An Out Of Synchronization (BSR.OOS1) condition is declared when the synchronization state machine is not in the Sync state ...

Page 148

... DS34T101, DS34T102, DS34T104, DS34T108 10.14.5.1 Transmit Error Insertion Errors can be inserted into the generated pattern one at a time rate of one out of every programmable ( off) in the TEICR.TEIR[2:0] configuration field.. Single bit error insertion is enabled by setting TEICR.BEI and can be initiated by a zero-to-one transition of TEICR.TSEI. ...

Page 149

... DS34T101, DS34T102, DS34T104, DS34T108 11 Device Registers 11.1 Addressing Device registers and memory can be accessed either bytes at a time, as specified by configuration pin DAT_32_16_N. In the 16-bit addressing mode, addresses are multiples of 2, while in 32-bit addressing, addresses are multiples of 4. The prefix 0x indicates hexadecimal (base 16) numbering, as does the suffix h (Example: 2FFh). Addresses are always indicated in hexadecimal format. The byte order for both addressing modes is “ ...

Page 150

... DS34T101, DS34T102, DS34T104, DS34T108 Figure 11-4. Partial Data Elements ( bits long) SPI interface mode ( H_CPU_SPI_N0) always uses 32-bit addressing. See section 11.2 Top-Level Memory Map Table 11-1. Top-Level Memory Map Address Range Contents 0 7F,FFF TDM-over-Packet Registers 80,000 9F,FFF Reserved 100,000 ...

Page 151

... DS34T101, DS34T102, DS34T104, DS34T108 11.3 Global Registers Functions contained in the global registers include device ID, CLAD configuration, TDMoP to framer connections, block resets, and block interrupt status. The global register base address is 0x108,000. Table 11-2. Global Registers Addr Register Name Offset 0x00 GCR1 04 GCR2 ...

Page 152

... DS34T101, DS34T102, DS34T104, DS34T108 GCR1 (Global Control Register) 0x00 Bits Data Element Name [10] MODE [9] CLKMODE [8] CLK_HIGHD [7] MCLKS [6] MCLKE [5] GFCLE [4] LOSS [3] RFMSS [2] IPOR [1] IPI1 R/W Default R/W 0 Mode Select Specifies internal mode or external mode connections for the cross-connect side of the framers and the TDMoP block. In external mode several input and output pins are enabled per port ...

Page 153

... DS34T101, DS34T102, DS34T104, DS34T108 GCR1 (Global Control Register) 0x00 Bits Data Element Name [0] IPI0 GCR2 (Global Control Register 2) 0x04 Bits Data Element Name [31:24] Not Used [23:9] Not Used [8] BRPMU [7:0] LIUDn GTRR (Global Transceiver Reset Register) 0x08 Bits Data Element Name [31:19] Not Used ...

Page 154

... DS34T101, DS34T102, DS34T104, DS34T108 GTRR (Global Transceiver Reset Register) 0x08 Bits Data Element Name [15:8] LIRSTn [7:0] LSRSTn IDR (Identification Device Register) 0x0C Bits Data Element Name [31:16] ID[31:16] [15:4] ID[15:4] [3:0] ID[3:0] GTISR (Global Transceiver Interrupt Status Register) 0x10 Bits Data Element Name [31:25] Not used. [24] TDMoPIS [23:16] LISn ...

Page 155

... DS34T101, DS34T102, DS34T104, DS34T108 GTIMR (Global Transceiver Interrupt Mask Register) 0x14 Bits Data Element Name [31:25] Not used. [24] TDMoPIM [23:16] LIMn [15:8] BIMn [7:0] FIMn FMRTOPISM1 (Framer and TDM-over-Packet Internal Signal Manager 1) 0x18 Bits Data Element Name [31:29] SYNCNTL4 [28:24] CLKCNTL4 [23:21] SYNCNTL3 [20:16] CLKCNTL3 [15:13] SYNCNTL2 [12:8] CLKCNTL2 [7:5] SYNCNTL1 ...

Page 156

... DS34T101, DS34T102, DS34T104, DS34T108 FMRTOPISM1 (Framer and TDM-over-Packet Internal Signal Manager 1) 0x18 Bits Data Element Name [4:0] CLKCNTL1 FMRTOPISM2 (Framer and TDM-over-Packet Internal Signal Manager 2) 0x1C Bits Data Element Name [31:29] SYNCNTL8 [28:24] CLKCNTL8 [23:21] SYNCNTL7 [20:16] CLKCNTL7 [15:13] SYNCNTL6 [12:8] CLKCNTL6 [7:5] SYNCNTL5 [4:0] CLKCNTL5 R/W Default Description R/W 0x0 Clock Control, Port 1 In external mode (GCR1 ...

Page 157

... DS34T101, DS34T102, DS34T104, DS34T108 FMRTOPISM3 (Framer and TDM-over-Packet Internal Signal Manager 3) 0x20 Bits Data Element Name [31] TDMRCLKS8 [30:28] TDMI8 [27] TDMRCLKS7 [26:24] TDMI7 [23] TDMRCLKS6 [22:20] TDMI6 [19] TDMRCLKS5 [18:16] TDMI5 [15] TDMRCLKS4 [14:12] TDMI4 [11] TDMRCLKS3 [10:8] TDMI3 [7] TDMRCLKS2 [6:4] TDMI2 [3] TDMRCLKS1 [2:0] TDMI1 R/W Default Description R/W 0x0 TDMoP Rx Clock Select 8 See TDMRCLKS1 below. ...

Page 158

... DS34T101, DS34T102, DS34T104, DS34T108 FMRTOPISM4 (Framer and TDM-over-Packet Internal Signal Manager 4) 0x24 Bits Data Element Name [31] Reserved [30:28] FRMR8 [27] Reserved [27:24] FRMR7 [23] Reserved [22:20] FRMR6 [19] Reserved [18:16] FRMR5 [15] Reserved [14:12] FRMR4 [11] Reserved [10:8] FRMR3 [7] Reserved [6:4] FRMR2 [3] Reserved [2:0] FRMR1 R/W Default Description - 0x0 Must be set to zero. R/W 0x7 Framer Interface 8 See FRMR1 below ...

Page 159

... DS34T101, DS34T102, DS34T104, DS34T108 11.4 TDM-over-Packet Registers The base address for the TDMoP registers is 0x0. Table 11-3. TDMoP Memory Map Address Offset Contents 0x0,000 C onfiguration and Status Registers 3 8,000 B undle Configuration Tables 3 10,000 C ounters 3 12,000 S tatus Tables 3 18,000 T imeslot Assignment Tables 3 20,000 ...

Page 160

... DS34T101, DS34T102, DS34T104, DS34T108 11.4.1 Configuration and Status Registers The base address for the TDMoP configuration and status registers is 0x0,000. Table 11-4. TDMoP Configuration Registers Addr Register Name Offset 0x00 G eneral_cfg_reg0 eneral_cfg_reg1 3 08 General_cfg_reg2 0C Port1_cfg_reg 10 Port2_cfg_reg 14 Port3_cfg_reg 18 Port4_cfg_reg 1C Port5_cfg_reg 20 Port6_cfg_reg 24 Port7_cfg_reg ...

Page 161

... DS34T101, DS34T102, DS34T104, DS34T108 Addr Register Name Offset 110 Port2_status_reg1 114 Port2_status_reg2 118 Port3_status_reg1 11C Port3_status_reg2 120 Port4_status_reg1 124 Port4_status_reg2 128 Port5_status_reg1 12C Port6_status_reg2 130 Port6_status_reg1 134 Port6_status_reg2 138 Port7_status_reg1 13C Port7_status_reg2 140 Port8_status_reg1 144 Port8_status_reg2 11.4.1.1 TDMoP Configuration Registers General_cfg_reg0 0x00 ...

Page 162

... DS34T101, DS34T102, DS34T104, DS34T108 General_cfg_reg0 0x00 Bits Data Element Name [6:5] Fq [4:3] Col_width [2:1] CAS_latency [0] Rst_SDRAM_n General_cfg_reg1 0x04 Bits Data Element Name RTP_timestamp_generation_ [31] mode [30:24] Sw_packet_offset [23:19] Tx_payload_offset [18] Reserved [17:10] JBC_sig_base_add [9:6] Tx_buf_base_add [5] IP_version [4] Dual_stack [3] Frames_count_check_en [2] Reserved [1:0] JBC_data_base_add Reset R/W Value SDRAM clock MHz R/W 0x0 MHz ...

Page 163

... Data Element Name [31:29] Rx_HDLC_min_flags [28:24] Reserved Rx_SAToP/CESoPSN_discard_ [23:20] mask [19:0] Reserved In the Port[n]_cfg_reg description below, the index n indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. Port[n]_cfg_reg 0x08n4 Bits Data Element Name [31:30] Reserved [29:24] Unframed_int_rate [23] PCM_rate Reset R/W Value Minimum number flags between 2 adjacent HDLC frames ...

Page 164

... DS34T101, DS34T102, DS34T104, DS34T108 Port[n]_cfg_reg 0x08n4 Bits Data Element Name [22:21] Tx_defect_modifier Port_Rx_enable [20] (Rx means from Ethernet MII) [19] CTS [18] CD_en [17] CD [16] Loss [15:11] Adapt_JBC_indx [10:9] SF_to_ESF_low_CAS_bits [8] TSA_act_blk Port_Tx_enable [7] (Tx mean toward Ethernet MII) [6] Rx_sample [5] Tx_sample Reset R/W Value Used in the control word M field for packets in all bundles ...

Page 165

... DS34T101, DS34T102, DS34T104, DS34T108 Port[n]_cfg_reg 0x08n4 Bits Data Element Name [4] Two_clocks [3:2] Int_framed_type [1:0] Int_type Reset R/W Value In two-clock mode (Two-clocks1) this field specifies the TDMn_TCLK edge on which TDMn_TX_SYNC, TDMn_TX_MF_CD TDMn_TX and Rx_sample field (above) specifies the for the Rx-side signals. Inputs ...

Page 166

... DS34T101, DS34T102, DS34T104, DS34T108 Rst_reg 0x2C Bits Data Element Name [31:28] Reserved [27:24] Rst_tx_port_num [23:18] Rst_tx_internal_bundle_num [17] Rst_tx_open/close [16] Rst_tx [15:7] Reserved [6:1] Rst_rx_internal_bundle_num [0] Rst_rx Reset R/W Value - 0x0 Must be set to zero Port number associated with 0000 Port 1 0001 Port 2 0010 Port 3 R/W 0x0 0011 Port 4 0100 Port 5 0101 Port 6 ...

Page 167

... DS34T101, DS34T102, DS34T104, DS34T108 The TDM_cond_data_reg register below holds four octets to be transmitted as conditioning data in the TDM direction (i.e. toward the cross-connection block) during jitter buffer underrun. This data applies to all bundle types. TDM_cond_data_reg 0x30 Bits Data Element Name [31:24] TDM_cond_octet_a [23:16] TDM_cond_octet_b ...

Page 168

... DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg2 0x40 Bits Data Element Name Packet_classifier_cfg_reg3 0x44 Bits Data Element Name [31:29] Reserved Discard_packet_length_ [28] mismatch [27] Ip_udp_bn_loc [26:25] TDMoIP_port_num_loc [24] Discard_switch_8 [23] Discard_switch_7 [22] Discard_switch_6 [21] Discard_switch_5 [20] Discard_switch_4 [19] Discard_switch_3 [18] Discard_switch_2 [17] Discard_switch_1 Reset R/W Value Packet_classifier_cfg_reg6. Relevant only for packets received from Ethernet port. ...

Page 169

... DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg3 0x44 Bits Data Element Name [16] Discard_switch_0 [15:0] MAC_add1 Packet_classifier_cfg_reg4 0x48 Bits Data Element Name [31:16] TDMoIP_port_num2 [15:0] TDMoIP_port_num1 Packet_classifier_cfg_reg5 0x4C Bits Data Element Name [31:0] MAC_add2 Packet_classifier_cfg_reg6 0x50 Bits Data Element Name [31:16] Ip_udp_bn_mask_n [15:0] MAC_add2 Packet_classifier_cfg_reg7 0x54 Bits Data Element Name ...

Page 170

... DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg7 0x54 Bits Data Element Name [15:0] vlan_2nd_tag_identifier Packet_classifier_cfg_reg8 0x58 Bits Data Element Name [31:0] Ipv4_add3 Packet_classifier_cfg_reg9 0x5C Bits Data Element Name [31:16] Mef_ ether_type [15:0] Mef_oam_ether_type Packet_classifier_cfg_reg10 0x60 Bits Data Element Name [31:0] Ipv6_add1[127:96] Packet_classifier_cfg_reg11 0x64 Bits Data Element Name ...

Page 171

... DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg13 0x6C Bits Data Element Name [31:0] Ipv6_add1[31:0] Packet_classifier_cfg_reg14 0x70 Bits Data Element Name [31:0] Ipv6_add2[127:96] Packet_classifier_cfg_reg15 0x74 Bits Data Element Name [31:0] Ipv6_add2[95:64] Packet_classifier_cfg_reg16 0x78 Bits Data Element Name [31:0] Ipv6_add2[63:32] Packet_classifier_cfg_reg17 0x7C Bits Data Element Name [31:0] Ipv6_add2[31:0] Packet_classifier_cfg_reg18 0x80 ...

Page 172

... DS34T101, DS34T102, DS34T104, DS34T108 Packet_classifier_cfg_reg18 0x80 Bits Data Element Name [15:0] VCCV_oam_value CPU_rx_arb_max_fifo_level_reg 0xD4 Bits Data Element Name [31:25] Tx_arb_max_fifo_level [24:10] Reserved [9:0] Rx_arb_max_fifo_level Reset R/W Value in the VCCV_oam_value field below. See section 10.6.13.3. Indicates the value of the 16 most significant bits of the control word for identifying VCCV OAM packets. The combination of this field and VCCV_oam_mask_n above specifies how the device does VCCV OAM identification ...

Page 173

... For each bit, the value 1 indicates that the event occurred. Writing bit clears Writing bit does not change its value. The index n indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. Port[n]_sticky_reg1 0xE4n4 ...

Page 174

... DPLL_level [4:2] Adapt_current_state [1] RTS [0] TSA_int_act_blk The Port[n]_stat_reg2 register has real-time (not latched) status fields. The index n indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. Port[n]_stat_reg2 0x104n8 Bits Data Element Name [31:29] Bw_tunn [28:4] Curr_pdv_std [3:0] Convergence_counter 11.4.2 Bundle Configuration Tables The base address for the TDMoP bundle configuration tables is 0x8,000 ...

Page 175

... DS34T101, DS34T102, DS34T104, DS34T108 AAL1_Bundle[n]_cfg[63:32] 0x100n4 Bits Data Element Name [31:22] Rx_max_buff_size [21:20] Payload_type_machine Tx_RTP [19] (Tx is toward Ethernet MAC) [18] Control_Word_exists [17:16] Tx_dest [15:9] Rx_max_lost_packets [8:4] Number_of_ts [3] Rx_ discard_sanity_fail [2:1] Header_type [0] Tx_R_bit AAL1_Bundle[n]_cfg[95:64] 0x200n4 Bits Data Element Name [31] Reserved [30] Tx_cond_data [29] Tx_dest_framing [28] Tx_CAS_source [27:13] Reserved [12:11] Tx_AAL1_bundle_type Reset ...

Page 176

... DS34T101, DS34T102, DS34T104, DS34T108 AAL1_Bundle[n]_cfg[95:64] 0x200n4 Bits Data Element Name [10:6] Reserved [5:4] Tx_cond_octet_type [3:2] Rx_AAL1_bundle_type [1:0] Protection_mode AAL1_Bundle[n]_cfg[127:96] 0x300n4 Bits Data Element Name [31] Reserved [30:16] Rx_PDVT [15] Rx_CAS_src [14] Rx_cell_chk_ignore [13] Reserved [12] OAM_ID_in_CW [11] Rx_discard [10] Rx_dest [9:8] Tx_MPLS_labels_l2tpv3_cookies Reset R/W Value 00 Unstructured 01 Structured 10 Structured with CAS 11 Reserved R/W None ...

Page 177

... DS34T101, DS34T102, DS34T104, DS34T108 AAL1_Bundle[n]_cfg[127:96] 0x300n4 Bits Data Element Name [7:4] Port_num [3:2] Tx_VLAN_stack [1] Rx_bundle_identifier_valid [0] Reserved AAL1_Bundle[n]_cfg[159:128] 0x400n4 Bits Data Element Name [31:23] Reserved [22] Rx_RTP [21:20] Rx_L2TPV3_cookies [19:15] Reserved [14:10] Packet_size_in_cells [9:5] Tx_bundle_identifier [4:0] Reserved 11.4.2.2 HDLC Bundle Configuration In the register descriptions below, the index n indicates the bundle number 63. ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Bits Data Element Name [31:22] Reserved [21:20] Payload_type_machine [19] Tx_RTP [18] Control_Word_exists [17:16] Tx_dest [15:11] Reserved [10:9] Packet_SN_mode [8:3] Reserved [2:1] Header_type [0] Tx_R_bit HDLC_Bundle[n]_cfg[95:64] 0x200n4 Bits Data Element Name [31:16] Reserved [15:13] Reserved [12:2] Tx_max_frame_size [1:0] Reserved HDLC_Bundle[n]_cfg[127:96] 0x300n4 Bits Data Element Name [31:28] Reserved [27] Tx_stop [26:13] Reserved [12] ...

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... DS34T101, DS34T102, DS34T104, DS34T108 HDLC_Bundle[n]_cfg[127:96] 0x300n4 Bits Data Element Name [7:4] Port_num [3:2] Tx_VLAN_stack [1] Rx_Bundle_Identifier_valid [0] Reserved HDLC_Bundle[n]_cfg[159:128] 0x400n4 Bits Data Element Name [31:22] Reserved [21:20] Rx_L2TPV3_cookies [19:16] Reserved [15:0] Tx_IP_checksum Reset R/W Value cookies in the TX L2TPv3 header 01 One cookie in the TX L2TPv3 header 10 Two cookies in the TX L2TPv3 header ...

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... DS34T101, DS34T102, DS34T104, DS34T108 11.4.2.3 SAToP/CESoPSN Bundle Configuration In the register descriptions below, the index n indicates bundle number 63. SAToP/CESoPSN_Bundle[n]_cfg[31:0] 0x000n4 Bits Data Element Name [31:0] Rx_bundle_identifier SAToP/CESoPSN_Bundle[n]_cfg[63:32] 0x100n4 Bits Data Element Name [31:22] Rx_max_buff_size [21:20] Payload_type_machine [19] Tx_RTP [18] Control_Word_exists [17:16] Tx_dest [15:9] Rx_max_lost_packets [8:4] Number_of_ts [3] Rx_ discard_sanity_fail ...

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... DS34T101, DS34T102, DS34T104, DS34T108 SAToP/CESoPSN_Bundle[n]_cfg[95:64] 0x200n4 Bits Data Element Name [30] Tx_cond_data [29] Tx_dest_framing [28] Tx_CAS_source [27] Reserved TDM_frames_in_packet [26:16] or TDM_bytes_in_packet [15:13] Reserved [12:11] Tx_SATOP_bundle_type [10:6] Reserved [5:4] Tx_cond_octet_type Rx_SAToP/CESoPSN_ [3:2] bundle_type [1:0] Protection_mode SAToP/CESoPSN_Bundle[n]_cfg[127:96] 0x300n4 Bits Data Element Name [31] Reserved [30:16] Rx_PDVT Reset R/W Value 0 Regular operation R/W None 1 Use conditioning octet specified by ...

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... DS34T101, DS34T102, DS34T104, DS34T108 SAToP/CESoPSN_Bundle[n]_cfg[127:96] 0x300n4 Bits Data Element Name [15] Rx_CAS_src [14] Rx_enable_reorder [13] Reserved [12] OAM_ID_in_CW [11] Rx_discard [10] Rx_dest [9:8] Tx_MPLS_lables_l2tpv3_cookies [7:4] Port_num [3:2] Tx_VLAN_stack [1] Rx_Bundle_Identifier_valid [0] Reserved SAToP/CESoPSN_Bundle[n]_cfg[159:128] 0x400n4 Bits Data Element Name [31:24] Reserved [23] Last_value_insertion [22] Rx_RTP [21:20] Rx_L2TPV3_cookies Reset R/W Value Source of signaling towards TDM: R/W None 0 SDRAM signaling jitter buffer CAS tables (section 11 ...

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... DS34T101, DS34T102, DS34T104, DS34T108 SAToP/CESoPSN_Bundle[n]_cfg[159:128] 0x400n4 Bits Data Element Name [19:16] Reserved [15:0] Tx_IP_checksum Reset R/W Value 01 One cookie in the received L2TPv3 header 10 Two cookies in the received L2TPv3 header 11 Reserved R/W None Must be set to zero R/W None IP header checksum for IP total length equal to zero ...

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... DS34T101, DS34T102, DS34T104, DS34T108 11.4.3 Counters Each counter can be read from two different addresses. Reading from the first address0x10,000 offsetdoes not affect the counter value. Reading from the second address0x11,000 offsetcauses the counter to be cleared after it is read. ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Ethernet Rx AAL1 Lost Cells / Rx SAToP/CESoPSN Discarded Packets Counter 0x400n4 Bits Data Element Name [31:16] Reserved [15:0] Lost_AAL1_Rxd_cells / Discarded_SAToP/CESoPSN_R xd_packets TDM Tx HDLC Frames with Error Counter 0x500n4 Bits Data Element Name [31:16] Reserved [15:0] TDM_HDLC_err_frames TDM Tx HDLC Good Frames Counter 0x600n4 ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Jitter Buffer Underrun/Overrun Events Counter 0x800n4 Bits Data Element Name 11.4.3.3 General Counters Received Ethernet Bytes Counter 0xE00 Bits Data Element Name [31:0] ETH_bytes_received Transmitted Ethernet Bytes Counter 0xE04 Bits Data Element Name [31:0] ETH_bytes_transmitted Classified Packets Counter 0xE08 ...

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... DS34T101, DS34T102, DS34T104, DS34T108 11.4.4 Status Tables The TDMoP status tables hold indications of hardware events. Except where noted, these are latched status bits. For each bit, the value 1 indicates that the event occurred. A bit set to 1 maintains its value unless the host CPU changes it ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Tx Payload Type Machine Status 0x200n4 Bits Data Element Name [1] Tx_HDLC_align_err [0] Tx_AAL1_framing_mismatch / Tx_HDLC_CRC_err / Tx_SAToP/CESoPSN_framing_ mismatch Tx Buffers Status 0x400n4 Bits Data Element Name [31:1] Reserved [0] TDM_to_ETH_buff_err Packet Classifier Status 0x600n4 Bits Data Element Name [31:8] Reserved [7] Packet_length_error [6] Rx_sync_loss [5] Rx_remote_fail [4:3] Rx_Lbit_modifier ...

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... Bank 2 TSA tables are located at offset 0x200 for ports and 0x600 for ports the register descriptions in this section, the index port indicates the port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts is the timeslot number 31. register. ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Bank1 Timeslot Assignment Registers Bank2 Timeslot Assignment Registers Bits Data Element Name [31:21] Reserved [20] Remote_loop [19] Local_loop [18] Structured_type [17:16] Timeslot_width [15] First_in_bundle [14] Rx_assigned [13] Transmit_assigned [12:7] Bundle_number [6:5] Reserved [4:0] Jitter_buffer_index Ports 0x000(port-1)0x80ts4 Ports 0x400(port-5)0x80ts4 Ports 0x200(port-1)0x80ts4 ...

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... DS34T101, DS34T102, DS34T104, DS34T108 11.4.6 CPU Queues The pools and queue referred to in this section are shown in the block diagram in or pool level exceeds the associated threshold register, a latched status bit is set in the register which generates an interrupt unless masked by the associated mask bit in the register ...

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... DS34T101, DS34T102, DS34T104, DS34T108 TDM_to_CPU_pool_level 0x04 (0x06) Bits Data Element Name [31:8] Reserved [7:0] Level TDM_to_CPU_pool_thresh 0x08 (0x0A) Bits Data Element Name [31:8] Reserved [7:0] Threshold 11.4.6.2 TDM-to-CPU Queue TDM_to_CPU_q_read 0x0C (0x0E) Bits Data Element Name [31:13] Reserved [12:0] Buffer ID TDM_to_CPU_q_level 0x10 (0x12) Bits Data Element Name ...

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... DS34T101, DS34T102, DS34T104, DS34T108 CPU_to_ETH_q_level 0x1C (0x1E) Bits Data Element Name [31:6] Reserved [5:0] Level CPU_to_ETH_q_thresh 0x20 (0x22) Bits Data Element Name [31:6] Reserved [5:0] Threshold 11.4.6.4 ETH-to-CPU Pool ETH_to_CPU_pool_insert 0x24 (0x26) Bits Data Element Name [31:13] Reserved [12:0] Buffer ID ETH_to_CPU_pool_level 0x28 (0x2A) Bits Data Element Name ...

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... DS34T101, DS34T102, DS34T104, DS34T108 11.4.6.5 ETH- to-CPU Queue ETH_to_CPU_q_read 0x30 (0x32) Bits Data Element Name [31:13] Reserved [12:0] Buffer ID ETH_to_CPU_q_level 0x34 (0x36) Bits Data Element Name [31:8] Reserved [7:0] Level ETH_to_CPU_q_thresh 0x38 (0x3A) Bits Data Element Name [31:8] Reserved [7:0] Threshold 11.4.6.6 CPU-to-TDM Queue CPU_to_TDM_q_insert 0x54 (0x56) ...

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... DS34T101, DS34T102, DS34T104, DS34T108 CPU_to_TDM_q_thresh 0x5C (0x5E) Bits Data Element Name 11.4.6.7 Tx Return Queue Tx_return_q_read 0x60 (0x62) Bits Data Element Name [31:13] Reserved [12:0] Buffer ID Tx_return _q _level 0x64 (0x62) Bits Data Element Name [31:6] Reserved [5:0] Level Tx_return_q_thresh 0x68 (0x6A) Bits Data Element Name [31:6] Reserved ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Rx_return_q_level 0x70 (0x72) Bits Data Element Name [31:6] Reserved [5:0] Level Rx_return_q_thresh 0x74 (0x76) Bits Data Element Name [31:6] Reserved [5:0] Threshold 11.4.7 Transmit Buffers Pool The base address for the TDMoP transmit buffers pool is 0x28,000. See section 11.4.7.1 Per-Bundle Head Pointers In the register descriptions in this section, the index n indicates the bundle number ...

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... The base address for the TDMoP jitter buffer control is 0x30,000. In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number 31. The index n indicates the bundle number 63. See section Table 11-8 ...

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... Current_level [15:2] Reserved [1:0] Status 11.4.8.2 Min_and_max_level In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number 31. 11.4.8.2.1 Structured AAL1/CESoPSN Min_and_max_level (port-1)0x100ts84 Bits Data Element Name [31:26] Reserved [25:16] ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Min_and_max_level (port-1)0x100ts84 Bits Data Element Name [15:10] Reserved [9:0] Maximal_level 11.4.8.2.2 Unstructured AAL1/SAToP Min_and_max_level (port-1)0x1004 Bits Data Element Name [31] Reserved [30:16] Minimal_level [15] Reserved [14:0] Maximal_level 11.4.8.2.3 High Speed AAL1/SAToP Min_and_max_level 0x004 Bits Data Element Name [31:16] Minimal_level [15:0] Maximal_level 11.4.8.3 Bundle Timeslot Registers In this section, the index n indicates the bundle number ...

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... DS34T101, DS34T102, DS34T104, DS34T108 Bundle_ts[n] 0xF00n4 Bits Data Element Name Reset R/W Value 1 Timeslot is assigned to the bundle 0 Timeslot is not assigned to the bundle Note: When the interface type is Nx64k this field should be set to all 1s. Description 200 of 366 ...

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