Datasheets»XMOS»XS1-U6A-64-FB96-C5 Datasheet

XS1-U6A-64-FB96-C5 Datasheet

Download or read online XMOS XS1-U6A-64-FB96-C5 XS1 Series 3.6 V 500 MIPS 64 KB 32-Bit Multicore Microcontroller - BGA-96 pdf datasheet.



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XS1-U6A-64-FB96 Datasheet
2013/07/19
Document Number: X4761,
XMOS © 2013, All Rights Reserved
Specifications of XMOS XS1-U6A-64-FB96-C5
Clock Frequency-Max:
500 MHz
MMAC/MIPS/FLOPS:
-/500/-
Cache Memory Size:
64 kB
I/O Voltage-Max:
3.6 V
Data Bus Width:
32 b

Summary of Contents

Page 1

... XS1-U6A-64-FB96 Datasheet 2013/07/19 XMOS © 2013, All Rights Reserved Document Number: X4761, ...

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... Energy management 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16 Board Integration 17 Example XS1-U6A-64-FB96 Board Designs 18 DC and Switching Characteristics 19 Package Information 20 Ordering Information Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 A Confi ...

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... XS1-U6A-64-FB96 Datasheet TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/. XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you AS IS with no warranty of any kind, express or implied and shall have no liability in relation to its use ...

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... Security PLL OTP ROM devices XS1-U devices are available in a range of resource densities, package, performance and temperature grades depending on your needs. XS1-U devices have up to eight logical cores on a single xCORE tile, providing 500-700 MIPS, 28 GPIO, and 64Kbytes of SRAM. X4761, ...

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... It is included in xTIME- composer Studio or available as a standalone tool from xmos.com/downloads. 1.2 xTIMEcomposer Studio Designing with XS1-U devices is simple thanks to the xTIMEcomposer Studio development environment, which includes a highly efficient compiler, debugger and device programming tools. Because xCORE devices operate deterministically, ...

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... XS1-U6A-64-FB96 Datasheet 2 XS1-U6A-64-FB96 Features Six-Core Multicore Microcontroller with Advanced Multi-Core RISC Architecture Up to 500 MIPS shared between real-time logical cores Each logical core has: Guaranteed throughput of between 16x32bit dedicated registers 159 high-density 16/32-bit instructions All have single clock-cycle execution (except for divide) — ...

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... XS1-U6A-64-FB96 Datasheet 3 Pin Configuration AVDD ADC0 ADC2 B TDO ADC1 ADC3 C TCK RST_N D TMS TDI E XI/ DEBUG_ CLK N F OSC_ XO EXT_N G X0D43/ NC WAKE H VSUP NC J SW1 SW1 K VDDCORE VDDCORE L PGND PGND NC M VSUP VSUP PGND X4761 USB_ ...

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... XS1-U6A-64-FB96 Datasheet 4 Signal Description Module Signal PUPull Up, PDPull Down, STSchmitt Trigger Input, OTOutput Tristate, SSwitchable GND PGND SW1 SW2 Power VDD1V8 VDDCORE VDDIO VSUP ADC0 ADC1 Analog ADC2 ADC3 AVDD USB_DN USB_DP USB USB_ID USB_VBUS MODE[3:0] OSC_EXT_N Clocks XI/CLK XO DEBUG_N ...

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... XS1-U6A-64-FB96 Datasheet Module Name X0D19 X0D20 X0D21 X0D22 X0D24 X0D35 X0D43/WAKE X0D49 X0D50 X0D51 X0D52 X0D53 X0D54 I/O X0D55 X0D56 X0D57 X0D58 X0D61 X0D62 X0D63 X0D64 X0D65 X0D66 X0D67 X0D68 X0D69 X0D70 X4761, Function XLB P4D P8B P16A ...

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... XS1-U6A-64-FB96 Datasheet 5 Example Application Diagram 3V3/5V0 GND C1 C2 4U7 100N GND GND Figure 2: Simplified Reference Schematic X4761, 3V3 C10 U1A 100N A1 AVDD M1 VSUP M2 VSUP H1 VSUP E5 VSS C3 E6 VSS E7 VSS E8 100N VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 GND VSS G6 VSS G7 VSS ...

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... XS1-U6A-64-FB96 Datasheet 6 Product Overview The XS1-U6A-64-FB96 comprises a digital and an analog node, as shown in Figure 3. The digital node comprises an xCORE Tile, a Switch, and a PLL (Phase-locked-loop). The analog node comprises the USB PHY, a multi-channel ADC (Analog to Digital Converter), deep sleep memory, an oscillator, a real-time counter, and power supply control ...

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... USB 2.0 specification, removing all low-level timing requirements from the application. 6.3 ADC and Power Management Each XS1-U6A-64-FB96 device includes a set of analog components, including a 12b, 4-channel ADC, power management unit, watchdog timer, real-time counter and deep sleep memory. The device reduces the number of additional external components required and allows designs to be implemented using simple 2-layer boards ...

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... XS1-L Link Performance and Design Guide, X2999. 7.3 Ports and Clock Blocks Ports provide an interface between the logical cores and I/O pins. The XS1-U6A- 64-FB96 includes a combination of 1bit, 4bit and 8bit ports. In addition the wider ports are partially or fully bonded out making the connected pins available for I/O or xCONNECT links. All pins of a port provide either output or input. Signals in diff ...

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... For 500 MHz parts, once booted, the PLL must be reprogrammed to provide this tile frequency. The XMOS tools perform this operation by default. Further details on configuring the clock can be found in the XS1-L Clock Frequency Control document, X1433. 9 Boot Procedure The device is kept in reset by driving RST_N low ...

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... XS1-U6A-64-FB96 Datasheet the processor starts its internal reset process. After approximately 750,000 input clocks, all GPIO pins have their internal pull-resistor enabled, and the processor boots at a clock speed that depends on MODE0 and MODE1. The processor boot procedure is illustrated in Figure 6. In normal usage, MODE[3:2] controls the boot source according to the table in Figure 7. If bit 5 of the security register (see § ...

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... XS1-U6A-64-FB96 Datasheet 9.1 Boot from SPI If set to boot from SPI, the processor enables the four pins specified in Figure 8, and drives the SPI clock at 2.5 MHz (assuming a 400 MHz core clock). A READ command is issued with a 24-bit address 0x000000. The clock polarity and phase are ...

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... XS1-U6A-64-FB96 Datasheet 9.3 Boot from OTP If an xCORE tile is set to use secure boot (see Figure 6), the boot image is read from address 0 of the OTP memory in the tiles security module. This feature can be used to implement a secure bootloader which loads an en- crypted image from external flash, decrypts and CRC checks it with the processor, and discontinues the boot process if the decryption or CRC check fails ...

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... Deep Sleep Memory The XS1-U6A-64-FB96 device includes 128 bytes of deep sleep memory for state storage during sleep mode. Data stored in the memory is lost if the device is powered down. 11 USB PHY The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go func- tionality. The PHY is confi ...

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... XS1-U6A-64-FB96 Datasheet Each IN (host requests data from device) or OUT (data transferred from host to device) endpoint requires one logical core. To guarantee correct operation the USB logical core must run at at least 80 MIPS, and the logical cores that communicate with the USB core must also run at 80 MIPS ...

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... The 16-bit watchdog timer provides 1ms accuracy and runs independently of the real-time counter. It can be programmed with a time-out of between 1 ms and 65 seconds (Appendix E). If the watchdog is not set before it times out, the XS1-U6A- 64-FB96 is reset. On boot, the program can read a register to test whether the reset was due to the watchdog ...

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... XS1-U6A-64-FB96 Datasheet Wakeup Request Input Activity Timer Event Exit USB Standby Figure 11: XS1-U6A-64- FB96 Power Up States and Transitions 1. An external pin is asserted or deasserted (set by the program); 2. The 64-bit real-time counter reaches a value set by the program The USB host (if USB is enabled) performs a wakeup. ...

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... XS1-U6A-64-FB96 Datasheet Awake Figure 12: 20 Mhz SiOsc Example 24 MHz Crystal trade-offs in oscillator 5 MHz ext osc selection 24 MHz Crystal During deep-sleep, the program can store some state in 128 bytes of Deep Sleep Memory. 14.4 Requirements during sleep mode Whilst in sleep mode, the device must still be powered as normal over 3V3 or 5V0 on VSUP, and 3V3 on VDDIO ...

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... OTP User ID USERCODE return value 0 16 Board Integration XS1-U6A-64-FB96 devices are optimized for layout on low cost, 2 layer PCBs using standard design rules. Careful layout is required to maximize the device X4761, DEBUG BS TAP TAP TDI TDO TDI Device Identification Register ...

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... The power supplies must be brought up monotonically and input voltages must not exceed specification at any time. The VDDIO supply to the XS1-U6A-64-FB96 requires a 100nF X5R or X7R ceramic decoupling capacitor placed as close as possible to the supply pins. If the ADC Is used, it requires a 100nF X5R or X7R ceramic decoupling capacitor placed as close as possible to the AVDD pin ...

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... XS1-U6A-64-FB96 Datasheet 16.1 Land patterns and solder stencils The land pattern recommendations in this document are based on a RoHS compliant process and derived, where possible, from the nominal Generic Requirements for Surface Mount Design and Land Pattern Standards standard aims to achieve desired targets of heel, toe and side fillets for solder- joints ...

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... XS1-U6A-64-FB96 Datasheet 16.2 Ground and Thermal Vias Vias next to each ground ball into the ground plane of the PCB are recommended for a low inductance ground connection and good thermal performance. Vias with with a 0.6mm diameter annular ring and a 0.3mm drill would be suitable. ...

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... XI/CLK input from 3V3 to 1V8. Figure 20 USB and that runs off the internal 20 MHz oscillator. The XS1-U6A-64-FB96 is powered directly from 3V3. Flash, AVDD, RST, and JTAG connectivity are all optional. Flash can be removed if the processor boots from OTP. The AVDD decoupler and wiring can be removed if the ADC is not used ...

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... XS1-U6A-64-FB96 Datasheet U3 5V NCP699SN33 1 VIN VOUT C14 100N GND GND 5V to 3V3 LDO IO Power U4 5V NCP699SN33 1 VIN VOUT C17 100N GND GND 5V to 3V3 LDO Analogue Power (only required i f ADC i s used 4U7 100N 100N ...

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... XS1-U6A-64-FB96 Datasheet U3 5V NCP699SN33 1 VIN C14 3 EN 100N GND GND 5V to 3V3 LDO IO Power U4 5V NCP699SN33 1 VIN 100N GND GND 5V to 3V3 LDO Analogue Power (only required i f ADC i s used 4U7 100N 100N ...

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... XS1-U6A-64-FB96 Datasheet 3V3 3V3 C1 C2 4U7 100N GND GND Notes: Internal oscillator 20 MHz Mode [1: (internal pullups) Analogue supply and filter may be ommited if ADC is not required Design assumes external 3V3 supply Figure 20: Example minimal system schematic, with top and bottom ...

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... XS1-U6A-64-FB96 Datasheet 18 DC and Switching Characteristics 18.1 Operating Conditions Symbol Parameter Power Supply (3.3V Mode) VSUP Power Supply (5V Mode) VDDIO I/O supply voltage AVDD Analog Supply and Reference Voltage Cl xCORE Tile I/O load capacitance Figure 21: Ta Ambient operating temperature Operating Tj Junction temperature conditions Tstg Storage temperature 18 ...

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... XS1-U6A-64-FB96 Datasheet 18.3 DC2 Characteristics Symbol VDD1V8 V(RIPPLE) V(ACC) F(S) F(SVAR) Effic PGT(HIGH) Figure 23: DC2 charac- PGT(LOW) teristics 18.4 ADC Characteristics Symbol N Fs Nch Vin DNL INL E(GAIN) Figure 24: E(OFFSET) ADC charac- T(PWRUP) teristics ENOB 18.5 USB Characteristics Figure 25: USB charac- teristics Symbol Parameter Contact XMOS for further details on USB characteristics ...

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... XS1-U6A-64-FB96 Datasheet 18.6 Digital I/O Characteristics Symbol Parameter V(IH) Input high voltage V(IL) Input low voltage V(OH) Output high voltage Figure 26: Digital I/O V(OL) Output low voltage characteris- R(PU) Pull-up resistance tics R(PD) Pull-down resistance 18.7 ESD Stress Voltage Figure 27: Symbol Parameter ESD stress HBM Human body model voltage CDM Charged Device Model 18 ...

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... Information on interfacing to high-speed synchronous interfaces can be found in the XS1 Port I/O Timing document, X5821. 18.14 xConnect Link Performance Symbol B(2blinkP) ...

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... XS1-U6A-64-FB96 Datasheet 18.15 JTAG Timing Symbol f(TCK_D) f(TCK_B) T(SETUP) Figure 35: T(HOLD) JTAG timing T(DELAY) X4761, Parameter TCK frequency (debug) TCK frequency (boundary scan) TDO to TCK setup time TDO to TCK hold time TCK to output delay MIN TYP MAX UNITS TBC MHz TBC ...

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... XS1-U6A-64-FB96 Datasheet 19 Package Information X4761, 35 ...

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... XS1-U6A-64-FB96 Datasheet 19.1 Part Marking CCFRTM MCYYWWXX Figure 36: LLLLLL.LL Part marking scheme 20 Ordering Information Product Code Figure 37: Orderable XS1U6A64FB96C5 part numbers XS1U6A64FB96I5 X4761 Number of logical cores F - Product family R - RAM (in log- Temperature grade M - MIPS grade ...

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... XS1-U6A-64-FB96 Datasheet Appendices A Configuring the device The device is configured through ten banks of registers, as shown in Figure 38. Security PLL OTP ROM Hardware response ports Figure 38: Registers A.1 Accessing a processor status register The processor status registers are accessed directly from the processor instruction set. The instructions GETPS and SETPS read and write a word. The register number should be translated into a processor-status resource identifi ...

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... XS1-U6A-64-FB96 Datasheet The response to the read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). A.3 Accessing digital and analogue node configuration registers Node configuration registers can be accessed through the interconnect using ...

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... XS1-U6A-64-FB96 Datasheet control-token 37 The response to the read message comprises either control token 3, data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). X4761, 24-bit response 8-bit channel-end identifier register number 8-bit control-token size 1 39 ...

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... XS1-U6A-64-FB96 Datasheet B Processor Status Configuration The processor status control registers can be accessed directly by the processor using processor status reads and writes (use reads and writes). Number 0x00 0x01 0x02 0x03 0x05 0x06 0x07 0x08 0x09 0x0A 0x10 0x11 0x12 ...

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... XS1-U6A-64-FB96 Datasheet B.1 RAM base address: 0x00 This register contains the base address of the RAM initialized to 0x00010000. Bits Perm 0x00: 31:2 RW RAM base address 1:0 RO B.2 Vector base address: 0x01 Base address of event vectors in each resource interrupt or event, the 16 most significant bits of the destination address are provided by this register; the least signifi ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:24 RO 23: 0x03: xCORE Tile 7:0 RO boot status B.5 Security configuration: 0x05 Copy of the security register as read from OTP. 0x05: Bits Perm Security configuration 31:0 RO B.6 Ring Oscillator Control: 0x06 There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register ...

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... XS1-U6A-64-FB96 Datasheet B.8 Ring Oscillator Value: 0x08 This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset. 0x08: Bits Perm Ring 31:16 RO Oscillator Value 15:0 RO B.9 Ring Oscillator Value: 0x09 This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 0x11: Debug SPC 31:0 DRW B.13 Debug SSP: 0x12 This register contains the value of the SSP register when the debugger was called. Bits Perm 0x12: Debug SSP 31:0 DRW B.14 DGETREG operand 1: 0x13 The resource ID of the logical core whose state read. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:18 RO 17:16 DRW 15:8 DRW 7:3 RO 2:0 DRW 0x15: Debug interrupt type B.17 Debug interrupt data: 0x16 On a data watchpoint, this register contains the effective address of the memory operation that triggered the debugger resource watchpoint, it countains the resource identifier. 0x16: ...

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... XS1-U6A-64-FB96 Datasheet B.19 Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG. This is the same set of registers as the Scratch registers in the xCORE tile 0x20 .. 0x27: Bits Perm Debug scratch 31:0 DRW B.20 Instruction breakpoint address: 0x30 .. 0x33 This register contains the address of the instruction breakpoint ...

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... XS1-U6A-64-FB96 Datasheet 0x50 .. 0x53: Data Bits Perm watchpoint address 1 31:0 DRW B.23 Data watchpoint address 2: 0x60 .. 0x63 This set of registers contains the second address for the four data watchpoints. 0x60 .. 0x63: Data Bits Perm watchpoint address 2 31:0 DRW B.24 Data breakpoint control register: 0x70 .. 0x73 This set of registers controls each of the four data watchpoints ...

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... XS1-U6A-64-FB96 Datasheet 0x80 .. 0x83: Resources Bits Perm breakpoint mask 31:0 DRW B.26 Resources breakpoint value: 0x90 .. 0x93 This set of registers contains the value for the four resource watchpoints. 0x90 .. 0x93: Resources Bits Perm breakpoint value 31:0 DRW B.27 Resources breakpoint control register: 0x9C .. 0x9F This set of registers controls each of the four resource watchpoints ...

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... XS1-U6A-64-FB96 Datasheet C xCORE Tile Configuration The xCORE Tile control registers can be accessed using configuration reads and writes (use for reads and writes). ...) Number 0x00 0x01 0x02 0x04 0x05 0x06 0x07 0x10 .. 0x13 0x20 .. 0x27 0x40 0x41 0x42 0x43 ...

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... XS1-U6A-64-FB96 Datasheet C.1 Device identification: 0x00 Bits Perm 31:24 RO 23:16 RO 0x00: 15:8 RO Device identification 7:0 RO C.2 xCORE Tile description 1: 0x01 This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile. Bits Perm 31:24 RO 23:16 RO 0x01: 15:8 RO xCORE Tile description 1 ...

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... XS1-U6A-64-FB96 Datasheet 0x04: Control Bits Perm PSwitch 31:1 RO permissions to debug 0 CRW registers C.5 Cause debug interrupts: 0x05 This register can be used to raise a debug interrupt in this xCORE tile. Bits Perm 31:2 RO 0x05 Cause debug interrupts 0 CRW C.6 xCORE Tile clock divider: 0x06 This register contains the value used to divide the PLL clock to create the xCORE tile clock ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:26 RO 25:24 RO 23:16 RO 15 0x10 .. 0x13 PLink status C.9 Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch. This is the same set of registers as the Debug Scratch registers in the processor 0x20 ...

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... XS1-U6A-64-FB96 Datasheet C. logical core 1: 0x41 0x41: Bits Perm PC of logical core 1 31 logical core 2: 0x42 0x42: Bits Perm PC of logical core 2 31 logical core 3: 0x43 0x43: Bits Perm PC of logical core 3 31 logical core 4: 0x44 0x44: ...

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... XS1-U6A-64-FB96 Datasheet 0x60: Bits Perm SR of logical core 0 31 logical core 1: 0x61 0x61: Bits Perm SR of logical core 1 31 logical core 2: 0x62 0x62: Bits Perm SR of logical core 2 31 logical core 3: 0x63 0x63: Bits Perm SR of logical ...

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... XS1-U6A-64-FB96 Datasheet C.22 Chanend status: 0x80 .. 0x9F These registers record the status of each channel-end on the tile. Bits Perm 31:26 RO 25:24 RO 23:16 RO 15 0x80 .. 0x9F: Chanend 0 RO status X4761, Init Description - Reserved 00 - ChannelEnd ERROR PSCTL Idle. Based on SRC_TARGET_TYPE value, it represents channelEnd ID or Idle status ...

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... XS1-U6A-64-FB96 Datasheet D Digital Node Configuration The digital node control registers can be accessed using configuration reads and writes (use for reads and writes). ...) Number 0x00 0x01 0x04 0x05 0x06 0x07 0x08 0x0C 0x0D 0x10 0x1F 0x20 .. 0x27 0x40 .. 0x43 Figure 41: 0x80 ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:24 RO 0x01: 23:16 RO System 15:8 RO switch description 7:0 RO D.3 Switch configuration: 0x04 This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode. Bits Perm 7:1 RO 0x04: Switch 0 RO configuration D.4 Switch node identifi ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:26 RO 25:23 RW 22: 0x06: 6:0 RW PLL settings D.6 System switch clock divider: 0x07 Sets the ratio of the PLL clock and the switch clock. Bits Perm 0x07: 31:16 RO System switch clock 15:0 RW divider D.7 Reference clock: 0x08 Sets the ratio of the PLL clock and the reference clock used by the node. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:28 RW 27:24 RW 23:20 RW 19:16 RW 15:12 RW 11:8 RW 0x0C: 7:4 RW Directions 0-7 3:0 RW D.9 Directions 8-15: 0x0D This register contains eight directions, for packets with a mismatch in bits 15..8 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. Bits Perm 31:28 RW 27:24 RW ...

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... XS1-U6A-64-FB96 Datasheet D.11 Debug source: 0x1F Contains the source of the most recent debug event. Bits Perm 31 3:1 RO 0x1F Debug source D.12 Link status, direction, and network: 0x20 .. 0x27 These registers contain status information for low level debugging (read-only), the network number that each link belongs to, and the direction that each link is part of ...

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... XS1-U6A-64-FB96 Datasheet D.13 PLink status and network: 0x40 .. 0x43 These registers contain status information and the network number that each processor-link belongs to. Bits Perm 31:26 RO 25:24 RO 23:16 RO 15 0x40 .. 0x43: PLink status 0 RO and network D.14 Link configuration and initialization: 0x80 .. 0x87 These registers contain confi ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 29: 0x80 .. 0x87: 21:11 RW Link configuration and 10:0 RW initialization D.15 Static link configuration: 0xA0 .. 0xA7 These registers are used for static (ie, non-routed) links. When a link is made static, all traffic is forwarded to the designated channel end and no routing is attempted. ...

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... XS1-U6A-64-FB96 Datasheet E Analogue Node Configuration The analogue node control registers can be accessed using configuration reads and writes (use for reads and writes). ...) Number 0x00 0x04 0x05 0x50 0x51 0x80 Figure 42: 0xD6 Summary 0xD7 E.1 Device identification register: 0x00 This register contains version information, and information on power-on behavior ...

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... RW identifier E.4 Reset and Mode Control: 0x50 The XS1-S has two main reset signals: a system-reset and an xCORE Tile-reset. System-reset resets the whole system including external devices, whilst xCORE Tile-reset resets the xCORE Tile(s) only. The resets are induced either by software (by a write to the register below one of the following: ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31: 23:18 RO 17: 0x50: Reset and Mode Control E.5 System clock frequency: 0x51 Bits Perm 31:7 RO 6:0 RW 0x51: System clock frequency X4761, Init Description - Reserved Tristate processor mode pins. - Reserved Processor mode pins. - Reserved 0 USB peripheral register access enable ...

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... XS1-U6A-64-FB96 Datasheet E.6 Link Control and Status: 0x80 Bits Perm 31: 21:11 RW 0x80: Link Control 10:0 RW and Status E.7 1 KHz Watchdog Control: 0xD6 The watchdog provides a mechanism to prevent programs from hanging by re- setting the xCORE Tile after a pre-set time. The watchdog should be periodically “ ...

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... XS1-U6A-64-FB96 Datasheet E.8 Watchdog Disable: 0xD7 To enable the watchdog, write 0 to this register. To disable the watchdog, write the value 0x0D1SAB1E to this register. Bits Perm 0xD7: Watchdog 31:0 RW Disable F USB PHY Configuration The USB PHY is connected to the following ports: XS1_PORT_1J Clk XS1_PORT_1K ...

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... XS1-U6A-64-FB96 Datasheet Number 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 Figure 43: 0x38 Summary 0x3C F.1 UIFM reset: 0x00 A write to this register with any data resets all UIFM state, but does not otherwise affect the phy. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31 0x04 UIFM IFM control 0 RW F.3 UIFM Device Address: 0x08 The device address whose packets should be received. 0 until enumeration, it should be set to the assigned value after enumeration. Bits Perm 31:7 RO 0x08: UIFM Device ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31 0x10 UIFM 1 RW on-the-go control 0 RW F.6 UIFM on-the-go flags: 0x14 Status flags used for on-the-go negotiation Bits Perm 31 0x14 UIFM 1 RO on-the-go flags 0 RO X4761, Init ...

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... XS1-U6A-64-FB96 Datasheet F.7 UIFM Serial Control: 0x18 Bits Perm 31 0x18 UIFM Serial Control 0 RW F.8 UIFM signal flags: 0x1C Set of flags that monitor line and error states. These flags normally clear on the next packet, but they may be made sticky by using PER_UIFM_FLAGS_STICKY, in which they must be cleared explicitly ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 0x20: 31:7 RO UIFM Sticky flags 6:0 RW F.10 UIFM port masks: 0x24 Set of masks that identify how port 1N, port 1O and port 1P are affected by changes to the flags in FLAGS Bits Perm 31:23 RO 22: 14 0x24: 6:0 RW UIFM port masks F.11 UIFM SOF value: 0x28 ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:4 RO 0x2C: UIFM PID 3:0 RO F.13 UIFM Endpoint: 0x30 The last endpoint seen Bits Perm 31:5 RO 0x30 UIFM Endpoint 3:0 RO F.14 UIFM Endpoint match: 0x34 This register can be used to mark UIFM endpoints as special. Bits Perm 31:16 RO 0x34: UIFM 15:0 RW Endpoint match F.15 UIFM power signalling: 0x38 ...

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... XS1-U6A-64-FB96 Datasheet F.16 UIFM PHY control: 0x3C Bits Perm 31: 17: 11 0x3C: 6:4 RW UIFM PHY control 3 ADC Configuration The device has a 12-bit Analogue to Digital Converter (ADC). It has multiple input pins, and on each positive clock edge on port 1I, it samples and converts a value on the next input pin ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:8 RW 0x00: 7:1 RO ADC Control input pin G.2 ADC Control input pin 1: 0x04 Controls specific to ADC input pin 1. Bits Perm 31:8 RW 0x04: 7:1 RO ADC Control input pin G.3 ADC Control input pin 2: 0x08 Controls specific to ADC input pin 2. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:8 RW 0x0C: 7:1 RO ADC Control input pin G.5 ADC General Control: 0x20 General ADC control. Bits Perm 31: 23:18 RO 17:16 RW 15 0x20: ADC General Control X4761, Init Description 0 The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifi ...

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... XS1-U6A-64-FB96 Datasheet H Deep sleep memory Configuration This peripheral contains a 128 byte RAM that retains state whilst the main processor is put to sleep. The Deep sleep memory is peripheral 3. The control registers are accessed using 8-bit reads and writes (use (device, 3, ...) ...

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... XS1-U6A-64-FB96 Datasheet Number 0x00 Figure 46: 0x01 Summary 0x02 I.1 General oscillator control: 0x00 Bits Perm 7 0x00: General 0 RW oscillator control I.2 On-silicon-oscillator control: 0x01 This register controls the on-chip logic that implements an on-chip oscillator. The on-chip oscillator does not require an external crystal, but does not provide an accurate timing source ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 7 0x02: Crystal- oscillator 0 RW control J Real time clock Configuration The Real time clock is peripheral 5. The control registers are accessed using 32-bit reads and writes (use for reads and writes). 5, ...) Number Figure 47: 0x00 Summary 0x04 J.1 Real time counter least signifi ...

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... XS1-U6A-64-FB96 Datasheet K Power control block Configuration The Power control block is peripheral 6. The control registers are accessed using 32-bit reads and writes (use device, 6, ...) Number 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x2C 0x30 0x34 Figure 48: ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31: 0x00 General control K.2 Time to wake-up, least significant 32 bits: 0x04 This register stores the time to wake-up. The value is only used if wake-up from the real-time clock is enabled, and the device is asleep. ...

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... XS1-U6A-64-FB96 Datasheet 0x08: Time to wake-up, Bits Perm most significant 32 31:0 RW bits K.4 Power supply states whilst ASLEEP: 0x0C This register controls the state the power control block should be in when in the ASLEEP state. It also defines the minimum time that the system shall stay in this state ...

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... XS1-U6A-64-FB96 Datasheet K.5 Power supply states whilst WAKING1: 0x10 This register controls what state the power control block should be in when in the WAKING1 state. It also defines the minimum time that the system shall stay in this state. When the minimum time is expired, the next state is entered if all enabled power supplies are good ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:21 RO 20: 13: 7 0x14: 3:2 RO Power supply 1 RO states whilst WAKING2 0 RW K.7 Power supply states whilst AWAKE: 0x18 This register controls what state the power control block should be in when in the AWAKE state. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31: 13: 7 0x18: 3:2 RO Power supply 1 RO states whilst AWAKE 0 RW K.8 Power supply states whilst SLEEPING1: 0x1C This register controls what state the power control block should be in when in the SLEEPING1 state. It also defines the time that the system shall stay in this state. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:21 RO 20: 13: 7 0x1C: 3:2 RO Power supply 1 RO states whilst SLEEPING1 0 RW K.9 Power supply states whilst SLEEPING2: 0x20 This register controls what state the power control block should be in when in the SLEEPING2 state. It also defines the time that the system shall stay in this state. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:21 RO 20: 13: 7 0x20: 3:2 RO Power supply 1 RO states whilst SLEEPING2 0 RW K.10 Power sequence status: 0x24 This register defines the current status of the power supply controller. X4761, Init Description - Reserved 16 Log2 number of cycles to stay in this state: ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31: 27: 23:19 RO 18: 13: 7 0x24: 3:2 RO Power 1 RO sequence status 0 RO K.11 DCDC control: 0x2C This register controls the two DC-DC converters. X4761, Init Description - Reserved VOUT6 was enabled in the previous state. ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:26 RO 25:24 RW 23: 14:13 RW 12: 6:5 RW 4:2 RO 1:0 RW 0x2C: DCDC control K.12 Power supply status: 0x30 This register provides the current status of the power supplies. X4761, Init Description - Reserved 2 Sets the power good level for VDDCORE and VDD1V8 ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31: 23: 18: 15: 7:2 RO 0x30 Power supply status 0 RO K.13 VDDCORE level control: 0x34 This register can be used to set the desired voltage on VDDCORE. If the level raised or lowered, it should be raised in steps of no more than 10 mV per microsecond in order to prevent overshoot and undershoot ...

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... XS1-U6A-64-FB96 Datasheet Bits Perm 31:3 RO 2:0 RW 0x40: LDO5 level control X4761, Init Description - Reserved pin The required voltage in 100 mV steps: 0: 0.6V 1: 0.7V 2: 0.8V ... 6: 1.2V 7: 1.3V 91 ...

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... XS1-U6A-64-FB96 Datasheet L Device Errata This section describes minor operational differences from the data sheet and recommended workarounds. As device and documentation issues become known, this section will be updated the document revised. To guarantee a logic low is seen on the pins DEBUG_N, MODE[3:0], TMS, TCK and TDI, the driving circuit should present an impedance of less than 100 Ω ...

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... XS1-U6A-64-FB96 Datasheet M.2 JTAG-only xSYS header The xSYS header connects to an xTAG debugger, which has a 20-pin 0.1" female IDC header. The design will hence need a male IDC header. We advise to use a boxed header to guard against incorrect plug-ins. If you use a 90 degree angled header, make sure that pins ...

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... XS1-U6A-64-FB96 Datasheet N Schematics Design Check List This section is a checklist for use by schematics designers using the XS1-U6A-64-FB96. Each of the following sections contains items to check for each design. N.1 Clock If you use USB, then your clock frequency is one of 12, 24, 48 MHz (Section 8) ...

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... XS1-U6A-64-FB96 Datasheet N.4 Multi device designs Skip this section if your design only includes a single XMOS device. One device is connected to a SPI flash for booting. Devices that boot from link have MODE2 grounded and MODE3 NC. These device must have link XLB connected to a device to boot from (see 9). If you included an XSYS header, you have included buff ...

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... XS1-U6A-64-FB96 Datasheet O PCB Layout Design Check List This section is a checklist for use by PCB designers using the XS1-U6A- 64-FB96. Each of the following sections contains items to check for each design. O.1 Ground Balls and Ground Plane There is one via for each ground ball to minimize impedance and conduct heat away from the device (Section 16 ...

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... Programming XC on XMOS Devices xTIMEcomposer User Guide Q Related Documentation Document Title The XMOS XS1 Architecture XS1 Port I/O Timing XS1-L System Specification XS1-L Link Performance and Design Guidelines XS1-L Clock Frequency Control X4761, Information Timers, ports, clocks, cores and channels Compilers, assembler and ...

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... XS1-U6A-64-FB96 Datasheet R Revision History Date Description 2013-01-30 New datasheet - revised part numbering 2013-02-26 New multicore microcontroller introduction Moved configuration sections to appendices 2013-03-27 Added connection details for USB_VBUS/USB_ID - Section VDDCORE parameters - Section 2013-04-16 OSC_REF_EXT_N Properties - Section Sleep mode requirements include JTAG - Section ...

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