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XS1-U16A-128-FB217-C10 Datasheet

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XS1-U16A-128-FB217 Datasheet
2013/04/16
Document Number: X1110,
XMOS © 2013, All Rights Reserved
Specifications of XMOS XS1-U16A-128-FB217-C10
Family Name:
XS1
Core Processor:
XCore
Program Memory Type:
ROMLess
RAM Size:
64 kB
Speed:
500 MHz
No of I/O Lines:
73
Peripherals:
On-Chip-ADC / PWM / Watchdog
Number Of Timers:
1
Supply Voltage:
3 to 5.5 V
Operating Temperature:
0 to 70 °C
On-Chip ADC:
8-chx12-bit
Watchdog:
1

Summary of Contents

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... XS1-U16A-128-FB217 Datasheet 2013/04/16 XMOS © 2013, All Rights Reserved Document Number: X1110, ...

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... XS1-U16A-128-FB217 Datasheet Table of Contents 1 xCORE Multicore Microcontrollers 2 XS1-U16A-128-FB217 Features 3 Pin Configuration 4 Signal Description 5 Example Application Diagram 6 Product Overview 7 xCORE Tile Resources 8 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 Boot Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11 USB PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12 Analog-to-Digital Converter 13 Supervisor Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 Energy management 15 JTAG ...

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... Security PLL devices OTP ROM XS1-U devices are available in a range of resource densities, package, performance and temperature grades depending on your needs. XS1-U devices have up to eight logical cores on a single xCORE tile, providing 500-700 MIPS, 28 GPIO, and 64Kbytes of SRAM. X1110, ...

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... It is included in xTIME- composer Studio or available as a standalone tool from xmos.com/downloads. 1.2 xTIMEcomposer Studio Designing with XS1-U devices is simple thanks to the xTIMEcomposer Studio development environment, which includes a highly efficient compiler, debugger and device programming tools. Because xCORE devices operate deterministically, ...

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... XS1-U16A-128-FB217 Datasheet 2 XS1-U16A-128-FB217 Features 16-Core Multicore Microcontroller with Advanced Multi-Core RISC Architecture Up to 1000 MIPS shared between real-time logical cores across two tiles Each logical core has: Guaranteed throughput of between 16x32bit dedicated registers 159 high-density 16/32-bit instructions All have single clock-cycle execution (except for divide) — ...

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... XS1-U16A-128-FB217 Datasheet 3 Pin Configuration X1D05 X1D06 X1D07 X1D08 X1D09 B X1D04 X1D53 X1D54 X1D55 X1D56 C X1D03 X1D52 D X1D02 X1D51 E X1D01 X1D50 F X1D00 X1D49 G USB_ USB_ DN VBUS H USB_ USB_ X0D43/ RST_N WAKE K VDDIO VDDIO L ADC6 ADC7 M ADC4 ADC5 ...

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... XS1-U16A-128-FB217 Datasheet 4 Signal Description Module Signal PUPull Up, PDPull Down, STSchmitt Trigger Input, OTOutput Tristate, SSwitchable GND PGND PSUP SW1 Power SW2 VDD1V8 VDDCORE VDDIO VDDIO_OUT ADC0 ADC1 ADC2 ADC3 Analog ADC4 ADC5 ADC6 ADC7 AVDD USB_DN USB_DP USB USB_ID USB_VBUS MODE[4:0] ...

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... XS1-U16A-128-FB217 Datasheet Module Name X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D24 X0D35 X0D43/WAKE X1D00 X1D01 X1D02 X1D03 X1D04 X1D05 X1D06 X1D07 X1D08 I/O X1D09 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21 X1D22 X1D23 X1D24 ...

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... XS1-U16A-128-FB217 Datasheet Module Name X1D35 X1D36 X1D37 X1D38 X1D39 X1D49 X1D50 X1D51 X1D52 X1D53 X1D54 X1D55 I/O X1D56 X1D57 X1D58 X1D61 X1D62 X1D63 X1D64 X1D65 X1D66 X1D67 X1D68 X1D69 X1D70 X1110, Function 0 P1L P1M P8D P16B P1N P8D P16B ...

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... XS1-U16A-128-FB217 Datasheet 5 Example Application Diagram 3V3/5V0 GND C1 C2 4U7 100N GND GND Figure 2: Simplified Reference Schematic X1110, 3V3 C10 U1A 100N N1 AVDD V7 VSUP W7 VSUP W1 VSUP F6 VSS 100N . . . . . . . . . . GND . . . . . . . . . . . . . K14 VSS XS1-U16A-128-FB217 GND 3V3 C9 K1 100N VDDIO K2 VDDIO GND V3 VDDCORE W3 VDDCORE ...

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... XS1-U16A-128-FB217 Datasheet 6 Product Overview The XS1-U16A-128-FB217 comprises a digital and an analog node, as shown in Figure 3. The digital node comprises an xCORE Tile, a Switch, and a PLL (Phase- locked-loop). The analog node comprises the USB PHY, a multi-channel ADC (Analog to Digital Converter), deep sleep memory, an oscillator, a real-time counter, and power supply control ...

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... USB 2.0 specification, removing all low-level timing requirements from the application. 6.3 ADC and Power Management Each XS1-U16A-128-FB217 device includes a set of analog components, including a 12b, 8-channel ADC, power management unit, watchdog timer, real-time counter and deep sleep memory. The device reduces the number of additional external components required and allows designs to be implemented using simple 2-layer boards ...

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... All packet communications can be multiplexed onto a single link. Information on the supported routing topologies that can be used to connect multiple devices together can be found in the XS1-L Link Performance and Design Guide, X2999. 7.3 Ports and Clock Blocks Ports provide an interface between the logical cores and I/O pins. All pins of a port provide either output or input. Signals in diff ...

Page 14

... PLL configuration register. The MODE pins must be held at a static value until the third rising edge of the system clock following the deassertion of the system reset. Further details on configuring the clock can be found in the XS1-L Clock Frequency Control document, X1433. X1110, ...

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... XS1-U16A-128-FB217 Datasheet 9 Boot Procedure The device is kept in reset by driving RST_N low. When in reset, all GPIO pins are high impedance. When the device is taken out of reset by releasing RST_N the processor starts its internal reset process. After approximately 750,000 input clocks, all GPIO pins have their internal pull-resistor enabled, and the processor boots at a clock speed that depends on MODE0 and MODE1 ...

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... XS1-U16A-128-FB217 Datasheet If set to boot from a Link, the processor enables Link B around 200 ns after the boot process starts. Enabling the Link switches off the pull-down X8338, on resistors X0D16..X0D19, drives X0D16 and X0D17 low (the initial state for the Link), and monitors pins X0D19 and X0D20 for boot-traffic. X0D19 and X0D20 must be low at this stage ...

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... There is no dedicated external memory interface, although data memory can be expanded through appropriate use of the ports. 10.3 Deep Sleep Memory The XS1-U16A-128-FB217 device includes 128 bytes of deep sleep memory for state storage during sleep mode. Data stored in the memory is lost if the device is powered down. 11 USB PHY The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go func- tionality. The PHY is confi ...

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... The 16-bit watchdog timer provides 1ms accuracy and runs independently of the real-time counter. It can be programmed with a time-out of between 1 ms and 65 seconds (Appendix E). If the watchdog is not set before it times out, the XS1-U16A- 128-FB217 is reset. On boot, the program can read a register to test whether the reset was due to the watchdog ...

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... The normal mode in which the XS1-U16A-128-FB217 operates is the AWAKE mode. In this mode, all cores, memory, and peripherals operate as normal. To save power, the XS1-U16A-128-FB217 can be put into a deep sleep mode, called ASLEEP, where the digital node is powered down, and most peripherals are powered down. The XS1-U16A-128-FB217 will stay in the ASLEEP mode until one of three conditions external pin is asserted or deasserted (set by the program) ...

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... XS1-U16A-128-FB217 Datasheet 3. The USB host (if USB is enabled) performs a wakeup. When the chip is awake, the real-time counter counts the number of clock ticks on the oscillator. As such, the real-time counter will run at a fixed ratio, but synchronously with the 100 MHz timers on the xCORE Tile. When asleep, the real-time counter can be automatically switched to the 31,250 Hz silicon oscillator to save power (see Appendix I) ...

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... XS1-U16A-128-FB217 Datasheet This will result in a power consumption of less than 100 uA on both PSUP and VDDIO. If any power supply loses power-good status during the asleep-to-awake or awake- to-asleep transitions, a system reset is issued. 15 JTAG The JTAG module can be used for loading programs, boundary scan testing, in- circuit source-level debugging and programming the OTP memory ...

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... The power supplies must be brought up monotonically and input voltages must not exceed specification at any time. The VDDIO supply to the XS1-U16A-128-FB217 requires a 100nF X5R or X7R ceramic decoupling capacitor placed as close as possible to the supply pins. If the ADC Is used, it requires a 100nF X5R or X7R ceramic decoupling capacitor placed as close as possible to the AVDD pin ...

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... XS1-U16A-128-FB217 Datasheet The crystal oscillator requires careful routing of the nodes as these are high impedance and very noise sensitive. Hence, the traces should be as wide and short as possible, and routed over a continuous ground plane. They should not be routed near noisy supply lines or clocks. The device has a load capacitance of 18pF for the crystal ...

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... XS1-U16A-128-FB217 Datasheet 0.80 Figure 14: Example land pattern ø0.35 included moisture indicator card shows excessive levels of moisture, then the parts should be baked as appropriate before use. This is based on information from Joint IPC/JEDEC Standard For Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface-Mount Devices X1110, 14 ...

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... XS1-U16A-128-FB217 Datasheet 17 DC and Switching Characteristics 17.1 Operating Conditions Symbol Parameter Power Supply (3.3V Mode) VSUP Power Supply (5V Mode) VDDIO I/O supply voltage AVDD Analog Supply and Reference Voltage Cl xCORE Tile I/O load capacitance Figure 15: Ta Ambient operating temperature Operating Tj Junction temperature conditions Tstg Storage temperature 17 ...

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... XS1-U16A-128-FB217 Datasheet 17.3 DC2 Characteristics Symbol VDD1V8 V(RIPPLE) V(ACC) F(S) F(SVAR) Effic PGT(HIGH) Figure 17: DC2 charac- PGT(LOW) teristics 17.4 ADC Characteristics Symbol N Fs Nch Vin DNL INL E(GAIN) Figure 18: E(OFFSET) ADC charac- T(PWRUP) teristics ENOB 17.5 USB Characteristics Figure 19: USB charac- teristics Symbol Parameter Contact XMOS for further details on USB characteristics. ...

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... XS1-U16A-128-FB217 Datasheet 17.6 Digital I/O Characteristics Symbol Parameter V(IH) Input high voltage V(IL) Input low voltage V(OH) Output high voltage Figure 20: Digital I/O V(OL) Output low voltage characteris- R(PU) Pull-up resistance tics R(PD) Pull-down resistance 17.7 ESD Stress Voltage Figure 21: Symbol Parameter ESD stress HBM Human body model voltage CDM Charged Device Model 17 ...

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... Information on interfacing to high-speed synchronous interfaces can be found in the XS1 Port I/O Timing document, X5821. 17.14 xConnect Link Performance Symbol B(2blinkP) ...

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... XS1-U16A-128-FB217 Datasheet 17.15 JTAG Timing Symbol f(TCK_D) f(TCK_B) T(SETUP) Figure 29: T(HOLD) JTAG timing T(DELAY) X1110, Parameter TCK frequency (debug) TCK frequency (boundary scan) TDO to TCK setup time TDO to TCK hold time TCK to output delay MIN TYP MAX UNITS TBC MHz TBC MHz ...

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... XS1-U16A-128-FB217 Datasheet 18 Package Information X1110, 29 ...

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... XS1-U16A-128-FB217 Datasheet 18.1 Part Marking CCFRTM MCYYWWXX Figure 30: LLLLLL.LL Part marking scheme 19 Ordering Information Product Code Figure 31: Orderable XS1U16A128FB217C10 part numbers XS1U16A128FB217I10 X1110 Number of logical cores F - Product family R - RAM (in log- Temperature grade M - MIPS grade ...

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... XS1-U16A-128-FB217 Datasheet Appendices A Configuring the device The device is configured through ten banks of registers, as shown in Figure 32. Security PLL OTP ROM Hardware response ports Hardware response ports Figure 32: Security PLL OTP ROM Registers A.1 Accessing a processor status register The processor status registers are accessed directly from the processor instruction set. The instructions GETPS and SETPS read and write a word. The register number should be translated into a processor-status resource identifi ...

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... XS1-U16A-128-FB217 Datasheet A write message comprises the following: control-token 192 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 193 The response to the read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). A.3 Accessing digital and analogue node confi ...

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... XS1-U16A-128-FB217 Datasheet A channel-end should be allocated to communicate with the configuration registers. The destination of the channel-end should be set to node-identifier and A write message comprises the following: control-token 36 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). ...

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... XS1-U16A-128-FB217 Datasheet B Processor Status Configuration The processor status control registers can be accessed directly by the processor using processor status reads and writes (use reads and writes). Number 0x00 0x01 0x02 0x03 0x05 0x06 0x07 0x08 0x09 0x0A 0x10 0x11 0x12 0x13 ...

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... XS1-U16A-128-FB217 Datasheet B.1 RAM base address: 0x00 This register contains the base address of the RAM initialized to 0x00010000. Bits Perm 0x00: 31:2 RW RAM base address 1:0 RO B.2 Vector base address: 0x01 Base address of event vectors in each resource interrupt or event, the 16 most significant bits of the destination address are provided by this register; the least signifi ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:24 RO 23: 0x03: xCORE Tile 7:0 RO boot status B.5 Security configuration: 0x05 Copy of the security register as read from OTP. 0x05: Security Bits Perm configuration 31:0 RO B.6 Ring Oscillator Control: 0x06 There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register ...

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... XS1-U16A-128-FB217 Datasheet B.8 Ring Oscillator Value: 0x08 This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset. 0x08: Bits Perm Ring 31:16 RO Oscillator Value 15:0 RO B.9 Ring Oscillator Value: 0x09 This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 0x11: Debug SPC 31:0 DRW B.13 Debug SSP: 0x12 This register contains the value of the SSP register when the debugger was called. Bits Perm 0x12: Debug SSP 31:0 DRW B.14 DGETREG operand 1: 0x13 The resource ID of the logical core whose state read. ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:18 RO 17:16 DRW 15:8 DRW 7:3 RO 2:0 DRW 0x15: Debug interrupt type B.17 Debug interrupt data: 0x16 On a data watchpoint, this register contains the effective address of the memory operation that triggered the debugger resource watchpoint, it countains the resource identifier. 0x16: Bits ...

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... XS1-U16A-128-FB217 Datasheet B.19 Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG. This is the same set of registers as the Scratch registers in the xCORE tile 0x20 .. 0x27: Debug Bits Perm scratch 31:0 DRW B.20 Instruction breakpoint address: 0x30 .. 0x33 This register contains the address of the instruction breakpoint ...

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... XS1-U16A-128-FB217 Datasheet 0x50 .. 0x53: Data Bits Perm watchpoint address 1 31:0 DRW B.23 Data watchpoint address 2: 0x60 .. 0x63 This set of registers contains the second address for the four data watchpoints. 0x60 .. 0x63: Data Bits Perm watchpoint address 2 31:0 DRW B.24 Data breakpoint control register: 0x70 .. 0x73 This set of registers controls each of the four data watchpoints ...

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... XS1-U16A-128-FB217 Datasheet 0x80 .. 0x83: Resources Bits Perm breakpoint mask 31:0 DRW B.26 Resources breakpoint value: 0x90 .. 0x93 This set of registers contains the value for the four resource watchpoints. 0x90 .. 0x93: Resources Bits Perm breakpoint value 31:0 DRW B.27 Resources breakpoint control register: 0x9C .. 0x9F This set of registers controls each of the four resource watchpoints. ...

Page 44

... XS1-U16A-128-FB217 Datasheet C xCORE Tile Configuration The xCORE Tile control registers can be accessed using configuration reads and writes (use for reads and writes). ...) Number 0x00 0x01 0x02 0x04 0x05 0x06 0x07 0x10 .. 0x13 0x20 .. 0x27 0x40 0x41 0x42 0x43 0x44 ...

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... XS1-U16A-128-FB217 Datasheet C.1 Device identification: 0x00 Bits Perm 31:24 RO 23:16 RO 0x00: 15:8 RO Device identification 7:0 RO C.2 xCORE Tile description 1: 0x01 This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile. Bits Perm 31:24 RO 23:16 RO 0x01: 15:8 RO xCORE Tile description 1 7 ...

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... XS1-U16A-128-FB217 Datasheet 0x04: Control Bits Perm PSwitch 31:1 RO permissions to debug 0 CRW registers C.5 Cause debug interrupts: 0x05 This register can be used to raise a debug interrupt in this xCORE tile. Bits Perm 31:2 RO 0x05 Cause debug interrupts 0 CRW C.6 xCORE Tile clock divider: 0x06 This register contains the value used to divide the PLL clock to create the xCORE tile clock ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:26 RO 25:24 RO 23:16 RO 15 0x10 .. 0x13 PLink status C.9 Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch. This is the same set of registers as the Debug Scratch registers in the processor 0x20 ...

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... XS1-U16A-128-FB217 Datasheet C. logical core 1: 0x41 0x41: Bits Perm PC of logical core 1 31 logical core 2: 0x42 0x42: Bits Perm PC of logical core 2 31 logical core 3: 0x43 0x43: Bits Perm PC of logical core 3 31 logical core 4: 0x44 0x44: Bits ...

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... XS1-U16A-128-FB217 Datasheet C. logical core 6: 0x46 0x46: Bits Perm PC of logical core 6 31 logical core 7: 0x47 0x47: Bits Perm PC of logical core 7 31 logical core 0: 0x60 Value of the SR of logical core 0 0x60: Bits Perm SR of logical core 0 31 logical core 1: 0x61 ...

Page 50

... XS1-U16A-128-FB217 Datasheet C. logical core 3: 0x63 0x63: Bits Perm SR of logical core 3 31 logical core 4: 0x64 0x64: Bits Perm SR of logical core 4 31 logical core 5: 0x65 0x65: Bits Perm SR of logical core 5 31 logical core 6: 0x66 0x66: Bits ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:26 RO 25:24 RO 23:16 RO 15 0x80 .. 0x9F: Chanend 0 RO status X1110, Init Description - Reserved 00 - ChannelEnd ERROR PSCTL Idle. Based on SRC_TARGET_TYPE value, it represents channelEnd ID or Idle status. - Reserved Two-bit network identifier - Reserved 1 when the current packet is considered junk and will be thrown away ...

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... XS1-U16A-128-FB217 Datasheet D Digital Node Configuration The digital node control registers can be accessed using configuration reads and writes (use for reads and writes). ...) Number 0x00 0x01 0x04 0x05 0x06 0x07 0x08 0x0C 0x0D 0x10 0x1F 0x20 .. 0x27 0x40 .. 0x43 0x80 .. 0x87 ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:24 RO 0x01: 23:16 RO System 15:8 RO switch description 7:0 RO D.3 Switch configuration: 0x04 This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode. Bits Perm 7:1 RO 0x04: Switch 0 RO configuration D.4 Switch node identifi ...

Page 54

... XS1-U16A-128-FB217 Datasheet Bits Perm 31:26 RO 25:23 RW 22: 0x06: 6:0 RW PLL settings D.6 System switch clock divider: 0x07 Sets the ratio of the PLL clock and the switch clock. Bits Perm 0x07: 31:16 RO System switch clock 15:0 RW divider D.7 Reference clock: 0x08 Sets the ratio of the PLL clock and the reference clock used by the node. ...

Page 55

... XS1-U16A-128-FB217 Datasheet Bits Perm 31:28 RW 27:24 RW 23:20 RW 19:16 RW 15:12 RW 11:8 RW 0x0C: 7:4 RW Directions 0-7 3:0 RW D.9 Directions 8-15: 0x0D This register contains eight directions, for packets with a mismatch in bits 15..8 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. Bits Perm 31:28 RW 27:24 RW 23:20 RW 19:16 RW ...

Page 56

... XS1-U16A-128-FB217 Datasheet D.11 Debug source: 0x1F Contains the source of the most recent debug event. Bits Perm 31 3:1 RO 0x1F Debug source D.12 Link status, direction, and network: 0x20 .. 0x27 These registers contain status information for low level debugging (read-only), the network number that each link belongs to, and the direction that each link is part of ...

Page 57

... XS1-U16A-128-FB217 Datasheet D.13 PLink status and network: 0x40 .. 0x43 These registers contain status information and the network number that each processor-link belongs to. Bits Perm 31:26 RO 25:24 RO 23:16 RO 15 0x40 .. 0x43: PLink status 0 RO and network D.14 Link configuration and initialization: 0x80 .. 0x87 These registers contain confi ...

Page 58

... XS1-U16A-128-FB217 Datasheet Bits Perm 29: 0x80 .. 0x87: 21:11 RW Link configuration and 10:0 RW initialization D.15 Static link configuration: 0xA0 .. 0xA7 These registers are used for static (ie, non-routed) links. When a link is made static, all traffic is forwarded to the designated channel end and no routing is attempted. ...

Page 59

... XS1-U16A-128-FB217 Datasheet E Analogue Node Configuration The analogue node control registers can be accessed using configuration reads and writes (use for reads and writes). ...) Number 0x00 0x04 0x05 0x50 0x51 0x80 0xD6 Figure 36: Summary 0xD7 E.1 Device identification register: 0x00 This register contains version information, and information on power-on behavior. ...

Page 60

... RW identifier E.4 Reset and Mode Control: 0x50 The XS1-S has two main reset signals: a system-reset and an xCORE Tile-reset. System-reset resets the whole system including external devices, whilst xCORE Tile-reset resets the xCORE Tile(s) only. The resets are induced either by software (by a write to the register below one of the following: ...

Page 61

... XS1-U16A-128-FB217 Datasheet Bits Perm 31: 23:18 RO 17: 0x50: Reset and Mode Control E.5 System clock frequency: 0x51 Bits Perm 31:7 RO 6:0 RW 0x51: System clock frequency X1110, Init Description - Reserved Tristate processor mode pins. - Reserved Processor mode pins. - Reserved 0 USB peripheral register access enable. ...

Page 62

... XS1-U16A-128-FB217 Datasheet E.6 Link Control and Status: 0x80 Bits Perm 31: 21:11 RW 0x80: Link Control 10:0 RW and Status E.7 1 KHz Watchdog Control: 0xD6 The watchdog provides a mechanism to prevent programs from hanging by re- setting the xCORE Tile after a pre-set time. The watchdog should be periodically “ ...

Page 63

... XS1-U16A-128-FB217 Datasheet E.8 Watchdog Disable: 0xD7 To enable the watchdog, write 0 to this register. To disable the watchdog, write the value 0x0D1SAB1E to this register. Bits Perm 0xD7: Watchdog 31:0 RW Disable F USB PHY Configuration The USB PHY is connected to the following ports: XS1_PORT_1J Clk XS1_PORT_1K Tx ready out (Tx valid) ...

Page 64

... XS1-U16A-128-FB217 Datasheet Number 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 Figure 37: Summary 0x3C F.1 UIFM reset: 0x00 A write to this register with any data resets all UIFM state, but does not otherwise affect the phy. ...

Page 65

... XS1-U16A-128-FB217 Datasheet Bits Perm 31 0x04 UIFM IFM control 0 RW F.3 UIFM Device Address: 0x08 The device address whose packets should be received. 0 until enumeration, it should be set to the assigned value after enumeration. Bits Perm 31:7 RO 0x08: UIFM Device ...

Page 66

... XS1-U16A-128-FB217 Datasheet Bits Perm 31 0x10 UIFM 1 RW on-the-go control 0 RW F.6 UIFM on-the-go flags: 0x14 Status flags used for on-the-go negotiation Bits Perm 31 0x14 UIFM 1 RO on-the-go flags 0 RO X1110, Init Description ...

Page 67

... XS1-U16A-128-FB217 Datasheet F.7 UIFM Serial Control: 0x18 Bits Perm 31 0x18 UIFM Serial Control 0 RW F.8 UIFM signal flags: 0x1C Set of flags that monitor line and error states. These flags normally clear on the next packet, but they may be made sticky by using PER_UIFM_FLAGS_STICKY, in which they must be cleared explicitly ...

Page 68

... XS1-U16A-128-FB217 Datasheet Bits Perm 0x20: 31:7 RO UIFM Sticky flags 6:0 RW F.10 UIFM port masks: 0x24 Set of masks that identify how port 1N, port 1O and port 1P are affected by changes to the flags in FLAGS Bits Perm 31:23 RO 22: 14 0x24: 6:0 RW UIFM port masks F.11 UIFM SOF value: 0x28 USB Start-Of-Frame counter ...

Page 69

... XS1-U16A-128-FB217 Datasheet Bits Perm 31:4 RO 0x2C: UIFM PID 3:0 RO F.13 UIFM Endpoint: 0x30 The last endpoint seen Bits Perm 31:5 RO 0x30 UIFM Endpoint 3:0 RO F.14 UIFM Endpoint match: 0x34 This register can be used to mark UIFM endpoints as special. Bits Perm 31:16 RO 0x34: UIFM 15:0 RW Endpoint match F.15 UIFM power signalling: 0x38 ...

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... XS1-U16A-128-FB217 Datasheet F.16 UIFM PHY control: 0x3C Bits Perm 31: 17: 11 0x3C: 6:4 RW UIFM PHY control 3 ADC Configuration The device has a 12-bit Analogue to Digital Converter (ADC). It has multiple input pins, and on each positive clock edge on port 1I, it samples and converts a value on the next input pin ...

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... XS1-U16A-128-FB217 Datasheet G.1 ADC Control input pin 0: 0x00 Controls specific to ADC input pin 0. Bits Perm 31:8 RW 0x00: 7:1 RO ADC Control input pin G.2 ADC Control input pin 1: 0x04 Controls specific to ADC input pin 1. Bits Perm 31:8 RW 0x04: 7:1 RO ADC Control input pin G.3 ADC Control input pin 2: 0x08 Controls specifi ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:8 RW 0x0C: 7:1 RO ADC Control input pin G.5 ADC Control input pin 4: 0x10 Controls specific to ADC input pin 4. Bits Perm 31:8 RW 0x10: 7:1 RO ADC Control input pin G.6 ADC Control input pin 5: 0x14 Controls specific to ADC input pin 5. Bits ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:8 RW 0x18: 7:1 RO ADC Control input pin G.8 ADC Control input pin 7: 0x1C Controls specific to ADC input pin 7. Bits Perm 31:8 RW 0x1C: 7:1 RO ADC Control input pin G.9 ADC General Control: 0x20 General ADC control. X1110, Init Description 0 The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifi ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31: 23:18 RO 17:16 RW 15 0x20: ADC General Control H Deep sleep memory Configuration This peripheral contains a 128 byte RAM that retains state whilst the main processor is put to sleep. The Deep sleep memory is peripheral 3. The control registers are accessed using 8-bit reads and writes (use (device, 3, ...

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... XS1-U16A-128-FB217 Datasheet Number 0x00 .. 0x7F Figure 39: Summary 0xFF H.1 Deep sleep memory: 0x00 .. 0x7F 128 bytes of memory that can be used to hold data when the xCORE Tile is powered down. 0x00 .. 0x7F: Deep sleep Bits Perm memory 7:0 RW H.2 Deep sleep memory valid: 0xFF One byte of memory that is reset to 0. The program can write a non zero value in this register to indicate that the data in deep sleep memory is valid ...

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... XS1-U16A-128-FB217 Datasheet I.1 General oscillator control: 0x00 Bits Perm 7 0x00: General 0 RW oscillator control I.2 On-silicon-oscillator control: 0x01 This register controls the on-chip logic that implements an on-chip oscillator. The on-chip oscillator does not require an external crystal, but does not provide an accurate timing source. The nominal frequency of the on-silicon-oscillator is given below, but the actual frequency are temperature, voltage, and chip dependent ...

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... XS1-U16A-128-FB217 Datasheet J Real time clock Configuration The Real time clock is peripheral 5. The control registers are accessed using 32-bit reads and writes (use for reads and writes). 5, ...) Number 0x00 Figure 41: Summary 0x04 J.1 Real time counter least significant 32 bits: 0x00 This registers contains the lower 32-bits of the real-time counter. ...

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... XS1-U16A-128-FB217 Datasheet Number 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x2C 0x30 0x34 Figure 42: Summary 0x40 K.1 General control: 0x00 This register controls the basic settings for power modes. X1110, Perm Description RW General control RW Time to wake-up, least significant 32 bits RW Time to wake-up, most signifi ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31: 0x00 General control K.2 Time to wake-up, least significant 32 bits: 0x04 This register stores the time to wake-up. The value is only used if wake-up from the real-time clock is enabled, and the device is asleep. ...

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... XS1-U16A-128-FB217 Datasheet 0x08: Time to wake-up, Bits Perm most significant 32 31:0 RW bits K.4 Power supply states whilst ASLEEP: 0x0C This register controls the state the power control block should be in when in the ASLEEP state. It also defines the minimum time that the system shall stay in this state ...

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... XS1-U16A-128-FB217 Datasheet K.5 Power supply states whilst WAKING1: 0x10 This register controls what state the power control block should be in when in the WAKING1 state. It also defines the minimum time that the system shall stay in this state. When the minimum time is expired, the next state is entered if all enabled power supplies are good ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:21 RO 20: 13: 7 0x14: 3:2 RO Power supply 1 RO states whilst WAKING2 0 RW K.7 Power supply states whilst AWAKE: 0x18 This register controls what state the power control block should be in when in the AWAKE state. ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31: 13: 7 0x18: 3:2 RO Power supply 1 RO states whilst AWAKE 0 RW K.8 Power supply states whilst SLEEPING1: 0x1C This register controls what state the power control block should be in when in the SLEEPING1 state. It also defines the time that the system shall stay in this state. ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:21 RO 20: 13: 7 0x1C: 3:2 RO Power supply 1 RO states whilst SLEEPING1 0 RW K.9 Power supply states whilst SLEEPING2: 0x20 This register controls what state the power control block should be in when in the SLEEPING2 state. It also defines the time that the system shall stay in this state. ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:21 RO 20: 13: 7 0x20: 3:2 RO Power supply 1 RO states whilst SLEEPING2 0 RW K.10 Power sequence status: 0x24 This register defines the current status of the power supply controller. X1110, Init Description - Reserved 16 Log2 number of cycles to stay in this state: ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31: 27: 23:19 RO 18: 13: 7 0x24: 3:2 RO Power 1 RO sequence status 0 RO K.11 DCDC control: 0x2C This register controls the two DC-DC converters. X1110, Init Description - Reserved VOUT6 was enabled in the previous state. ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:26 RO 25:24 RW 23: 14:13 RW 12: 6:5 RW 4:2 RO 1:0 RW 0x2C: DCDC control K.12 Power supply status: 0x30 This register provides the current status of the power supplies. X1110, Init Description - Reserved 2 Sets the power good level for VDDCORE and VDD1V8: 0: 0.80 x VDDCORE, 0.80 x VDD1V8 1: 0 ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31: 23: 18: 15: 7:2 RO 0x30 Power supply status 0 RO K.13 VDDCORE level control: 0x34 This register can be used to set the desired voltage on VDDCORE. If the level raised or lowered, it should be raised in steps of no more than 10 mV per microsecond in order to prevent overshoot and undershoot ...

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... XS1-U16A-128-FB217 Datasheet Bits Perm 31:3 RO 2:0 RW 0x40: LDO5 level control X1110, Init Description - Reserved pin The required voltage in 100 mV steps: 0: 0.6V 1: 0.7V 2: 0.8V ... 6: 1.2V 7: 1.3V 88 ...

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... Programming XC on XMOS Devices xTIMEcomposer User Guide M Related Documentation Document Title The XMOS XS1 Architecture XS1 Port I/O Timing XS1-L System Specification XS1-L Link Performance and Design Guidelines XS1-L Clock Frequency Control X1110, Information Timers, ports, clocks, cores and channels Compilers, assembler and ...

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... XS1-U16A-128-FB217 Datasheet N Revision History Date Description 2013-01-30 New datasheet - revised part numbering 2013-02-26 New multicore microcontroller introduction Moved configuration sections to appendices 2013-03-27 Added connection details for USB_VBUS/USB_ID - Section VDDCORE parameters - Section 2013-04-04 Added ADC control pin configuration details 4-7 - Section ...

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