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FMS1616LAX-XXEX Datasheet - Page 8

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sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used
in conjunction with the BURST TERMINATE command to gene-
rate arbitrary burst lengths. Reserved states should not be used,
as unknown operation or incompatibility with future versions
may result. When a READ or WRITE command is issued, a
block of columns equal to the burst length is effectively select-
ed. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A7 when the
burst length is set to two; by A2-A7 when the burst length is
set to four; and by A3-A7 when the burst length is set to eight.
M11-
M10-
M9-A9
M8-A8
BA
A10
Reserved(Set to ‘0’)
WB
M2 M1 M0
M3=0
0 0 0
1
0 0 1
2
0 1 0
4
0 1 1
8
1 0 0
Reserved
1 0 1
Reserved
1 1 0
Reserved
1 1 1
Full Page
M6 M5 M4
CAS Latency
0 0 0
Reserved
0 0 1
1
0 1 0
2
0 1 1
3
1 0 0
Reserved
1 0 1
Reserved
1 1 0
Reserved
1 1 1
Reserved
Note :
4.
For full-page accesses: y = 256
5.
For a burst length of two, A1-A7 select the block-of-two burst; A0 selects the starting column within the block.
6.
For a burst length of four, A2-A7 select the block-of-four burst; A0-A1 select the starting column within the block.
7.
For a burst length of eight, A3-A7 select the block-of-eight burst; A0-A2 select the starting column within the block.
8.
For a full-page burst, the full row is selected and A0-A7 select the starting column.
9.
Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
10.
For a burst length of one, A0-A7 select the unique column to be accessed,and mode register bit M3 is ignored.
Table 1. Mode Register Definition.
Rev0.3, May., 2010
The remaining(least significant) address bit(s) is (are) used
to select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached.
Burst Type
The burst type can be set to either Sequential or Interleaved
by using the M3 bit in the Mode register. The ordering of
accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in
Table 2.
[4.5.6.7.8.9.10.]
M7-A7
M6-A6
M5-A5
M4-A4
Op Mode
CAS Latency
Burst Length
M3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M8
M7
0
0
-
-
FMS1616LAx-xxEx
M3-A3
M2-A2
M1-A1
M0-A0
BT
Burst Length
M3
Burst Type
0
Sequential
1
Interleaved
M9
Write Burst Mode
0
Prog. Burst Length
1
Single Mode Access
M6-M0
Operating Mode
Defined
Standard Operation
-
All other states reserved

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