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FMS1616LAX-XXEX Datasheet - Page 39

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T0
T1
CLK
CKE
Internal
CLK
Read
NOP
Command
Bank
Address
Col n
DQ
Figure 24. Clock Suspend During Read Burst - Burst of 4 (CAS latency =2)
Concurrent Auto Precharge
If an access command with Auto Precharge is being execeuted
an access command (either a Read or Write ) is not allowed by
SDRAM’s. If this feature is allowed then the SDRAM supports
Concurrent Auto Precharge. Coremagic SDRAMs support
Concurrent Auto Precharge. Four casees where Concurrent
Auto Precharge occurs are defined below.
Read With Auto Precharge
1.Interrupted by a Read(with or without auto precharge): A read
to bank m will interrupt a Read on bank n, CAS latency later.
The precharge to bank n will begin when the Read to bank m is
registered. (Figure 25. )
2. Interrupted by a Write(with or without auto precharge): A
Write to bank m will interrupt a Read on bank n when registered.
Rev0.3, May., 2010
T2
T3
T4
NOP
NOP
Dout
Dout
n
n+1
DQM should be used two clocks prior to the Write command to
prevent bus contention. The Precharge to bank n will begin
when the write to bank m is registered. (Figure 26. )
Write with Auto Precharge
3. Interrupted by a Read(with or without auto precharge): A
Read to bank m will interrupt a Write on bank n when regis-
tered , with the data-out appearing CAS latency later. The Pre-
charge to bank n will begin after t
when the Read to bank m is registered. The last valid Write to
bank n will be data-in registered one clock prior to the Read to
bank m.(Figure 27. )
4. Interrupted by a Write ( with or without auto Precharge): A
Write to bank m will interrupt a Write on bank n when registered.
The Precharge to bank n will begin after t
begins when the Write to bank m is registered. The latest valid
data Write to bank n will be data registered one clock prior to a
Write to bank m.( Figure 28. )
FMS1616LAx-xxEx
T5
T6
NOP
NOP
Dout
Dout
n+2
n+3
is met, where t
begins
WR
WR
is met ,where t
WR
WR

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