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FMS1616LAX-XXEX Datasheet - Page 28

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CLOCK
CKE
/CS
t
RCD
/RAS
/CAS
ADDR
RAa
CAa
BA
A10/AP
RAa
CL=2
t
RAC
*note 47.
DQ
CL=3
t
RAC
*note 47.
/WE
DQM
Row Active
Read
(A-Bank)
(A-Bank)
Note :
45. Minimum row cycle times is required to complete internal DRAM operation.
46. Row precharge can interrupt burst on any cycle.[CAS Latency -1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t
the clock.
47. Access time from Row active command. t
CC
48. Out put will be Hi-Z after the end of burst. (1,2,3,8 & Full page bit burst)
Figure 11. Read & Write Cycle at Same Bank @Burst Length=4, t
Rev0.3, May., 2010
5
6
7
8
9
10
11
HIGH
*note 45.
t
RC
t
RP
*note 46.
RAb
t
OH
Qa0
Qa1
Qa2
Qa3
t
t
*note 48.
AC
HZ
t
OH
Qa0
Qa1
Qa2
Qa3
t
t
*note 48.
AC
HZ
Precharge
Row Active
(A-Bank)
(A-Bank)
*(t
+ CAS latency - 1) + t
RCD
AC
FMS1616LAx-xxEx
12
13
14
15
16
17
18
CAb
RAb
Qb0
Qb1
Qb2
Qb3
t
DPL
Qb0
Qb1
Qb2
Qb3
t
DPL
Write
Precharge
(A-Bank)
(A-Bank)
Don’t Care
=2CLK
DPL
19
) after
SHZ

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