Datasheets»Fidelix»FMS1616LAX-XXEX Datasheet

FMS1616LAX-XXEX Datasheet - Page 22

Download or read online Fidelix FMS1616LAX-XXEX 16m 1mx16 Low Power Sdram pdf datasheet.



Page
22 of 46
prevnext
T0
CLK
Command
Read
Bank
Address
Col n
DQ
CAS Latency=2
T0
CLK
Command
Read
Read
Bank
Bank
Address
Col n
Col a
DQ
Figure 5. Random Read Accesses for CAS Latency =1,2,3
A Read Burst can be terminated by a subsequent Write com-
mand, and data from a fixed length READ burst may be
immediately followed by data from a WRITE command (subject
to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last
desired) data element from the READ burst, provided that I/O
contention can be avoided. In a given system design, there may
be a possibility that the device driving the input data will go
Low-Z before the SDRAM DQs go High-Z. In this case, at least
Rev0.3, May., 2010
T2
T3
T1
Read
Read
Read
Bank
Bank
Bank
Col a
Col x
Col m
Dout
Dout
n
T2
T3
T1
Read
Read
Bank
Bank
Col x
Col m
Dout
n
CAS Latency=3
a single-cycle delay should occur between the last read data
and the WRITE command. The DQM input is used to avoid I/O
contention, as shown in Figure 6. and Figure 7. . The DQM
signal must be asserted (HIGH) at least two clocks prior to the
WRITE command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE comma-
nd is registered, the DQs will go High-Z (or remain High-Z),
regardless of the state of the DQM signal, provided the DQM
FMS1616LAx-xxEx
T4
T5
NOP
NOP
Dout
Dout
a
x
m
T4
T5
T6
NOP
NOP
NOP
Dout
Dout
Dout
a
x
m

Comments to this Datasheet