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FMS1616LAX-XXEX Datasheet - Page 16

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Table 8. I
Specifications and Conditions
DD
Parameter
Operating Current : Active Mode ; Burst =1 ; Read or Write ; t
I
1
DD
CAS Latency =3
[28.29.30.]
,tCK=10ns
I
2p
Precharge Standby Current in Power Down Mode ; CKE=LOW ; All banks Idle, tCK=10ns
DD
I
2n
Precharge Standby Current in non Power down Mode; CKE=HIGH ; All banks Idle,tCK=10ns
DD
Active Standby Current in Power Down Mode ; CS#=HIGH ; CKE=LOW ; All
I
3p
DD
banks active after t
met ; No access in progress
RCD
Active Standby Current in non Power Down Mode ; CS#=HIGH ; CKE=HIGH ; All
I
3n
DD
banks active after t
met ; No access in progress
RCD
Operating Current : Burst Mode ; Continuous Burst ; Read or Write ; All banks
I
4
DD
Active ; CAS Latency =3
[28.29.30.]
I
5
Auto Refresh Current : t
=t
DD
RC
Self Refresh Current : CKE <=0.2V, 2 Banks
I
6
DD
Self Refresh Current : CKE <=0.2V, 1 Banks
I
7
Deep power down
DD
Note :
21. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-25°C = TA = +85°C for Ex parts) is ensured.
22. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (V
powered up simultaneously. V
and V
must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the t
SS
SSQ
requirement is exceeded.
23. All states and sequences not shown are illegal or reserved.
24. In addition to meeting the transition rate specification, the clock and CKE must transit between V
25. t
defines the time at which the output achieves the open circuit condition; it is not a reference to V
HZ
26. AC timing and I
tests have V
and V
, with timing referenced to V
DD
IL
IH
at V
(MAX) and V
(MIN) and no longer at the V
IL
IH
27. I
specifications are tested after the device is properly initialized.
DD
28. I
is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
DD
29. The I
current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.
DD
30. Address transitions average one transition every two clocks.
31. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid V
32. CKE is HIGH during refresh command period t
RFC
Capacitance
Parameter
C
IN
C
OUT
AC Test Loads
Z0=50Ω
OUTPUT
Rev0.3, May., 2010
[21.22.26.27.]
.
Description
= t
(min);
RC
RC
, tCK=10ns
[28.30.31.]
[28.30.31.]
, tCK=10ns
, tCK=10ns
(min) CAS Latency=3 ; CKE,CS#=HIGH
RC
and V
IH
or V
OH
= crossover point. If the input transition time is longer than t
IH/2
crossover point.
IH/2
(MIN) else CKE is LOW. The I
6 limit is actually a nominal value and does not result in a fail value
DD
Description
Test Conditions
Input Capacitance
T
=25℃, f=1Mhz, V
A
Output Capacitance
VDDQ/2
50Ω
30pF
FMS1616LAx-xxEx
-60
-75
40
30
200
5.5
1.5
12
60
50
[28.29.30.32.32.]
, tCK=10ns
45
150
140
10
and V
must be
DD
DDQ
refresh
REF
(or between V
and V
) in a monotonic manner.
IL
IL
IH
. The last valid data element will meet t
before going High-Z.
OL
OH
(MAX), then the timing is referenced
T
or V
levels.
IH
IL
Max
4
DD(typ)
6
Units
Units
pF
pF

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