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FMS1616LAX-XXEX Datasheet - Page 14

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AUTO REFRESH is used during normal operation of the
SDRAM. This command is nonpersistent, so it must be issued
each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command.
The AUTO REFRESH command should not be issued until the
minimum t
has been met after the PRECHARGE command.
The addressing is generated by the internal refresh controller.
The address bits thus are a “Don’t Care” during an AUTO
REFRESH command. The Coremagic 16Mb SDRAM requires
2,048 AUTO REFRESH cycles every 32ms (t
of width option. Providing a distributed AUTO REFRESH
command every 15.625µs will meet the refresh requirement and
ensure that each row is refreshed.
Alternatively, 2,048 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (t
), once every 32ms.
The SELF REFRESH command can be used to retain data in
the SDRAM(without external clocking), even if the rest of the
system is powered down. The SELF REFRESH command is
initiated like an AUTO REFRESH command except CKE is
disabled (LOW). Once the SELF REFRESH command is reg-
istered, all the inputs to the SDRAM become “Don’t Care” with
the exception of CKE, which must remain LOW. Once self
refresh mode is engaged, the SDRAM provides its own internal
clocking, causing it to perform its own AUTO REFRESH cycles.
The SDRAM must remain in self refresh mode for a minimum
period equal to t
and may remain in self refresh mode for
an indefinite period beyond that. The procedure for exiting self
refresh requires a sequence of commands. First, CLK must be
stable (meet the clock specifications in the AC characteristics)
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two clocks)
for t
because time is required for the completion of any
internal refresh in progress. Upon exiting the self refresh mode,
AUTO REFRESH commands must be issued every 15.625µs or
less as both SELF REFRESH and AUTO REFRESH utilize he
row refresh counter.
Rev0.3, May., 2010
Deep Power Down Mode is an operating mode to achieve maximum
power reduction by cutting the power of the whole memory array of
the device.
Data will not be retained once the device enters DPD Mode.
Full initialization is required when the device exits from DPD Mode.
The DC value of DPD Mode can’t be zero due to transistor’s leakage
current; a reverse PN diode leakage current which is called ‘Junction
leakage current’ and a punch-through leakage current.
), regardless

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