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FMS1616LAX-XXEX Datasheet

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FMS1616LAx-xxEx
16M(1Mx16) Low Power SDRAM
Revision 0.3
May., 2010
Rev0.3, May., 2010

Summary of Contents

Page 1

... Low Power SDRAM Rev0.3, May., 2010 Revision 0.3 May., 2010 FMS1616LAx-xxEx ...

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... Document Title 16M(1Mx16) Low Power SDRAM Revision History Revision No. 0.0 Initial Draft Revised Package type 0.1 Revised Typo 0.2 Add IDD2P/6 level 0.3 Revised tOH Rev0.3, May., 2010 History FMS1616LAx-xxEx Draft date Remark Sep.25 , 2009 Preliminary th Jan. 2010 Preliminary Mar 2010 Final May ...

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... FMS1616LAH : Lead Free & Halogen Free - Wafer - FMS1616LAW Functional Description The FMS1616LAx-xxEx family is high-performance CMOS Dynamic RAMs (DRAM) organized 16. These devices feature advanced circuit design to provide ultra-low active current and extremely low standby current.This is ideal for providing More Battery Life in portable applications such as wireless handsets ...

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... DQ15 V SSQ DQ13 V DDQ DQ11 V SSQ DQ9 V DDQ CLK CKE FMS1616LAx-xxEx DQ0 DDQ DD V DQ1 DQ2 SSQ V DQ3 DQ4 DDQ V DQ5 DQ6 SSQ V DQ7 LDQM DD /CAS /RAS / / ...

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... BA (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output : Data bus No Connect DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: Voltage dependent on option. Ground. FMS1616LAx-xxEx Description ...

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... The following sections pro- vide detailed information regarding device initialization, register definition, command descriptions and device operation. Rev0.3, May., 2010 FMS1616LAx-xxEx Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to ...

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... Read and write accesses to the SDRAM are burst oriented. The burst length is programmable, as shown in Table 2. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, locations are available for both the FMS1616LAx-xxEx [1.2.3 ...

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... Table 2. [4.5.6.7.8.9.10.] M7-A7 M6-A6 M5-A5 M4-A4 Op Mode CAS Latency Burst Length M3 Reserved Reserved Reserved Reserved FMS1616LAx-xxEx M3-A3 M2-A2 M1-A1 M0-A0 BT Burst Length M3 Burst Type 0 Sequential 1 Interleaved M9 Write Burst Mode 0 Prog. Burst Length 1 Single Mode Access M6-M0 Operating Mode Defined Standard Operation - All other states reserved ...

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... Write Burst Mode When M90, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M91, the programmed burst length applies to READ bursts, but write accesses are single-location (non-burst) accesses. FMS1616LAx-xxEx Order of Accesses within a Burst TypeInterleaved 0-1 0-1 1-0 ...

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... CLK Command Read DQ Rev0.3, May., 2010 T0 T1 Read NOP Dout t AC CAS Latency Read NOP NOP CAS Latency NOP NOP t LZ CAS Latency3 Figure 2. CAS Latency FMS1616LAx-xxEx Dout T3 T4 NOP t OH Dout t AC ...

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... The driver strength feature allows one to reduce the drive strength of the I/Os on the device during low frequency operation. This allows systems to reduce the noise associated with the I/Os switching. EM7- EM6- EM5- EM4 Driver Strength FMS1616LAx-xxEx EM3- EM2- EM1- EM0 PASR . ...

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... RFU Address MSB0) Address 2 MSB0) RFU CKE / [16 [16 [17 [18. 19 FMS1616LAx-xxEx A6 A5 Driver Strength 0 0 100 75 50 25% /RAS /CAS /WE DQM ADDR Bank/ ...

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... DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. Rev0.3, May., 2010 FMS1616LAx-xxEx WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location ...

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... Data will not be retained once the device enters DPD Mode. Full initialization is required when the device exits from DPD Mode. The DC value of DPD Mode cant be zero due to transistors leakage current; a reverse PN diode leakage current which is called Junction leakage current and a punch-through leakage current. [Figure29.30] ), regardless REF FMS1616LAx-xxEx ...

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... Symbol DDQ OUT DDQ OZ [21.22.23.24.25.26.] Symbol FMS1616LAx-xxEx DDQ 1.7V to 1.95V [21,22] Min Max Units 1.7 1.95 V 1.7 1. 0.3 V DDQ DDQ -0.3 0.2V V DDQ 0. DDQ 0.1V ...

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... IH/2 (MIN) else CKE is LOW. The I 6 limit is actually a nominal value and does not result in a fail value DD Description Test Conditions Input Capacitance T 25, f1Mhz Output Capacitance VDDQ/2 50Ω 30pF FMS1616LAx-xxEx -60 - 200 5.5 1 [28.29.30.32.32.] , tCK10ns 45 150 140 ...

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... HZ t RAS RCD t REF t RFC RRD XSR [38.] t CCD [39.] t CKED [39.] t PED t DQD t DQM [38.] t DQZ t DWD t DAL t DPL t BDL FMS1616LAx-xxEx -60 -75 Min Max Min Max 6.0 7.5 1000 1000 10 12 2.5 3.0 2.5 3.0 1.5 2.0 1.0 1.0 1.5 2.0 1.0 1.0 5 1.0 1.0 2.0 2.0 1.8 1.5 2.0 1.0 1.0 1.5 2.0 1.0 1.0 5 100000 48 120000 60 75 ...

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... Timing actually specified 42. JEDEC and PC100 specify three clocks. Rev0.3, May., 2010 Symbol [38.] t CDL t RDL t [42.] MRD CL3 t (3) ROH [38.] CL2 t (2) ROH CL1 t (1) ROH FMS1616LAx-xxEx -60 -75 Units Min Max Min Max ...

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... Full-speed random read . RRD accesses can be performed to the same bank, as shown in Figure each subsequent READ may be performed to a different bank. High Column Address Enable Auto Precharge Disable Auto Precharge Bank Address Dont Care Figure 3. Read Command FMS1616LAx-xxEx ...

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... Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 Rev0.3, May., 2010 NOP NOP NOP Dout Dout Dout n n1 n NOP NOP Dout Dout n n1 CAS Latency2 FMS1616LAx-xxEx T4 T5 Read NOP X0cycles Bank Col b Dout Dout n X1cycles Read NOP NOP Bank Col b Dout Dout Dout ...

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... Bank Col b Dout n CAS Latency Read Read Read Bank Bank Bank Col a Col x Col m Dout Dout n a CAS Latency1 Figure 5. Random Read Accesses for CAS Latency 1,2,3 FMS1616LAx-xxEx NOP NOP X2cycles Dout Dout Dout n1 n2 n NOP Dout Dout NOP ...

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... WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE comma registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM FMS1616LAx-xxEx T4 T5 NOP NOP ...

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... CAS Latency3 Rev0.3, May., 2010 allows for bus contention to be avoided without adding a NOP cycle, and Figure 7. shows the case where the additional NOP is needed NOP NOP NOP t HZ Dout n Figure 6. Read to Write FMS1616LAx-xxEx T4 Write Bank Col b Din ...

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... Figure 7. Read to Write with extra clock cycle Read masked by write Din Din Din n1 n3 n n2 Write Read masked by DQM Din Din n1 n Write Read CAS2 Dout Din n n FMS1616LAx-xxEx T4 T5 NOP Write Bank Col b Din Din Din n3 n2 Din Din Din n1 n3 n2 ...

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... T3 T4 NOP NOP Precharge X0cycles Bank (a or all) Dout Dout Dout n1 n2 n NOP NOP Precharge X1cycles Bank (a or all) Dout Dout Dout n n1 n2 Figure 9. Read to Precharge FMS1616LAx-xxEx NOP NOP Active Bank a Row NOP NOP Active Bank a Row Dout n3 ...

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... NOP NOP Precharge X2cycles Bank (a or all) Dout Dout n n1 CAS Latency3 Figure 9. Read to Precharge Burst NOP NOP Terminate X0cycles Dout Dout Dout n1 n2 n3 Figure 10. Terminating a Read Burst FMS1616LAx-xxEx NOP NOP Active Bank a Row Dout Dout n2 n NOP NOP NOP ...

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... Col n DQ Rev0.3, May., 2010 Burst NOP NOP Terminate X1cycles Dout Dout Dout n n1 n Burst NOP NOP Terminate X2cycles Dout Dout n n1 CAS Latency3 Figure 10. Terminating a Read Burst FMS1616LAx-xxEx NOP NOP NOP Dout n NOP NOP NOP Dout Dout n2 n3 ...

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... Qa3 t t note 48 Qa0 Qa1 Qa2 Qa3 t t note 48 Precharge Row Active (A-Bank) (A-Bank) (t CAS latency - RCD AC FMS1616LAx-xxEx CAb RAb Qb0 Qb1 Qb2 Qb3 t DPL Qb0 Qb1 Qb2 Qb3 t DPL Write Precharge (A-Bank) (A-Bank) Don’ ...

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... OH Qa0 Qa1 Qa2 Qa3 t t note 48 Qa0 Qa1 Qa2 Qa3 Precharge Row Active (A-Bank) (A-Bank) FMS1616LAx-xxEx CAb Qb0 Qb1 Qb2 Qb3 t Qb0 Qb1 Qb2 Qb3 note 48. t Write (A-Bank) Dont Care 2CLK DPL ...

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... QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 Read (B-Bank) Precharge Precharge (A-Bank) (B-Bank) before Row precharge, will be written. DPL in Figure 14. The starting column and bank addresses are provided with the WRITE command, and auto precharge is FMS1616LAx-xxEx Dont Care 19 ...

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... WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 17 each subsequent WRITE may be performed to a different bank. High Column Address Enable Auto Precharge Disable Auto Precharge Bank Address Dont Care Figure 14. Write Command FMS1616LAx-xxEx ...

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... PRECHARGE command. An example is shown in Figure 19. Data either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. RP FMS1616LAx-xxEx T3 NOP T2 b ...

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... Figure 18. Write to Read Burst of 2 Write and Read(CAS Latency 2) Rev0.3, May., 2010 T1 T2 Write Write Bank Bank Col a Col x Din Din a x Figure 17. Random Write Cycles NOP Read NOP Bank Col b Din n1 FMS1616LAx-xxEx T3 Write Bank Col m Din NOP NOP Dout Dout b b1 ...

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... Bank (Address) Col n Din n Figure 20. Terminating a Write Burst TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE FMS1616LAx-xxEx T5 T6 NOP NOP NOP Active Bank a Row ...

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... Care. Once a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Rev0.3, May., 2010 FMS1616LAx-xxEx POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down ...

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... Precharge Command CLK CKE /CS /RAS /CAS /WE A0-A9 A10 BA Rev0.3, May., 2010 High All banks Bank Selected Bank Address Dont Care Figure 21. Precharge Command FMS1616LAx-xxEx ...

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... The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. READ commands access columns according to the programmed burst length and sequence. FMS1616LAx-xxEx Active t RCD t ...

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... T0 CLK CKE Internal CLK NOP Command Address DQ Rev0.3, May., 2010 Write Bank Col n Din n Figure 23. Clock Suspend During Write Burst FMS1616LAx-xxEx T4 T5 NOP NOP Din Din n1 n2 ...

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... Write to bank m will interrupt a Write on bank n when registered. The Precharge to bank n will begin after t begins when the Write to bank m is registered. The latest valid data Write to bank n will be data registered one clock prior to a Write to bank m.( Figure 28. ) FMS1616LAx-xxEx T5 T6 NOP NOP ...

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... CAS Latency3(Bank n) CAS Latency3(Bank Write NOP NOP NOP Bank m Interrupt Burst, Precharge Write with Burst of 4 Bank m Col d Dout Din Din a d d1 FMS1616LAx-xxEx NOP NOP t - Bank m RP Idle Precharge Dout Dout Dout a NOP NOP ...

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... CAS Latency3(Bank Write-AP NOP NOP NOP Bank m t -Bank n WR Interrupt Burst, Write-Bank Write with Burst of 4 Bank m Col d Din Din Din Din a1 a2 d d1 FMS1616LAx-xxEx NOP NOP t - Bank m RP Precharge Precharge Dout Dout d d NOP NOP t -Bank n RP Precharge ...

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... Deep Power Down Entry Figure 29. Deep Power Down Mode Entry Precharge NOP AREF All Bank A10 t RP Precharge All Bank Figure 30. Deep Power Down Mode Exit FMS1616LAx-xxEx NOP NOP Active MRS EMRS Bank a Key Key Row Normal Extended Row Active MRS ...

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... Read w/Auto Precharge Enabled: RCD RCD has been met. Once met. Once t RC has been met. Once t MRD is met. Once t RP FMS1616LAx-xxEx Command Action Maintain Power Down X Maintain Self Refresh X Maintain Clock Suspend ...

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... WRITE (Select column and start WRITE burst PRECHARGE [76 ACTIVE (Select and activate row READ (Select column and start READ burst WRITE (Select column and start new WRITE burst PRECHARGE [76.] FMS1616LAx-xxEx Command(Action) [66.] [66.] [64.] [66.] [66.] [64.] [65.] [66.] [66.] [64.] [65.] Command(Action) [74.] [74.] [74.78.] [74.79.] [74 ...

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... RP is met, where t begins when the READ to bank m is registered. The last valid WRITE to bank n will met, where t begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one WR FMS1616LAx-xxEx Command(Action) [74.75.81.] [74.75.82.] [76.] [74.75.83.] [74.75.84.] [76.] has been met. No data RCD has been met ...

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... Top View # Side View Rev0.3, May., 2010 FMS1616LAx-xxEx Unit : millimeters Bottom View E/2 Unit : mm - Min Typ Max 1.20 A1 0.30 0. ...

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