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SH69P26K Datasheet

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Features
SH6610D-based single-chip 4-bit micro-controller
OTPROM: 6k X 16 bits
RAM: 389 X 4 bits
- 69 System control register
- 320 Data memory
Operation voltage:
- f
= 30kHz - 4MHz, V
= 2.4V - 5.5V
OSC
DD
- f
= 4MHz - 8MHz, V
= 4.5V - 5.5V
OSC
DD
29 CMOS bi-directional I/O pins
8-level stack (including interrupts)
Two 8-bit auto re-loaded timer/counter, one can switch to
external clock source
Warm-up timer
Built-in pull-high for I/O port
Powerful interrupt sources:
- Timer0 interrupt
- Timer1 interrupt
- Timer2 interrupt
- External interrupts: PORTF (Falling edge), CMPOUT
Oscillator (code option)
- Crystal oscillator: 32.768kHz, 400kHz - 8MHz
General Description
The SH69P26 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, 6K words of OTPROM, 389
nibbles of RAM, two 8-bit timer/counter and one 16-bit timer/counter, comparator, two channel tone generators, on-chip
oscillator clock circuitry, on-chip watchdog timer, low voltage reset function. The SH69P26 is suitable for microwave oven
application.
OTP 6K 4-Bit Micro-controller
- Ceramic resonator: 400kHz - 8MHz
- External RC oscillator: 400kHz - 8MHz
- Internal RC oscillator: 2MHz, 4MHz, 6MHz
- External clock: 30kHz - 8MHz
Instruction cycle time (4/f
OSC
Two low power operation modes: HALT and STOP
Reset:
- Built-in watchdog timer (code option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR)
Two-level Low Voltage Reset (LVR) (code option)
One 16-bit timer/counter for pulse measurement
LED numeric display drive capability on PORTA, PORTB,
PORTD and PORTH [1:0]
Built-in one comparator
Read ROM Table function
2 channels Tone generator
Internal reliable reset circuit
OTP type/code protection
28-pin SKINNY/28-pin SOP/32-pin DIP package
1
SH69P26
)
V2.2

Summary of Contents

Page 1

Features SH6610D-based single-chip 4-bit micro-controller OTPROM bits RAM: 389 X 4 bits - 69 System control register - 320 Data memory Operation voltage 30kHz - 4MHz 2.4V - 5.5V OSC DD - ...

Page 2

Pin Configuration (32-Lead DIP Package) PORTG.2/CMPP4 1 PORTG.3/CMPP3 2 PORTE.3/CMPP2 3 PORTE.2/CMPP1 4 PORTE.1/CMPN 5 PORTE.0/CMPOUT 6 PORTC.2/ RESET GND 9 PORTA.0 10 PORTA.1 11 PORTA.2 12 PORTA.3 13 PORTD.0 14 PORTD.1 15 PORTH.0 16 (28-Lead SKINNY/SOP Package) ...

Page 3

Block Diagram Reset Circuit RESET RAM bits System Register RAM 320 X 4 bits Data Memory OTP ROM 6144 X 16 bits CPU V DD Power Circuit GND WDT RC Oscillator PORTC (2 bits) Watchdog Timer PORTA ...

Page 4

Pin Description Pin No. 28-pin 32-pin DIP SKINNY/SOP ...

Page 5

Pin Description (continued) Pin No. Designation 28-pin 32-pin DIP SKINNY/SOP OTP Programming Pin Description (OTP Program Mode) Pin No. Symbol 28-pin 32-pin DIP SKINNY/SOP 24 22 ...

Page 6

Function Description 1. CPU The CPU contains the following functional blocks: Program Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY), Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, and DPL) and Stacks. 1.1. PC The PC is used ...

Page 7

Configuration of System Register (continued) Address Bit3 Bit2 08 PA.3 PA.2 09 PB.3 PB.2 0A PC.3 PC.2 0B PD.3 PD.2 0C PE.3 PE.2 0D PF.3 PF.2 0E TBR.3 TBR.2 0F INX.3 INX.2 10 DPL.3 DPL.2 11 - DPM.2 12 - ...

Page 8

Configuration of System Register (continued) Address Bit3 Bit2 2A PPGCR.3 PPGCR.2 PPGCR.1 PPGCR.0 R/W 2C TV1.3 TV1.2 2D TG1EN TV1.6 2E TV2.3 TV2.2 2F TG2EN TV2.6 380 RDT.3 RDT.2 381 RDT.7 RDT.6 382 RDT.11 RDT.10 383 RDT.15 ...

Page 9

ROM The ROM can address 6144 X 16 bits of program area from 000 to 17FF. 3.1. Vector Address Area (000 to 004) The program is sequentially executed. There is an area address 000 through 004 that is reserved ...

Page 10

Initial State 4.1. System Register State: Address Bit3 Bit2 00 IET0 IET1 01 IRQT0 IRQT1 02 T0S T0M.2 03 T0E T1M.2 04 T0L.3 T0L.2 05 T0H.3 T0H.2 06 T1L.3 T1L.2 07 T1H.3 T1H.2 08 PA.3 PA.2 09 PB.3 PB.2 ...

Page 11

System Register State: (continued) Address Bit3 Bit2 29 PPFCR.3 PPFCR.2 PPFCR.1 PPFCR.0 2A PPGCR.3 PPGCR.2 PPGCR.1 PPGCR.0 PPHCR.1 PPHCR.0 2C TV1.3 TV1.2 2D TG1EN TV1.6 2E TV2.3 TV2.2 2F TG2EN TV2.6 380 RDT.3 RDT.2 381 RDT.7 RDT.6 ...

Page 12

System Clock and Oscillator The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on-chip peripherals. System clock f /4. OSC 5.1. Instruction Cycle Time: (1) 4/32.768kHz ( 122.1 µ s) ...

Page 13

Capacitor Selection for Oscillator Ceramic Resonators Frequency C1 455kHz 47 - 100pF 3.58MHz - 4MHz - - The specified ceramic resonator has internal built-in load capacity Crystal Oscillator Frequency C1 32.768kHz 5 - 12.5pF 4MHz 8 - 15pF 8MHz 8 ...

Page 14

I/O Ports The MCU provides 29 bi-directional I/O ports. The PORT data put in register 08 - 0D, 22 - 23. The PORT control register (16 - 21) controls the PORT as input or output. Each I/O port has ...

Page 15

Equivalent Circuit for a Single I/O Pin Pull high Register I/O Control Register DATA Register READ DATA IN DATA READ In SH69P26, each output port contains a latch, which can hold the output data. Writing the port data register (PDR) ...

Page 16

Port Interrupt & CMP Interrupt The PORTF are used as external port interrupt sources. Since PORTF are bit programmable I/Os, only the voltage transition from V to GND applying to the digital input port can generate a external interrupt. The ...

Page 17

Timer 7.1. Timer0/Timer1 The device has three timers: two 8-bit timers (Timer0, Timer1) and one 16-bit timer (Timer2). The Timer0/Tiemr1 has the following features: - 8-bit up-counting timer/counter - Automatic re-load counter. - 8-level prescaler. - Interrupt on overflow ...

Page 18

External Clock/Event T0 as Timer0 Source When external clock/event T0 input as Timer0 source synchronized with the CPU system clock (System clock/4). The external source must follow certain constraints. The system clock samples it in instruction frame ...

Page 19

Timer2 Timer2 is a 16-bit timer, and it has the following features: - 16-bit up-counting timer/counter. - Automatic re-load counter. - 8-level prescaler. - Interrupt on overflow from FFFF to 0000. The following is a simplified Timer2 block diagram. ...

Page 20

Timer Mode In this mode, Timer2 is performed using the internal clock. The contents of the Timer2 counter register (384 - 387) are loaded into the up-counter while the highest nibble (387) has been written. The up-counter will start ...

Page 21

External Trigger Timer Mode In this mode, the counting is triggered by an external signal. This trigger is the edge of the ESS input. Either the rising or falling edge can be selected with the external trigger controlled by ...

Page 22

Count start ESS Internal clock Up-counter FF9C FF9D T2GO Timer2 INT Count start ESS Internal clock Up-counter F060 F061 T2GO Timer2 INT 7.2.7. Pulse Width Measurement Mode In this mode, Timer2 is performed using a special function under the timer ...

Page 23

In this mode, writing the Timer2 counter register (384 - 387) at any time cannot affect the up-counter operating anymore. In this mode, the pulse signal must follow certain constraints as in the external trigger timer mode. So, the limitation ...

Page 24

Four interrupt sources are available on SH69P26: - Timer0 interrupt - Timer1 interrupt - Timer2 interrupt - External interrupts (including PORTF interrupts, comparator interrupt) Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on 00 and ...

Page 25

Port Interrupts by Bit Only the digital input port can generate a port interrupt. The analog input cannot generate an interrupt request. System Register: Address Bit 3 Bit 2 390 PFIEN.3 PFIEN.2 392 PFIF.3 PFIF.2 System Register: Address Bit 3 ...

Page 26

Analog Comparator (CMP) Comparator includes 1 negative input, 6 positive inputs and 1 output. Each of them can be selected individually by comparator control register (CCR). When CMPEN is set to 1, the comparator enables. PORTE.1 input or internal ...

Page 27

Dual Tone Two Channel Tone is provided. They are the 12-bit pseudo random counter. To reduce power consumption, disable the sound effect generator during both STOP and HALT statuses. Tone Generator Control Register Address Bit 3 Bit 2 388 ...

Page 28

Music Table 1. Following is the music scale reference table for the Tone Generator channel 1(or channel 2) under OSC 4MHz. TGCR Ideal Note N (TGx.11 - TGx.0) freq 123.47 4050 02E C3 ...

Page 29

Music Table 2. Following is the music scale reference table for the Tone Generator channel 1(or channel 2) under OSC 2MHz. TGCR Ideal Note N (TGx.11 - TGx.0) freq 61.73 4050 2E C2 65.10 ...

Page 30

Low Voltage Reset (LVR) The LVR function is to monitor the supply voltage and generate an internal reset in the device typically used in AC line applications or large battery where large loads may be switched in ...

Page 31

Code Option OSC: 000: External Clock (default) 001: Internal RC Oscillator (2MHz) 010: Internal RC Oscillator (4MHz) 011: Internal RC Oscillator (6MHz) 100: External RC Oscillator (400kHz - 8MHz) 101: Ceramic Resonator (400kHz - 8MHz) 110: Crystal Oscillator (400kHz ...

Page 32

In System Programming Notice for OTP The In System Programming technology is valid for OTP chip. The Programming Interface of the OTP chip must be set on users application PCB, and users can assemble all components including the OTP chip ...

Page 33

Instruction Set All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. 1. Arithmetic and Logical Instruction 1.1 Accumulator Type Mnemonic Instruction Code ADC 00000 0bbb xxx xxxx ADCM 00000 1bbb ...

Page 34

Transfer Instruction Mnemonic Instruction Code LDA 00111 0bbb xxx xxxx STA 00111 1bbb xxx xxxx LDI X, I 01111 iiii xxx xxxx 3. Control Instruction Mnemonic Instruction Code BAZ X 10010 xxxx xxx ...

Page 35

Electrical Characteristics Absolute Maximum Ratings DC Supply Voltage . . . . . . . . . . . . . . . . . . . -0.3V to 7.0V Input Voltage . . . . . . . . ...

Page 36

AC Electrical Characteristics (V DD Parameter Symbol Instruction cycle time t CY T0/T2 input width t IW Input pulse width t IPW RESET pulse width t RESET WDT Period t WDT f/f Frequency Variation f/f Frequency Variation Analog Comparator Electrical ...

Page 37

Timing Waveform (a) System Clock Timing Waveform f OSC System Clock (b) T0/T2 Input Waveform T0/T2 input signal RC Oscillator Characteristics Graphs (for reference only) Typical RC Oscillator Resistor vs. Frequency (V 9.00 8.00 7.00 6.00 5.00 4.00 3.00 2.00 ...

Page 38

Application Circuit (For Reference Only) AP: SH69P26 has powerful drive ability, and it can drive LED directly. (1) Operating voltage: 5.0V (2) Oscillator: Crystal resonator 4MHz (3) PORTA Output 0.1u C2 0.1u C3 15p ...

Page 39

... Ordering Information Part No. SH69P26K SH69P26M SH69P26 Package 28L SKINNY 28L SOP 32L DIP 39 SH69P26 ...

Page 40

Package Information SKINNY 28-pin Outline Dimensions Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E 3. Dimension S includes end flash Dimensions in ...

Page 41

SOP (N.B.) 28L Outline Dimensions Seating Plane Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. 4. Dimension S includes ...

Page 42

P-DIP 32-pin Outline Dimensions Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E 3. Dimension S includes end flash Base Plane Seating Plane ...

Page 43

Data Sheet Revision History Version 2.2 Delete Bonding Diagram, Pad Location and update DC Electrical Characteristic 2.1 Package information update 2.0 Add reset pin share function (share as IO) 1.0 Original Content 43 SH69P26 Date Feb. 2008 Apr. 2007 Feb. ...

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